CN119486157A - Junction barrier schottky diode and preparation method thereof - Google Patents
Junction barrier schottky diode and preparation method thereof Download PDFInfo
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- CN119486157A CN119486157A CN202411611174.1A CN202411611174A CN119486157A CN 119486157 A CN119486157 A CN 119486157A CN 202411611174 A CN202411611174 A CN 202411611174A CN 119486157 A CN119486157 A CN 119486157A
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Abstract
The application provides a junction barrier Schottky diode and a preparation method thereof, wherein the junction barrier Schottky diode comprises a drift layer positioned at one side of a semiconductor substrate layer; the semiconductor substrate comprises a plurality of grooves, a first P-type doped region, an anode layer, a drift layer, an anode layer and a drift layer, wherein the grooves are arranged in the drift layer along a first direction, the grooves are arranged in the drift layer along the first direction, the first P-type doped region is arranged in the drift layer on one side of the grooves along the first direction and in the drift layer on one side of the grooves facing the semiconductor substrate, the anode layer is arranged on the inner wall of the grooves, the surface of the first P-type doped region on one side of the grooves facing away from the semiconductor substrate, and the surface of the drift layer between the adjacent grooves facing away from the semiconductor substrate, the first P-type doped region surrounds the anode layer on one side of the grooves along the first direction and part of the anode layer on the bottom wall of the grooves, and the first P-type doped region exposes the anode layer on the other side of the grooves along the other side of the first direction and the other part of the anode layer on the bottom wall of the grooves. And the anti-surge capability and the integration degree of the junction barrier Schottky diode are both improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a junction barrier Schottky diode and a preparation method thereof.
Background
Common power semiconductor structures include power diodes, vertical metal oxide semiconductor field effect transistors, or insulated gate bipolar transistors. Among them, the power diode is one of the most commonly used electronic components, is the most basic constituent unit of the power electronic circuit, and its unidirectional conductivity can be used for rectifying, clamping and freewheeling of the circuit. The diode in the peripheral circuit mainly plays a role in preventing the reverse action and prevents the damage of the device caused by reverse current filling. Conventional power diodes mainly include schottky power diodes (SBD) and PN junction power diodes. The schottky power diode forms a metal-semiconductor junction with a metal-to-semiconductor contact (gold-semiconductor contact) such that its forward turn-on voltage is small compared to a PN junction power diode. And schottky power diodes are a unipolar majority carrier conduction mechanism with a reverse recovery time of ideally zero, without accumulation of excess minority carriers. The Schottky power diode has the characteristics of low conduction voltage drop, good switching characteristics, small reverse recovery current and the like. However, schottky power diodes have poor reverse blocking characteristics and large leakage currents at high temperatures and high reverse voltages. The PN junction power diode has good reverse blocking characteristic, but has higher forward conduction voltage drop than the Schottky power diode, long reverse recovery time, large recovery current and larger energy consumption. The junction barrier Schottky diode (JunctionBarrier Schottky Diode, JBS) combines the Schottky power diode (SBD) and the PN junction power diode together, and the surface electric field of the Schottky contact area can be shielded by introducing the P-type area, so that higher reverse characteristic breakdown characteristic and forward surge performance can be realized.
Disclosure of Invention
The invention aims to solve the technical problem of improving the surge resistance and integration degree of a junction barrier Schottky diode.
In order to solve the technical problems, the invention provides a junction barrier Schottky diode which comprises a semiconductor substrate layer, a drift layer, a plurality of grooves, a first P-type doped region, an anode layer, a first P-type doped region and a drift layer, wherein the drift layer is arranged on one side of the semiconductor substrate layer, the grooves are arranged in the first direction, the grooves are arranged in parallel to the surface of the semiconductor substrate layer, the first P-type doped region is arranged in the drift layer on one side of the grooves along the first direction, the grooves are arranged in the drift layer on one side of the semiconductor substrate layer, the anode layer is arranged on the other side of the grooves along the first direction, the anode layer is exposed from the first P-type doped region, the anode layer is exposed from the inner wall of the grooves, the surface of the first P-type doped region is arranged on one side of the surface of the first P-type doped region is away from the semiconductor substrate layer, and the drift layer between the adjacent grooves is arranged on one side of the surface of the semiconductor substrate layer away from the semiconductor substrate layer, the anode layer is surrounded by the first P-type doped region.
Optionally, the size of the groove along the direction perpendicular to the semiconductor substrate layer is 0.5 micrometers to 3 micrometers.
Optionally, the dimension of the drift layer located between adjacent grooves and at the side of the first P-type doped region along the first direction is 0.5 to 2 micrometers.
Optionally, in a first direction, a portion of the first P-type doped region located on a side of the groove facing the semiconductor substrate layer has a first dimension, and in a direction perpendicular to the semiconductor substrate layer, a portion of the first P-type doped region located on a side of the groove along the first direction has a second dimension, wherein the second dimension is greater than the first dimension.
Optionally, the second dimension is 1.2 times to 2 times of the first dimension.
Optionally, the semiconductor substrate layer further comprises a second P-type doped region located in the drift layer, wherein the doping concentration of the second P-type doped region is smaller than that of the first P-type doped region, the second P-type doped region is located at one side of the first P-type doped region facing the semiconductor substrate layer and is in contact with the first P-type doped region, or the second P-type doped region is located at one side of the groove facing away from the first P-type doped region along the first direction and one side of the groove facing the semiconductor substrate layer, the second P-type doped region and the first P-type doped region respectively surround the anode layer of different areas of the bottom wall of the groove, and the distance from the second P-type doped region to the surface of one side of the drift layer facing away from the semiconductor substrate layer is larger than zero.
Optionally, the semiconductor substrate layer further comprises a current expansion region, wherein the current expansion region is positioned in the drift layer, the distance from the current expansion region to the surface of one side of the drift layer, which is away from the semiconductor substrate layer, is larger than zero, the doping concentration of the current expansion region is larger than the doping concentration of the drift layer, the first P-type doping region and the groove also extend into the current expansion region, and the current expansion region is arranged between the adjacent first P-type doping regions.
The application further provides a preparation method of the junction barrier Schottky diode, which comprises the steps of forming a drift layer on one side of a semiconductor substrate layer, forming a plurality of grooves which are distributed along a first direction, wherein the grooves extend into a part of the drift layer from one side surface of the drift layer, which is away from the semiconductor substrate layer, the first direction is parallel to the surface of the semiconductor substrate layer, a first P-type doped region is formed in the drift layer on one side of the grooves along the first direction and in the drift layer on one side of the grooves, which faces the semiconductor substrate layer, the inner wall of the grooves, the surface of the first P-type doped region, which faces away from the semiconductor substrate layer, and the surface of the drift layer, which faces away from the semiconductor substrate layer, between the adjacent grooves, wherein the first P-type doped region surrounds the anode layer on one side wall of the grooves along the first direction and one part of the anode layer on the bottom wall of the grooves, and the anode layer on the other side wall of the grooves, which the first P-type doped region exposes, and the anode layer on the other side of the grooves, which faces the other side of the anode layer.
Optionally, the process of forming the first P-type doped region includes an ion implantation process.
Optionally, before the anode layer is formed, a second P-type doped region is formed in the drift layer, the doping concentration of the second P-type doped region is smaller than that of the first P-type doped region, the second P-type doped region is located on one side of the first P-type doped region facing the semiconductor substrate layer and is in contact with the first P-type doped region, or the second P-type doped region is located on one side of the groove facing away from the first P-type doped region along the first direction and one side of the groove facing the semiconductor substrate layer, the second P-type doped region and the first P-type doped region respectively surround the anode layer in different regions of the bottom wall of the groove, and the distance from the second P-type doped region to the surface of the drift layer facing away from the semiconductor substrate layer is larger than zero.
Optionally, a current expansion region is formed in the drift layer, the distance from the current expansion region to the surface of one side of the drift layer, which faces away from the semiconductor substrate layer, is larger than zero, the doping concentration of the current expansion region is larger than that of the drift layer, the grooves also extend to the current expansion region after the grooves are formed, the first P-type doped region also extends to the current expansion region after the first P-type doped region is formed, and the current expansion region is arranged between the adjacent first P-type doped regions.
The technical scheme of the application has the following technical effects:
According to the junction barrier Schottky diode provided by the technical scheme of the invention, due to the arrangement of the groove, the depth of the first P-type doped region facing one side surface of the semiconductor substrate layer is deeper based on the existence of the groove, so that the first P-type doped region positioned at one side of the groove along the first direction is larger in size in the direction perpendicular to the semiconductor substrate layer, the contact area of the first P-type doped region and the drift layer is increased, more surge current and surge voltage are applied to the junction of the first P-type doped region and the drift layer in the surge process, the opening of a PN junction formed by the first P-type doped region and the drift layer is promoted, electrons in the drift layer are diffused into the first P-type doped region, the conductivity modulation is generated, the voltage in the surge process is limited to be further improved, the power consumption is limited to be increased, the failure probability of the junction barrier Schottky diode is reduced, and the surge resistance is improved. And secondly, the size of the first P-type doped region positioned at one side of the groove along the first direction is larger in the direction perpendicular to the semiconductor substrate layer, so that the size of the first P-type doped region positioned at one side of the groove towards the semiconductor substrate layer in the first direction is not influenced, the whole area of the junction barrier Schottky diode can not be increased, and the integration level is higher.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a junction barrier schottky diode in the related art;
FIG. 2 is a schematic diagram of a junction barrier Schottky diode according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a junction barrier Schottky diode in accordance with another embodiment of the present application;
fig. 4 is a schematic structural diagram of a junction barrier schottky diode according to another embodiment of the present application;
Fig. 5 is a schematic diagram of a junction barrier schottky diode according to another embodiment of the present application;
fig. 6 is a schematic diagram of a junction barrier schottky diode according to another embodiment of the present application;
Fig. 7 to 9 are block diagrams illustrating a junction barrier schottky diode manufacturing process according to an embodiment of the present application;
fig. 10 to 11 are block diagrams illustrating a fabrication process of a junction barrier schottky diode according to another embodiment of the present application;
Fig. 12 to 13 are block diagrams illustrating a fabrication process of a junction barrier schottky diode according to another embodiment of the present application;
fig. 14 to 17 are block diagrams illustrating a fabrication process of a junction barrier schottky diode according to another embodiment of the present application;
Fig. 18 to 19 are block diagrams illustrating a fabrication process of a junction barrier schottky diode according to another embodiment of the present application.
Detailed Description
The related art junction barrier schottky diode, referring to fig. 1, includes a semiconductor substrate layer 10, a drift layer 11 located at one side of the semiconductor substrate layer 10, a plurality of P-type doped layers F located in the drift layer 11 and arranged along a first direction X, the first direction X being parallel to a surface of the semiconductor substrate layer 10, and an anode layer 14 located at a side surface of the P-type doped layers F facing away from the semiconductor substrate layer 10 and a side surface of the drift layer 11 between adjacent P-type doped layers F facing away from the semiconductor substrate layer 10.
In fig. 1, the width of one part of the P-type doped layer 13b along the first direction X is greater than the width of the other part of the P-type doped layer 13a along the first direction X, so that the contact area between the P-type doped layer 13b and the drift layer 11 is larger, more surge current and surge voltage are applied to the junction between the P-type doped layer and the drift layer 11 in the process of surge, the opening of a PN junction formed by the P-type doped layer 13b and the drift layer 11 is promoted, holes in the P-type doped layer 13b are diffused into the drift layer, electrons in the drift layer 11 are diffused into the P-type doped layer 13b, conductivity modulation is generated, further voltage improvement in the process of surge is limited, power consumption increase is limited, the probability of failure of the junction barrier schottky diode is reduced, and the anti-surge capability is improved.
However, since the width of the P-type doped layer 13b in the first direction X becomes large, the area of the entire junction barrier schottky diode increases and the integration level decreases.
On the basis, the application provides the junction barrier Schottky diode and the preparation method thereof, and the surge resistance and the integration degree of the junction barrier Schottky diode are both improved.
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intermediate medium, and in communication with each other between two elements, and wirelessly connected, or wired. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
An embodiment of the present application proposes a junction barrier schottky diode, referring to fig. 2, comprising:
a semiconductor substrate layer 100;
a drift layer 110 located on one side of the semiconductor substrate layer 100;
A plurality of grooves 120 located in the drift layer 110 and arranged along a first direction X, the first direction X being parallel to the surface of the semiconductor substrate layer 100;
A first P-type doped region 130 located in the drift layer 110 on the side of the recess 120 along the first direction X and in the drift layer 110 on the side of the recess 120 toward the semiconductor substrate layer 100;
an anode layer 140, located on the inner wall of the recess 120, on the surface of the first P-type doped region 130 facing away from the semiconductor substrate layer 100, and on the surface of the drift layer 110 between adjacent recesses 120 facing away from the semiconductor substrate layer 100;
The first P-doped region 130 surrounds the anode layer 140 on one side of the groove 120 along the first direction X and a portion of the anode layer 140 on the bottom wall of the groove 120, and the first P-doped region 130 exposes the anode layer 140 on the other side of the groove 120 along the first direction X and another portion of the anode layer 140 on the bottom wall of the groove 120.
In this embodiment, due to the provision of the recess 120, the depth of the first P-type doped region 130 facing the surface of the semiconductor substrate layer 100 is deeper based on the presence of the recess 120, so that the first P-type doped region 130 located at one side of the recess 120 along the first direction X has a larger dimension in the direction perpendicular to the semiconductor substrate layer 100, which increases the contact area between the first P-type doped region 130 and the drift layer 110, and in the process of surging, more surge current and surge voltage are applied to the junction between the first P-type doped region 130 and the drift layer 110, so as to promote the opening of the PN junction formed by the first P-type doped region 130 and the drift layer 110, promote the hole in the first P-type doped region 130 to diffuse into the drift layer 110, and the electrons in the drift layer 110 diffuse into the first P-type doped region 130, thereby generating conductivity modulation, limiting further increase of voltage in the surging process, limiting the increase of power consumption, reducing the probability of failure of the junction schottky diode, and improving the anti-surge capability. Second, since the first P-type doped region 130 located at the side of the recess 120 along the first direction X has a larger size in the direction perpendicular to the semiconductor substrate layer 100, the size of the first P-type doped region 130 located at the side of the recess 120 facing the semiconductor substrate layer 100 in the first direction X is not affected, so that the overall area of the junction barrier schottky diode can be not increased, and the integration level is high.
The first P-type doped region 130 is in contact with the anode layer 140 of the sidewall of the recess 120 along the first direction X and a portion of the anode layer 140 of the bottom wall of the recess 120.
The first P-type doped region 130 exposes the anode layer 140 of the sidewall of the groove 120 along the other side of the first direction X and another portion of the anode layer 140 of the bottom wall of the groove 120, which means that the first P-type doped region 130 does not surround the anode layer 140 of the sidewall of the groove 120 along the other side of the first direction X and another portion of the anode layer 140 of the bottom wall of the groove 120, and the first P-type doped region 130 is not in contact with the anode layer 140 of the sidewall of the groove 120 along the other side of the first direction X and is not in contact with another portion of the anode layer 140 of the bottom wall of the groove 120.
Preferably, a portion of the anode layer 140 of the first P-type doped region 130 surrounding the bottom wall of the recess 120 has a dimension in the first direction X that is greater than 1/2 of the dimension of the recess 120 in the first direction X. Increasing reverse blocking capability.
In this embodiment, a new generation of SiC-based semiconductor power devices represented by SiC has higher reverse withstand voltage capability, lower forward conduction loss, faster switching frequency, and stronger environmental withstand capability than Si-based semiconductor power devices, and is therefore considered as a new hope in the field of electric energy conversion. In this embodiment, the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. In one embodiment, the conductive ions in the semiconductor substrate layer 100 are N-type ions. In other embodiments, the conductivity type of the semiconductor substrate layer 100 is not limited.
In one embodiment, the conductivity type of the drift layer 110 is the same as the conductivity type of the semiconductor substrate layer 100, and the doping concentration of the drift layer 110 is less than the doping concentration of the semiconductor substrate layer 100. In one embodiment, the material of the drift layer 110 is silicon carbide doped with N-type conductive ions. The N-type conductive ions may be phosphorus ions or nitrogen ions.
The first P-type doped region 130 has a conductivity type opposite to that of the drift layer 110, and illustratively, the drift layer 110 has an N-type conductivity and the first P-type doped region 130 has a P-type conductivity.
If the size of the recess 120 along the direction perpendicular to the semiconductor substrate layer 100 is too large, the difficulty of implementation in the process increases, the cost increases, the distance between the recess 120 and the semiconductor substrate layer 100 becomes small, and the area of forward conduction current of the semiconductor power device decreases, which is unfavorable for the decrease of forward on-resistance. If the size of the recess 120 in the direction perpendicular to the semiconductor substrate layer 100 is too small, the degree of increase in the size of the first P-type doped region 130 in the direction perpendicular to the semiconductor substrate layer 100 is limited, and the degree of improvement in the anti-surge capability is limited. Thus, in one embodiment, the dimension of the recess 120 along a direction perpendicular to the semiconductor substrate layer 100 is 0.5 microns to 3 microns, such as 0.5 microns, 1 micron, 1.5 microns, 2 microns, 2.5 microns, or 3 microns.
If the size of the drift layer 100 located between the adjacent grooves 120 and located at the side of the first P-type doped region 130 in the first direction X is too small, the forward conduction performance is affected, and if the size of the drift layer 100 located between the adjacent grooves 120 and located at the side of the first P-type doped region 130 in the first direction X is too large, the pinch-off performance in the reverse withstand voltage process is affected. Thus, in one embodiment, the drift layer 100 between adjacent ones of the recesses 120 and laterally of the first P-type doped region 130 has a dimension in the first direction X of 0.5 microns to 2 microns, such as 0.5 microns, 1 micron, 1.5 microns, or 2 microns.
In one embodiment, the portion of the first P-type doped region 130 on the side of the recess 120 facing the semiconductor substrate layer 100 has a first dimension in the first direction X, and the portion of the first P-type doped region 130 on the side of the recess 120 in the first direction X has a second dimension in the direction perpendicular to the semiconductor substrate layer 100, the second dimension being greater than the first dimension. Preferably, the second dimension is 1.2 to 2 times, e.g. 1.2, 1.5, 1.8 or 2 times, the first dimension.
Another embodiment of the present application further provides a junction barrier schottky diode, referring to fig. 3, where the junction barrier schottky diode of the present embodiment is different from the junction barrier schottky diode of fig. 2 in that the junction barrier schottky diode further includes a second P-type doped region 150 located in the drift layer 110, and the second P-type doped region 150 is located at a side of the first P-type doped region 130 facing the semiconductor substrate layer 110 and is in contact with the first P-type doped region 130, and a doping concentration of the second P-type doped region 150 is less than a doping concentration of the first P-type doped region 130.
Since the second P-type doped region 150 is disposed, the PN junction of the drift layer 110 and the integrated structure formed by the first P-type doped region 130 and the second P-type doped region 150 shifts the electric field peak toward the semiconductor substrate layer 100, thereby enhancing the protection of the vicinity of the inner wall of the recess 120.
Preferably, the doping concentration of the first P-type doped region 130 is 1E18atom/cm 3～1E19atom/cm3, and the doping concentration of the second P-type doped region 150 is 3E16atom/cm 3～1E17atom/cm3.
Another embodiment of the present application further provides a junction barrier schottky diode, referring to fig. 4, where the junction barrier schottky diode of the present embodiment is different from the junction barrier schottky diode of fig. 2 in that the junction barrier schottky diode further includes a second P-type doped region 151 located in the drift layer 110, wherein the second P-type doped region 151 is located at a side of the recess 120 facing away from the first P-type doped region 130 along the first direction X and a side of the recess 120 facing toward the semiconductor substrate layer 100, the second P-type doped region 130 and the first P-type doped region 130 respectively surround the anode layer 140 of different regions of the bottom wall of the recess 120, the second P-type doped region 151 is in contact with the first P-type doped region 130, a distance from the second P-type doped region 151 to a surface of the drift layer 110 facing away from the semiconductor substrate layer 100 is greater than zero, and a doping concentration of the second P-type doped region 151 is less than a doping concentration of the first P-type doped region 130.
The second P-type doped region 151 has a low doping concentration, so that the degree of depletion of the drift layer 110 between the second P-type doped region 151 surrounding the anode layer of the inner wall of one recess 120 and the first P-type doped region 130 surrounding the anode layer of the inner wall of the adjacent recess 120 is reduced in favor of the reduction of the forward on-resistance in the absence of a voltage. In the absence of applied voltage, the drift layer 110 between the second P-type doped region 151 of the anode layer surrounding the inner wall of one recess 120 and the first P-type doped region 130 of the anode layer surrounding the inner wall of an adjacent recess 120 is prevented from being pinched off.
Preferably, the doping concentration of the first P-type doped region 130 is 1E18atom/cm 3～1E19atom/cm3, and the doping concentration of the second P-type doped region 151 is 3E16atom/cm 3～1E17atom/cm3.
Another embodiment of the present application further provides a junction barrier schottky diode, referring to fig. 5, where the junction barrier schottky diode of the present embodiment is different from the junction barrier schottky diode of fig. 4 in that the junction barrier schottky diode further includes a current expansion region 160 located in the drift layer 110, a distance from the current expansion region 160 to a surface of the drift layer 110 on a side facing away from the semiconductor substrate layer 100 is greater than zero, and a doping concentration of the current expansion region 160 is greater than a doping concentration of the drift layer 110. The first P-doped regions 130 and the grooves 120 further extend into the current expansion regions 160, and the current expansion regions 160 are disposed between adjacent first P-doped regions 130. The second P-type doped region 151 also extends into the current spreading region 160. For any adjacent two of the recesses 120, there is a current spreading region 160 between the second P-type doped region 151 of the anode layer 140 surrounding the inner wall of one recess 120 and the first P-type doped region 130 of the anode layer 140 comprising the inner wall of the other recess 120.
Another embodiment of the present application further provides a junction barrier schottky diode, referring to fig. 6, where the junction barrier schottky diode of the present embodiment is different from the junction barrier schottky diode of fig. 3 in that the junction barrier schottky diode further includes a current expansion region 160 located in the drift layer 110, a distance from the current expansion region 160 to a surface of the drift layer 110 on a side facing away from the semiconductor substrate layer 100 is greater than zero, and a doping concentration of the current expansion region 160 is greater than a doping concentration of the drift layer 110. The first P-doped regions 130 and the grooves 120 further extend into the current expansion regions 160, and the current expansion regions 160 are disposed between adjacent first P-doped regions 130. A current spreading region 160 is provided between adjacent second P-type doped regions 150.
Another embodiment of the present application further provides a method for manufacturing a junction barrier schottky diode, and the manufacturing process of the junction barrier schottky diode of this embodiment is described in detail with reference to fig. 7 to 9.
Referring to fig. 7, a drift layer 110 is formed on one side of a semiconductor substrate layer 100, a plurality of grooves 120 arranged in a first direction X are formed, the grooves 120 extending from a surface of one side of the drift layer 110 facing away from the semiconductor substrate layer 100 into a portion of the drift layer 110, the first direction X being parallel to the surface of the semiconductor substrate layer 100.
In one embodiment, the process of forming the recess 120 is an etching process.
Referring to fig. 8, a first P-type doped region 130 is formed in the drift layer 110 on the side of the recess 120 along the first direction X and in the drift layer 110 on the side of the recess 120 toward the semiconductor substrate layer 100.
The process of forming the first P-type doped region 130 includes an ion implantation process.
Referring to fig. 9, an anode layer 140 is formed on the inner wall of the recess 120, the surface of the first P-type doped region 130 on the side facing away from the semiconductor substrate layer 100, and the surface of the drift layer 110 between adjacent recesses 120 on the side facing away from the semiconductor substrate layer 100.
The first P-doped region 130 surrounds the anode layer 140 on one side of the groove 120 along the first direction X and a portion of the anode layer 140 on the bottom wall of the groove 120, and the first P-doped region 130 exposes the anode layer 140 on the other side of the groove 120 along the first direction X and another portion of the anode layer 140 on the bottom wall of the groove 120.
Another embodiment of the present application further provides a method for manufacturing a junction barrier schottky diode, and the manufacturing process of the junction barrier schottky diode of this embodiment is described in detail with reference to fig. 10 to 11.
Referring to fig. 10, fig. 10 is a schematic diagram based on fig. 8, a second P-type doped region 150 is formed in the drift layer 110, the second P-type doped region 150 is located at a side of the first P-type doped region 130 facing the semiconductor substrate layer 100 and is in contact with the first P-type doped region 130, and the doping concentration of the second P-type doped region 150 is smaller than that of the first P-type doped region 130.
The process of forming the second P-type doped region 150 includes an ion implantation process.
Referring to fig. 11, an anode layer 140 is formed on the inner wall of the recess 120, the surface of the first P-type doped region 130 on the side facing away from the semiconductor substrate layer 100, and the surface of the drift layer 110 between adjacent recesses 120 on the side facing away from the semiconductor substrate layer 100.
Another embodiment of the present application further provides a method for manufacturing a junction barrier schottky diode, and the manufacturing process of the junction barrier schottky diode of this embodiment is described in detail with reference to fig. 12 to 13.
Referring to fig. 12, fig. 12 is a schematic diagram based on fig. 8, a second P-type doped region 151 is formed in the drift layer 110, the second P-type doped region 151 is located on a side of the recess 120 facing away from the first P-type doped region 130 along the first direction X and a side of the recess 120 facing toward the semiconductor substrate layer 100, the second P-type doped region 130 and the first P-type doped region 130 respectively surround the anode layer 140 of different regions of the bottom wall of the recess 120, the second P-type doped region 151 is in contact with the first P-type doped region 130, a distance from the second P-type doped region 151 to a surface of the drift layer 110 facing away from the semiconductor substrate layer 100 is greater than zero, and a doping concentration of the second P-type doped region 151 is smaller than that of the first P-type doped region 130.
The process of forming the second P-type doped region 151 includes an ion implantation process.
Referring to fig. 13, an anode layer 140 is formed on the inner wall of the recess 120, the surface of the first P-type doped region 130 on the side facing away from the semiconductor substrate layer 100, and the surface of the drift layer 110 between adjacent recesses 120 on the side facing away from the semiconductor substrate layer 100.
Another embodiment of the present application further provides a method for manufacturing a junction barrier schottky diode, and the manufacturing process of the junction barrier schottky diode of this embodiment is described in detail with reference to fig. 14 to 17.
Referring to fig. 14, a drift layer 110 is formed on one side of a semiconductor substrate layer 100, a current expansion region 160 is formed in the drift layer, a distance from the current expansion region 160 to a surface of the drift layer 110 on one side facing away from the semiconductor substrate layer 100 is greater than zero, and a doping concentration of the current expansion region 160 is greater than a doping concentration of the drift layer 110.
The process of forming the current spreading region 160 includes an ion implantation process.
Referring to fig. 15, a plurality of grooves 120 are formed to be arranged in a first direction X, the grooves 120 extending from a side surface of the drift layer 110 facing away from the semiconductor substrate layer 100 into a portion of the drift layer 110, the first direction X being parallel to the surface of the semiconductor substrate layer 100.
In one embodiment, the process of forming the recess 120 is an etching process.
After forming the recess, the recess also extends to the current spreading region.
Referring to fig. 16, a first P-type doped region 130 is formed in the drift layer 110 on the side of the recess 120 along the first direction X and in the drift layer 110 on the side of the recess 120 toward the semiconductor substrate layer 100.
The process of forming the first P-type doped region 130 includes an ion implantation process.
After the first P-type doped region 130 is formed, the first P-type doped region 130 also extends into the current expansion region, with the current expansion region 160 between adjacent first P-type doped regions 130.
In this embodiment, the second P-type doped region 151 is formed in the drift layer 110, the second P-type doped region 151 is located at one side of the recess 120 facing away from the first P-type doped region 130 along the first direction X and one side of the recess 120 facing toward the semiconductor substrate layer 100, the second P-type doped region 130 and the first P-type doped region 130 respectively surround the anode layer 140 of different regions of the bottom wall of the recess 120, the second P-type doped region 151 is in contact with the first P-type doped region 130, the distance from the second P-type doped region 151 to the surface of the drift layer 110 facing away from the semiconductor substrate layer 100 is greater than zero, and the doping concentration of the second P-type doped region 151 is smaller than that of the first P-type doped region 130. It should be noted that, in other embodiments, the second P-type doped region may not be formed.
Referring to fig. 17, an anode layer 140 is formed on the inner wall of the recess 120, the surface of the first P-type doped region 130 on the side facing away from the semiconductor substrate layer 100, and the surface of the drift layer 110 between adjacent recesses 120 on the side facing away from the semiconductor substrate layer 100.
The second P-type doped region 151 also extends into the current spreading region 160. For any adjacent two of the recesses 120, there is a current spreading region 160 between the second P-type doped region 151 of the anode layer 140 surrounding the inner wall of one recess 120 and the first P-type doped region 130 of the anode layer 140 comprising the inner wall of the other recess 120.
Another embodiment of the present application further provides a method for manufacturing a junction barrier schottky diode, and the manufacturing process of the junction barrier schottky diode of this embodiment is described in detail with reference to fig. 18 to 19.
Referring to fig. 18, fig. 18 is a schematic view based on fig. 15, in which a first P-type doped region 130 is formed in the drift layer 110 on the side of the recess 120 along the first direction X and in the drift layer 110 on the side of the recess 120 toward the semiconductor substrate layer 100.
The process of forming the first P-type doped region 130 includes an ion implantation process.
After the first P-type doped region 130 is formed, the first P-type doped region 130 also extends into the current extension region 160, with the current extension region 160 between adjacent first P-type doped regions 130.
In this embodiment, the second P-type doped region 150 is formed in the drift layer 110, the second P-type doped region 150 is located on the side of the first P-type doped region 130 facing the semiconductor substrate layer 100 and is in contact with the first P-type doped region 130, and the doping concentration of the second P-type doped region 150 is smaller than that of the first P-type doped region 130. A current spreading region 160 is provided between adjacent second P-type doped regions 150.
It should be noted that, in other embodiments, the second P-type doped region 150 may not be formed.
Referring to fig. 19, an anode layer 140 is formed on the inner wall of the recess 120, the surface of the first P-type doped region 130 on the side facing away from the semiconductor substrate layer 100, and the surface of the drift layer 110 between adjacent recesses 120 on the side facing away from the semiconductor substrate layer 100.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (10)
1. A junction barrier schottky diode which comprises a semiconductor substrate, characterized by comprising the following steps:
a semiconductor substrate layer;
a drift layer located on one side of the semiconductor substrate layer;
A plurality of grooves in the drift layer arranged in a first direction, the first direction being parallel to a surface of the semiconductor substrate layer;
A first P-type doped region located in the drift layer on one side of the recess along the first direction and in the drift layer on one side of the recess toward the semiconductor substrate layer;
The anode layer is positioned on the inner wall of the groove, the surface of one side of the first P-type doped region, which is away from the semiconductor substrate layer, and the surface of one side of the drift layer, which is between the adjacent grooves, which is away from the semiconductor substrate layer;
The first P-type doped region surrounds the anode layer of the side wall of the groove along the first direction and part of the anode layer of the bottom wall of the groove, and exposes the anode layer of the side wall of the groove along the other side of the first direction and the other part of the anode layer of the bottom wall of the groove.
2. The junction barrier schottky diode of claim 1 wherein the recess has a dimension in a direction perpendicular to the semiconductor substrate layer of 0.5-3 microns.
3. The junction barrier schottky diode of claim 1 wherein the dimension of the drift layer between adjacent ones of the recesses and laterally of the first P-type doped region along the first direction is 0.5 to 2 microns.
4. The junction barrier schottky diode of claim 1 wherein the portion of the first P-type doped region on the side of the recess facing the semiconductor substrate layer has a first dimension in a first direction; in the direction perpendicular to the semiconductor substrate layer, the dimension of the part of the first P-type doped region, which is positioned at one side of the groove along the first direction, is a second dimension, and the second dimension is larger than the first dimension;
preferably, the second dimension is 1.2 times to 2 times of the first dimension.
5. The junction barrier Schottky diode of claim 1, further comprising a second P-type doped region in said drift layer, said second P-type doped region having a doping concentration less than a doping concentration of said first P-type doped region;
The second P-type doped region is positioned at one side of the first P-type doped region facing the semiconductor substrate layer and is in contact with the first P-type doped region, or the second P-type doped region is positioned at one side of the groove facing away from the first P-type doped region along the first direction and one side of the groove facing the semiconductor substrate layer, the second P-type doped region and the first P-type doped region respectively surround the anode layer of different areas of the bottom wall of the groove, the second P-type doped region is in contact with the first P-type doped region, and the distance from the second P-type doped region to the surface of the drift layer facing away from one side of the semiconductor substrate layer is larger than zero.
6. The junction barrier Schottky diode of claim 1, further comprising a current extension region in said drift layer, wherein a distance from said current extension region to a side surface of said drift layer facing away from said semiconductor substrate layer is greater than zero, and wherein a doping concentration of said current extension region is greater than a doping concentration of said drift layer;
The first P-type doped region and the groove also extend into the current expansion region, and the current expansion region is arranged between the adjacent first P-type doped regions.
7. The preparation method of the junction barrier Schottky diode is characterized by comprising the following steps of:
Forming a drift layer on one side of the semiconductor substrate layer;
Forming a plurality of grooves arranged along a first direction, wherein the grooves extend into a part of the drift layer from one side surface of the drift layer, which faces away from the semiconductor substrate layer, and the first direction is parallel to the surface of the semiconductor substrate layer;
Forming a first P-type doped region in the drift layer on one side of the groove along the first direction and in the drift layer on one side of the groove towards the semiconductor substrate layer;
Forming an anode layer on the inner wall of the groove, the surface of one side of the first P-type doped region, which is away from the semiconductor substrate layer, and the surface of one side of the drift layer between the adjacent grooves, which is away from the semiconductor substrate layer;
The first P-type doped region surrounds the anode layer of the side wall of the groove along the first direction and part of the anode layer of the bottom wall of the groove, and exposes the anode layer of the side wall of the groove along the other side of the first direction and the other part of the anode layer of the bottom wall of the groove.
8. The method of claim 7, wherein the process of forming the first P-type doped region comprises an ion implantation process.
9. The method of manufacturing a junction barrier Schottky diode of claim 7, further comprising forming a second P-type doped region in said drift layer prior to forming said anode layer, said second P-type doped region having a doping concentration less than a doping concentration of said first P-type doped region;
The second P-type doped region is positioned at one side of the first P-type doped region facing the semiconductor substrate layer and is in contact with the first P-type doped region, or the second P-type doped region is positioned at one side of the groove facing away from the first P-type doped region along the first direction and one side of the groove facing the semiconductor substrate layer, the second P-type doped region and the first P-type doped region respectively surround the anode layer of different areas of the bottom wall of the groove, the second P-type doped region is in contact with the first P-type doped region, and the distance from the second P-type doped region to the surface of the drift layer facing away from one side of the semiconductor substrate layer is larger than zero.
10. The method of manufacturing a junction barrier Schottky diode of claim 7, further comprising forming a current extension region in the drift layer, wherein a distance from the current extension region to a surface of the drift layer on a side away from the semiconductor substrate layer is greater than zero, and wherein a doping concentration of the current extension region is greater than a doping concentration of the drift layer;
after forming the recess, the recess also extends to the current spreading region;
after the first P-type doped region is formed, the first P-type doped region also extends into the current expansion region, and the current expansion region is arranged between adjacent first P-type doped regions.
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| CN202411611174.1A CN119486157A (en) | 2024-11-12 | 2024-11-12 | Junction barrier schottky diode and preparation method thereof |
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