CN119484439A - Multicast message duplication method, switching chip, storage medium and electronic device - Google Patents
Multicast message duplication method, switching chip, storage medium and electronic device Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/201—Multicast operation; Broadcast operation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9057—Arrangements for supporting packet reassembly or resequencing
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Abstract
The embodiment of the invention provides a replication method, a switching chip, a storage medium and an electronic device of a multicast message. The method comprises the steps of receiving and caching multicast messages to be replicated, wherein the multicast messages to be replicated comprise packet descriptors of the multicast messages to be replicated and loads of the multicast messages to be replicated, obtaining N target packet descriptors by obtaining and replicating the packet descriptors of the multicast messages to be replicated, scheduling the N target packet descriptors, obtaining the cached loads of the multicast messages to be replicated when each scheduled target packet descriptor to be sent is sent, splicing the target packet descriptors to be sent with the loads, obtaining target multicast messages and sending the target multicast messages. The method solves the problem that more cache capacity is needed to store the copied multicast messages when the exchange chip copies the multicast messages, and further achieves the technical effect of reducing the cache capacity in the exchange chip.
Description
Technical Field
The embodiment of the invention relates to the field of communication, in particular to a replication method, a switching chip, a storage medium and an electronic device of multicast messages.
Background
The multicast technology is a network communication technology of one transmitting end corresponding to a plurality of receiving ends, and with the wide development of applications such as streaming media, video conferences and the like, the multicast technology plays an important role in improving network efficiency, bandwidth utilization rate and user experience, and the application of the multicast technology is also becoming wider. Therefore, the multicast performance also becomes an important performance index of the switch forwarding system, especially the ethernet switch chip as the core of the switch system, and the multicast performance is very important.
In multicast implementation, an original multicast message enters a switching chip through an incoming port to which the original multicast message is connected, copies the original multicast message into multiple copies in the switching chip, and then the original multicast message is sent out from at least one or more outgoing ports, and in the process, one copy of the original multicast message is copied into multiple copies. Because multiple messages are generated by the copying process, bandwidth expansion exists in the chip, and larger burst traffic exists. As shown in fig. 1, after the original multicast message with 10Gbps of traffic is replicated to 32 copies, the average flow rate of the internal bandwidth is expanded to 320Gbps in a longer unit time, but the specific replication process is seen in a smaller unit time, and the traffic in a short time is far greater than 320Gbps, which is called traffic burst. Short-time flow bursts of messages require higher working frequency for the switching chip, increase the requirements on chip design, and increase more caches to accommodate the burst of messages. For the outgoing port, the packet with large burst flow is very easy to cause port congestion to cause packet loss, so that the network is unstable and has large jitter, and further, the network service quality (Quality of Service, abbreviated as QoS) is adversely affected.
In the prior art, to solve the above-mentioned problems, a leaky bucket algorithm or a token bucket algorithm has been developed to limit the traffic to the output port. The methods optimize the congestion processing strategy of the port, and back pressure or discard the message entering the port, thereby improving the influence of network jitter. However, these methods can limit the output flow forcibly, and the capacity requirement of the buffer memory is further increased to accommodate more duplicate messages, so as to reduce the occurrence of port congestion, but these methods still have the phenomenon of discarding messages, thereby affecting the QoS. And unnecessary packet discarding is a waste of the replication performance of the chip multicast packet.
Aiming at the problem that in the related art, more cache capacity is needed to store the copied multicast message when the exchange chip copies the multicast message, no effective solution is proposed at present.
Disclosure of Invention
The embodiment of the invention provides a multicast message copying method, a switching chip, a storage medium and an electronic device, which are used for at least solving the problem that more cache capacity is needed to store a copied multicast message when the switching chip copies the multicast message in the related technology.
According to one embodiment of the invention, a replication method of multicast messages is provided, which comprises the steps of receiving and caching multicast messages to be replicated, wherein the multicast messages to be replicated comprise packet descriptors of the multicast messages to be replicated and loads of the multicast messages to be replicated, obtaining N target packet descriptors by obtaining the packet descriptors of the multicast messages to be replicated, wherein the similarity between each target packet descriptor in the N target packet descriptors and the packet descriptor is greater than a preset threshold value, scheduling the N target packet descriptors, obtaining the loads of the cached multicast messages to be replicated when each target packet descriptor to be sent after scheduling is sent, splicing the target packet descriptors to be sent with the loads, obtaining a target multicast message, and sending the target multicast message.
In an exemplary embodiment, the packet descriptor carries a replication index related to a multicast address of the multicast packet to be replicated, where replicating the packet descriptor of the multicast packet to be replicated includes determining N port identifiers corresponding to the replication index from a multicast member table, where the multicast member table has a set of port identifiers corresponding to different replication indexes, the N target multicast packets are sent through N ports corresponding to the N port identifiers, replicating the packet descriptor N-1 times to obtain N packet descriptors, and obtaining an i target packet descriptor to obtain the N target packet descriptors, where i is an integer greater than or equal to 1 and less than or equal to N, and replacing the replication index in the i target packet descriptor in the N packet descriptors with the i port identifier in the N port identifiers to obtain the i target packet descriptor.
In one exemplary embodiment, caching the multicast message to be replicated includes caching a payload of the multicast message to be replicated in a first storage module and caching a packet descriptor of the multicast message to be replicated in a second storage module.
In an exemplary embodiment, caching the multicast message to be replicated includes caching a load of the multicast message to be replicated, writing a cache address of the load of the multicast message to be replicated into a packet descriptor of the multicast message to be replicated, and splicing the target packet descriptor to be sent with the load, including acquiring the load of the multicast message to be replicated from the cache address carried by the target packet descriptor to be sent, and splicing the target packet descriptor to be sent with the load of the multicast message to be replicated.
In an exemplary embodiment, after the packet descriptors of the multicast packet to be copied are copied, the method further includes storing the obtained N target packet descriptors in one or more queues, and scheduling the N target packet descriptors, including sending the N target packet descriptors stored in the one or more queues to a processing module according to a scheduling result, where the processing module executes the steps of obtaining the cached load of the multicast packet to be copied, splicing the target packet descriptors to be sent with the load, obtaining a target multicast packet, and sending the target multicast packet.
In an exemplary embodiment, the processing module is configured to send the target multicast packet to a port corresponding to the target multicast packet according to the scheduling result.
In an exemplary embodiment, the steps of copying the packet descriptors of the multicast packet to be copied and storing the obtained N destination packet descriptors in one or more queues are performed by a copying engine, and the step of scheduling the N destination packet descriptors is performed by a scheduler, where the copying engine, the scheduler, and the processing module are located in a switch chip, and the switch chip is configured to copy and send the multicast packet.
In an exemplary embodiment, the N target packet descriptors stored in the one or more queues are respectively sent to a processing module according to a scheduling result, wherein the scheduling result comprises a sending time interval of each target packet descriptor sent to the processing module, corresponding target packet descriptors are obtained from the one or more queues according to the scheduling result, and the target packet descriptors are sent to the processing module.
In an exemplary embodiment, determining the scheduling result of the N target packet descriptors includes determining a receiving time interval for receiving two adjacent multicast messages to be replicated, determining an average replication number of packet descriptors, wherein the average replication number is an average number of target packet descriptors obtained after replication of the packet descriptors, and dividing the receiving time interval by the average replication number to obtain a sending time interval of each target packet descriptor.
In an exemplary embodiment, determining a receiving time interval for receiving two adjacent multicast messages to be replicated includes determining a primary frequency of a switch chip, and determining a packet forwarding rate of the multicast messages to be replicated, where the packet forwarding rate is used to indicate a number of data packets transmitted by the switch chip in a unit time, and the switch chip is used to replicate and send the multicast messages, and dividing the primary frequency of the switch chip by the packet forwarding rate to obtain the receiving time interval.
In an exemplary embodiment, determining the packet forwarding rate of the multicast packet to be replicated includes determining a first average traffic of the multicast packet to be replicated and a packet size of the multicast packet to be replicated, and dividing the first average traffic by the packet size to obtain the packet forwarding rate of the multicast packet to be replicated.
In an exemplary embodiment, determining the average copy number of the packet descriptor includes determining a first average traffic of the multicast message to be copied and a second average traffic of the multicast message after being copied, and dividing the second average traffic by the first average traffic to obtain the average copy number of the packet descriptor.
In an exemplary embodiment, determining the scheduling result of the N target packet descriptors includes obtaining a primary frequency and a target data bit width of a switching chip, and obtaining a start rate and a step rate for transmitting the target packet descriptors to the processing module, where the target data bit width is a data bit width of a multicast packet copied and transmitted by the switching chip, and the switching chip is used to copy and transmit the multicast packet, determining a remaining capacity of a memory in the processing module when determining a transmission time interval of each target packet descriptor, and determining a transmission time interval of the target packet descriptors according to the remaining capacity of the memory, the primary frequency, the target data bit width, the start rate, and the step rate.
In an exemplary embodiment, determining the transmission time interval of the target packet descriptor according to the remaining capacity of the memory, the primary frequency, the target data bit width, the start rate and the step rate includes calculating the transmission time interval by the following formula, t=f/(fi+fstep) r, where t is the transmission time interval, f is the primary frequency, W is the target data bit width, fi is the start rate, fstep is the step rate, r is a group play big factor, and d is the remaining capacity of the memory.
According to one embodiment of the invention, a switching chip is provided, which comprises a first storage module, a replication engine and a processing module, wherein the first storage module is used for caching the load of a received multicast message to be replicated, the multicast message to be replicated comprises a packet descriptor of the multicast message to be replicated and the load of the multicast message to be replicated, the replication engine is used for acquiring and replicating the packet descriptor of the multicast message to be replicated to obtain N target packet descriptors, the scheduler is used for scheduling the N target packet descriptors, and the processing module is used for acquiring the cached load of the multicast message to be replicated when each scheduled target packet descriptor to be sent is sent, and splicing the target packet descriptor to be sent with the load to obtain a target multicast message and sending the target multicast message.
According to a further embodiment of the invention, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.
According to a further embodiment of the invention, there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
According to the method and the device for copying the multicast message to be copied, when the multicast message to be copied is copied, the load of the multicast message to be copied, which occupies more buffer capacity, is stored, only the packet descriptor of the multicast message to be copied is copied, and then each target packet descriptor obtained after copying and the load are spliced and sent, so that the problem that the multicast message to be copied is required to be stored by more buffer capacity due to the fact that the multicast message to be copied is integrally copied is avoided, and further the problem that the multicast message to be copied is required to be stored by more buffer capacity when the multicast message is copied by a switching chip in the related art is solved, and the technical effect that the buffer capacity in the switching chip can be reduced is achieved.
Drawings
FIG. 1 is a schematic diagram of bursty traffic in the prior art;
fig. 2 is a block diagram of a hardware structure of a mobile terminal of a replication method of a multicast message according to an embodiment of the present invention;
Fig. 3 is a flowchart of a method for copying a multicast message according to an embodiment of the present invention;
FIG. 4 is a block diagram of a switch chip according to an embodiment of the invention;
FIG. 5 is a schematic diagram of an adaptive replication traffic according to an embodiment of the present invention;
FIG. 6 is a block diagram of a switch chip according to an embodiment of the invention;
fig. 7 is a schematic diagram of a relationship between a buffer depth and a transmission time interval of a multicast packet according to an embodiment of the present invention;
Fig. 8 is a block diagram of a switch chip according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The method embodiments provided in the embodiments of the present application may be performed in a mobile terminal, a computer terminal or similar computing device. Taking the mobile terminal as an example, fig. 2 is a block diagram of a hardware structure of the mobile terminal according to a method for copying a multicast message according to an embodiment of the present application. As shown in fig. 2, the mobile terminal may include one or more (only one is shown in fig. 2) processors 202 (the processor 202 may include, but is not limited to, a microprocessor (Central Processing Unit, MCU), a programmable logic device (Field Programmable GATE ARRAY, FPGA), etc. processing means) and a memory 204 for storing data, wherein the mobile terminal may further include a transmission device 206 for communication functions and an input-output device 208. It will be appreciated by those skilled in the art that the structure shown in fig. 2 is merely illustrative and not limiting of the structure of the mobile terminal described above. For example, the mobile terminal may also include more or fewer components than shown in fig. 2, or have a different configuration than shown in fig. 2.
The memory 204 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a method for copying a multicast packet in an embodiment of the present invention, and the processor 202 executes the computer program stored in the memory 204 to perform various functional applications and data processing, that is, implement the above-mentioned method. Memory 204 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 204 may further include memory remotely located relative to the processor 202, which may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 206 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 206 includes a network adapter (Network Interface Controller, simply referred to as a NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 206 may be a Radio Frequency (RF) module, which is used to communicate with the internet wirelessly.
For a better understanding, the following description is given of the application environment of the present application:
there is a functional requirement in the ethernet switch chip that one multicast packet is duplicated into multiple copies and sent to the corresponding outgoing port, a process called multicast duplication. Due to the multicast replication, the traffic in the chip is expanded multiple times, the short-time traffic bursts are large, and more caches are needed to accommodate the burst messages. The process is easy to cause port congestion, causes port packet loss, further causes unstable network and has adverse effect on network QoS.
In order to solve the related problems in the prior art, the present embodiment provides a method for copying a multicast message, including but not limited to being applied to a switch chip, fig. 3 is a flowchart of a method for copying a multicast message according to an embodiment of the present invention, as shown in fig. 3, the flowchart includes steps S302 to S308 as follows:
Step S302, receiving and caching a multicast message to be replicated, wherein the multicast message to be replicated comprises a packet descriptor of the multicast message to be replicated and a load of the multicast message to be replicated;
it should be noted that, when the original multicast message enters the chip from the ingress port of the switch chip, the original multicast message is processed by the packet processing module, and then the data caching module receives and caches the processed multicast message (i.e. the multicast message to be replicated).
In one exemplary embodiment, caching the multicast message to be replicated includes caching a payload of the multicast message to be replicated in a first storage module and caching a packet descriptor of the multicast message to be replicated in a second storage module.
It should be noted that the data buffer module includes a first storage module and a second storage module.
Step S304, acquiring and copying packet descriptors of the multicast message to be copied to obtain N target packet descriptors;
It should be noted that, the above-mentioned packet descriptor for copying the multicast message to be copied is to partially copy the packet descriptor for copying the multicast message. For example, the contents of the target field in the packet descriptor are modified, and the contents of all the characters except the target field in the packet descriptor are copied, so that the target packet descriptor is obtained. The similarity between the packet descriptor and the target packet descriptor is within the target range.
As an alternative example, the step S304 is performed by the replication engine in the switch chip, that is, the replication engine generates N target packet descriptors according to the packet descriptors of the multicast packet to be replicated.
Step S306, scheduling the N target packet descriptors;
As an optional example, the step S304 is performed by a scheduler in the switch chip, where the scheduler schedules the N target packet descriptors, obtains a scheduling result, and sends the N target packet descriptors to the processing module according to the scheduling result.
Step 308, when each scheduled target packet descriptor to be transmitted is transmitted, acquiring the load of the cached multicast message to be copied, splicing the target packet descriptor to be transmitted with the load, obtaining a target multicast message and transmitting the target multicast message.
As an optional example, the step S308 is executed by the processing module in the switch chip, that is, after the processing module obtains the target packet descriptor sent by the scheduler, the processing module needs to obtain the cached load of the multicast message to be replicated, splice the target packet descriptor with the load of the multicast message to be replicated, obtain the target multicast message, and send the target multicast message.
In the above steps S302-S308, when the multicast message to be copied is copied, the load of the multicast message to be copied, which occupies more buffer capacity, is stored, only the packet descriptor of the multicast message to be copied is copied, and then each target packet descriptor obtained after the copying and the load are spliced and sent, so that the multicast message to be copied is prevented from being entirely copied, and the multicast message after the copying is stored by requiring more buffer capacity.
In an exemplary embodiment, a packet descriptor of a multicast packet to be replicated carries a replication index related to a multicast address of the multicast packet to be replicated, that is, the replication of the packet descriptor of the multicast packet to be replicated may be achieved by determining N port identifiers corresponding to the replication index from a multicast member table, where the multicast member table has a set of port identifiers corresponding to different replication indexes, the N target multicast packets are sent through N ports corresponding to the N port identifiers, and replicating the packet descriptor N-1 times to obtain N packet descriptors, where i is an integer greater than or equal to 1 and less than or equal to N, so as to obtain the N target packet descriptors, and replacing the replication index in the i packet descriptor in the N packet descriptors with the i port identifier in the N port identifiers to obtain the i target packet descriptor.
It should be noted that, in the multicast replication module, in order to ensure that the N target packet descriptors obtained after replication can be stored in the queue, the replication engine needs to check the remaining depth of the queue before replicating the packet descriptors, and when the remaining depth of the queue can buffer the N replicated target packet descriptors, the replication engine uses the replication index in the packet descriptors to check the multicast member table, determines N port identifiers corresponding to the replication index, and then completes replication of the packet descriptors of the multicast message to be replicated according to the N port identifiers.
It should be noted that, a certain processing time is required for the replication engine to replicate one original packet descriptor into N target packet descriptors, and therefore, in order to ensure replication efficiency, the replication engine caches multiple original packet descriptors first, and immediately after the replication engine completes replication of the previous original packet descriptor, a new original packet descriptor is called out from the descriptor cache in the multicast replication module for replication.
In an exemplary embodiment, the caching the multicast message to be replicated includes caching a load of the multicast message to be replicated, writing a cache address of the load of the multicast message to be replicated into a packet descriptor of the multicast message to be replicated, and splicing the target packet descriptor to be sent with the load includes acquiring the load of the multicast message to be replicated from the cache address carried by the target packet descriptor to be sent, and splicing the target packet descriptor to be sent with the load of the multicast message to be replicated.
That is, in this embodiment, after the data caching module caches the load of the multicast packet to be replicated, the cache address of the load of the multicast packet to be replicated is written into the packet descriptor of the multicast packet to be replicated, and then the packet descriptor carrying the cache address is sent to the multicast replication module, the replication engine in the multicast replication module replicates the packet descriptor to obtain N target packet descriptors, and then the processing module obtains the target packet descriptor sent by the scheduler, determines the cache address of the load of the multicast packet to be replicated from the target packet descriptors, obtains the load of the multicast packet to be replicated from the cache address in the data caching module, and splices the target packet descriptor with the load of the multicast packet to be replicated, so as to obtain the target multicast packet and send the target multicast packet. It should be noted that the scheduler is located in the multicast replication module.
In an exemplary embodiment, after copying the packet descriptors of the multicast packet to be copied, the method further includes storing the N obtained target packet descriptors in one or more queues.
That is, after the replication engine generates N packet descriptors according to the packet descriptor replication, the N target packet descriptors need to be stored in one or more queues, and the replicated target packet descriptors are sent to the corresponding queues to be cached while being replicated, and waiting for the scheduler to schedule.
In an exemplary embodiment, the scheduling the N target packet descriptors includes the steps of respectively sending the N target packet descriptors stored in the one or more queues to a processing module according to a scheduling result, wherein the processing module executes the steps of obtaining the cached load of the multicast message to be replicated, splicing the target packet descriptors to be sent with the load, obtaining a target multicast message, and sending the target multicast message.
In an exemplary embodiment, the processing module is further configured to send the target multicast packet to a port corresponding to the target multicast packet according to the scheduling result.
In an exemplary embodiment, the steps of copying the packet descriptors of the multicast packet to be copied and storing the obtained N destination packet descriptors in one or more queues are performed by a copying engine, and the step of scheduling the N destination packet descriptors is performed by a scheduler, where the copying engine, the scheduler, and the processing module are located in a switch chip, and the switch chip is configured to copy and send the multicast packet.
In an exemplary embodiment, the N target packet descriptors stored in the one or more queues are respectively sent to a processing module according to a scheduling result, wherein the scheduling result comprises a sending time interval of each target packet descriptor sent to the processing module, corresponding target packet descriptors are obtained from the one or more queues according to the scheduling result, and the target packet descriptors are sent to the processing module.
It should be noted that, the transmission time interval of the destination packet descriptor is a time interval between the destination packet descriptor and a previous destination packet descriptor described by the destination packet descriptor, that is, after the last destination packet descriptor is transmitted to the processing module, the destination packet descriptor needs to be transmitted after the corresponding transmission time interval. Namely, the scheduler needs to acquire corresponding target packet descriptors from the queues at corresponding moments according to the scheduling results, and then sends the target packet descriptors to the processing module.
In an exemplary embodiment, determining the scheduling result of the N target packet descriptors may be implemented by the following steps S11-S13:
Step S11, determining a receiving time interval for receiving two adjacent multicast messages to be replicated;
As an optional example, the above-mentioned receiving time interval is a time interval when the data buffering module receives two adjacent multicast messages to be replicated.
In an exemplary embodiment, step S11 may be implemented by steps S111-S112:
Step S111, determining a main frequency of an exchange chip and determining a packet forwarding rate of a multicast message to be copied, wherein the packet forwarding rate is used for indicating the number of data packets transmitted by the exchange chip in unit time, and the exchange chip is used for copying and transmitting the multicast message;
and step S112, dividing the main frequency of the exchange chip by the packet forwarding rate to obtain the receiving time interval.
It should be noted that, the receiving time interval t=f/R, where F is the primary frequency of the switch chip, and R is the packet forwarding rate.
In an exemplary embodiment, the packet forwarding rate of the multicast packet to be replicated may be determined by determining a first average traffic of the multicast packet to be replicated and a packet size of the multicast packet to be replicated, and dividing the first average traffic by the packet size to obtain the packet forwarding rate of the multicast packet to be replicated.
As an optional example, the first average traffic of the multicast message to be replicated may be counted by the ingress port of the switch chip, or the first average traffic of the multicast message to be replicated may be counted by the packet processing module. It should be noted that the first average flow is an average flow of a plurality of multicast messages to be replicated in a preset time.
As an alternative example, the size of the packet of the multicast packet to be replicated is (l+20) ×8) B, where L is the packet length of the multicast packet to be replicated, and 20B is the frame structure data of the ethernet frame, including the frame interval of 12B and the frame preamble of 8B.
And further, the packet forwarding rate r=fa/((l+20)) of the multicast packet to be replicated, where FA is a first average traffic.
Step S12, determining the average copy number of the packet descriptors, wherein the average copy number is the average number of the target packet descriptors obtained after the packet descriptors are copied;
in an exemplary embodiment, the average number of copies of the packet descriptor may be determined by determining a first average traffic of the multicast message to be copied and a second average traffic of the multicast message after copying, and dividing the second average traffic by the first average traffic to obtain the average number of copies of the packet descriptor.
It should be noted that, the second average flow is the average flow of multiple groups of replicated multicast messages, and each group of replicated multicast messages is replicated by one multicast message to be replicated.
As an alternative example, the second average flow may be obtained by statistics of the outgoing ports of the switch chip, or may be obtained by statistics of the processing module.
I.e. copy count=fb/FA, where FB is the second average flow and FA is the first average flow.
And step S13, dividing the receiving time interval by the average copy number to obtain the sending time interval of each target packet descriptor.
I.e. transmission time interval tc=t/Count, where t is the reception time interval and Count is the average number of copies.
That is, in this embodiment, through the above scheme, the number of copies of the multicast message may be determined according to statistics of the ingress traffic of the multicast message to be copied and the egress traffic of the copied message, and further, the time interval in which the scheduler sends the target packet descriptor to the processing module may be determined according to the number of copies and the receiving time interval between the two multicast messages to be copied, so as to achieve the function of adaptive multicast copying, and avoid the scenario of large traffic burst.
In an exemplary embodiment, determining the scheduling result of the N target packet descriptors may be further implemented by the following steps S21-S22:
step S21, acquiring a main frequency and a target data bit width of the switching chip, and acquiring a starting rate and a stepping rate for transmitting a target packet descriptor to the processing module, wherein the target data bit width is a data bit width of the switching chip for copying and transmitting a multicast message;
It should be noted that, the starting rate and the stepping rate of the scheduler sending the target packet descriptor to the processing module are configured for the target object.
Step S22, when determining the transmission time interval of each target packet descriptor, determining the residual capacity of a memory in the processing module, and determining the transmission time interval of the target packet descriptor according to the residual capacity of the memory, the main frequency, the target data bit width, the starting rate and the stepping rate.
In an exemplary embodiment, determining the transmission time interval of the target packet descriptor according to the remaining capacity of the memory, the primary frequency, the target data bit width, the start rate and the step rate includes calculating the transmission time interval by the following formula, t=f/(fi+fstep) r, where t is the transmission time interval, f is the primary frequency, W is the target data bit width, fi is the start rate, fstep is the step rate, r is a group play big factor, and d is the remaining capacity of the memory.
It should be noted that fi+fstep×r×d must be smaller than Fmax, where Fmax is the maximum rate of sending the target packet descriptor to the processing module, where the unit of the start rate, the step rate, and the maximum rate is bps or pps.
It should be noted that, the scheduler controls the process of scheduling the packet descriptor according to the residual capacity of the memory in the processing module, so as to achieve the self-adaptive replication of the multicast message and avoid the occurrence of a scene of short-time traffic burst.
It will be apparent that the embodiments described above are merely some, but not all, embodiments of the invention. For better understanding of the above method, the following description will explain the above process with reference to the examples, but is not intended to limit the technical solution of the embodiments of the present invention, specifically:
In an exemplary embodiment, fig. 4 illustrates a chip architecture diagram of a switch chip for implementing a multicast replication and transmission function, specifically, after an original multicast packet enters the chip from an ingress port, the packet processing module processes the original multicast packet and sends the original multicast packet to the multicast replication processing section shown in fig. 4. In fig. 4, the processed original multicast message is first sent to a data buffering module, where the data portion of the multicast message is buffered, and the packet descriptor of the multicast message is sent to a multicast replication module. The packet descriptor contains information such as a message storage address, a replication index, and the like.
In the multicast replication module, to ensure that the replicated packet descriptors can be stored in the queues, the replication engine checks the remaining depth of the destination queues before replication. When the surplus depth of the destination queue can buffer the copied packet descriptors, the copying engine uses the packet descriptors as indexes to check a multicast member table, then completes copying of the multicast message descriptors according to the table look-up contents, and sends the copied packet descriptors to the corresponding queues for buffering while copying, and waits for a scheduler to schedule. The copy engine copies one original packet descriptor into a plurality of original packet descriptors, a certain processing time is needed, the plurality of original packet descriptors are cached for ensuring the copy efficiency, and after the copy engine finishes copying the previous original packet descriptor, a new original packet descriptor is called out from the descriptor cache for copying. In addition, the copied packet descriptors stored in the queue cache also need to be scheduled, and are sent to a processing module at a later stage according to a scheduling result.
In the processing module, the message data is read out from the corresponding address of the data cache module according to the received copied multicast message packet descriptor, and the copied multicast message is spliced with the packet descriptor content to obtain the copied multicast message, and then the processing module sends the copied multicast message to the corresponding output port, and the copying process of the multicast message is completed at the moment. In the process, only one part of message data part occupying more multicast messages is stored in the data caching module, and only the packet descriptors of the multicast messages are operated in the copying process, so that the cache occupied by the copied multicast messages is greatly reduced.
It should be noted that, based on the chip architecture shown in fig. 4, in order to solve the scenario of large traffic burst shown in fig. 1, the present application proposes an adaptive multicast replication method, and specific embodiments thereof are divided into two types. Two embodiments are specifically described below:
In the first embodiment, the achieved effect of copying the message is shown in fig. 5. The multicast message of the adaptive replication in fig. 5 is uniform in time distribution, if the original multicast message traffic is 10Gbps, 32 copies are needed, the multicast message rate after replication is 320Gbps, and the situation that the traffic exceeds 320Gbps in a short time does not occur.
In this embodiment, the ingress traffic (i.e., the first average traffic in the above embodiment) of the original multicast packet and the egress traffic (i.e., the second average traffic in the above embodiment) of the duplicated packet are detected separately, and the interval time of the duplicated packet is dynamically adjusted according to the data of the ingress traffic and the egress traffic (i.e., the second average traffic in the above embodiment), so as to achieve the function of adaptive multicast duplication, and avoid the scenario of large traffic bursts. The ingress traffic may be detected at the ingress of the switching chip or may be entered after statistics by the upper packet processing module. The same outlet flow can be detected at the outlet of the exchange chip or can be counted by the processing module and then input.
The specific calculation mode of the flow regulation is as follows, the flow FA of the source packet (namely the original multicast message) is obtained by the inlet flow statistics, and the outlet flow FB is obtained by the outlet flow statistics at the later stage. In order to obtain the time interval t between two source packets, firstly, the source packet forwarding rate R needs to be calculated, and according to the packet length L of the source packets, the unit is B, and the following R=FA/((L+20) x 8) is calculated. Wherein 20B is frame structure data of an ethernet frame, and includes a frame interval of 12B and a frame preamble of 8B. According to the system main frequency F of the chip and the source packet forwarding rate R, the time interval t=F/R can be obtained, and further the copied packet sending interval time tc=t/Count is calculated.
In the chip structure shown in fig. 4, the time interval of the copied packet descriptors is called out from the queues 1-n by controlling the scheduler, so that the time interval of the copied packet sent out by the processing module is controlled, the copied packet is uniformly distributed in time, and the situation of large traffic burst is avoided.
Taking an actual system as an example, assume that the ingress traffic is 10Gbps, the egress traffic is 320Gbps, the packet length of the original multicast packet is 64B, and the system dominant frequency is 1.4Ghz. According to the above calculation procedure, it is possible to obtain:
Copy count=320 Gbps/10 gbps=32;
Source packet forwarding rate r=10 Gbps/((64+20) x 8) =15 Mpps
Source packet time interval t=1.4 Ghz/15Mpps =93 Cl k;
and then sending the multicast message at the rising edge of every 3 clocks under the main frequency of the system clock, so that the flow after multicast replication can reach 320Gbps uniformly.
In the second embodiment, the packet descriptor buffer capacity of the processing module is monitored, and the interval of the packet descriptor after being transmitted and copied by the scheduler in the multicast copying module is adaptively adjusted, so that the burst flow is regulated and controlled, and the occurrence of a scene with large flow burst is avoided. The specific chip architecture is shown in fig. 6:
Compared with the structure of fig. 4, a small buffer (i.e. the memory in the above embodiment) for buffering the packet descriptors sent by the scheduler is added in the processing module, and the remaining capacity of the buffer is reported to the scheduler in the multicast replication module in real time. The small buffer memory has the functions of not only absorbing the packet descriptors of burst scheduling, but also providing feedback information for a scheduler to adjust the scheduling interval so as to realize the regulation and control of the outlet flow.
By applying the architecture to the chip, the system main frequency f, the transmission data bit width W of the multicast copy message and the residual cache capacity depth d returned by the small cache in the processing module can be obtained. For the purpose of adaptive replication, the scheduler also needs to configure parameters such as the start rate Fi (unit: bps or pps) of the multicast transmission, the maximum rate Fmax (unit: bps or pps) of the multicast transmission, the step rate Fstep (unit: bps or pps) of the multicast transmission, and the amplification factor r of the multicast transmission. Where bps is the unit of network transmission rate, which is how many bits of data can be transmitted per second, pps is the unit of network transmission rate, which is how many packets can be transmitted per second.
According to the above parameters, the calculation formula of the packet sending time interval t of the multicast message is as follows:
t=f/(fi+fstep r) d), wherein, fi+fstep r d must be smaller than Fmax;
The minimum value of the time interval t of the packet descriptor can be known from f W/Fmax, so that the purpose of limiting the maximum packet sending rate is achieved, and the scene of large short-time traffic burst is avoided. In the copying process, the group play large factor r and the residual buffer depth d jointly act on the stepping rate Fstep and jointly act on the multicast starting rate Fi. When the replication is started, the residual buffer depth d is the maximum value, fi+fstep r d is the maximum value, the packet interval time t is the minimum value, the scheduler sends a packet descriptor to the processing module according to the time t, the processing module removes the original multicast message from the data buffer module, and the copied multicast message is generated and sent to the output port. Wherein the rate of reading the copied packet descriptors from the small buffer is constant.
Fig. 7 is a schematic diagram illustrating a relationship between a buffer depth in a processing module and a multicast packet transmission time interval, as shown in fig. 7, if, as a multicast replication process proceeds, a packet descriptor buffer depth d in the processing module gradually decreases, a corresponding value of fi+fstep×r×d also gradually decreases, and a packet transmission time interval t of a corresponding scheduler gradually increases, thereby correspondingly decreasing the number of packet descriptors sent to the processing module in a unit time. The reduction of packet descriptors issued by the scheduler to the processing module results in a reduction of the remaining capacity of the queue cache of the replication module, which in turn results in a reduction of replication of packet descriptors by the replication engine. In particular, if the Fi rate is smaller than the minimum traffic of the egress, the writing speed of the small buffer memory storing the packet descriptor in the processing module is smaller than the reading speed, so as to ensure that the small buffer memory is not fully written.
The scheduler controls the process of scheduling the packet descriptors according to the cache capacity of the small cache in the processor, so as to achieve self-adaptive replication of the multicast message and avoid the occurrence of a scene with short-time and large traffic burst. In addition, the structure only copies the packet descriptors of the multicast messages in the copying process, reads the data of the multicast source packets from the data caching module and splices the data into the multicast messages only when the data are finally sent out of the processing module, and the process reduces the consumption of caching in the multicast copying process.
Briefly, the present application provides a chip architecture and method to address large bursts of multicast replication traffic. The improved chip architecture can reduce the demand of the multicast replication process for the buffer capacity, and in addition, the multicast message is replicated in a self-adaptive mode, so that the generation of short-time traffic burst large scenes is reduced from the source. And the reduction of the large traffic burst scene is also beneficial to the processing module to reduce the cache capacity for accommodating the copied message, thereby saving precious cache resources on the chip. In addition, the reduction of the large flow burst scene is more beneficial to reducing the occurrence of the conditions of discarding outgoing port messages and port congestion, and the QoS of the network is improved so as to further improve the user experience.
From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based On such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. Read-only Memory/Random Access Memory (ROM/RAM), magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present invention.
In this embodiment, an exchange chip is further provided, and the exchange chip is used to implement the foregoing embodiments and preferred embodiments, and is not described herein. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the switch chip described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
Fig. 8 is a block diagram of a switch chip according to an embodiment of the present invention, and as shown in fig. 8, the switch chip includes:
A first storage module 82, configured to cache a load of a received multicast message to be replicated, where the multicast message to be replicated includes a packet descriptor of the multicast message to be replicated and the load of the multicast message to be replicated;
The replication engine 84 is configured to obtain and replicate the packet descriptors of the multicast packet to be replicated to obtain N target packet descriptors;
A scheduler 86 for scheduling the N target packet descriptors;
And the processing module 88 is configured to obtain a cached load of the to-be-replicated multicast packet when each scheduled to-be-transmitted target packet descriptor is transmitted, splice the to-be-transmitted target packet descriptor with the load, obtain a target multicast packet, and transmit the target multicast packet.
According to the switching chip, when the multicast message to be copied is copied, the load of the multicast message to be copied, which occupies more buffer capacity, is stored, only the packet descriptor of the multicast message to be copied is copied, and then each target packet descriptor and load obtained after the copying are spliced and sent, so that the multicast message to be copied is prevented from being integrally copied, more buffer capacity is needed for storing the multicast message after the copying, and further the problem that the multicast message after the copying is needed for storing the multicast message when the switching chip copies the multicast message in the related art is solved by adopting the technical scheme, and the technical effect that the buffer capacity in the switching chip can be reduced is achieved.
In an exemplary embodiment, the packet descriptor carries a replication index related to a multicast address of the multicast packet to be replicated, the replication engine 84 is further configured to determine N port identifiers corresponding to the replication index from a multicast member table, where the multicast member table has a set of port identifiers corresponding to different replication indexes, the N target multicast packets are sent through N ports corresponding to the N port identifiers, and perform N-1 replication on the packet descriptor to obtain N packet descriptors, where i is an integer greater than or equal to 1 and less than or equal to N, so as to obtain the N target packet descriptors, and replace the replication index in the i packet descriptor in the N packet descriptors with the i port identifier in the N port identifiers to obtain the i target packet descriptor.
In an exemplary embodiment, the switch chip further includes a second storage module, configured to cache a packet descriptor cache of the multicast packet to be replicated.
In an exemplary embodiment, the first storage module 82 is further configured to write a buffer address of the payload of the multicast packet to be replicated in a packet descriptor of the multicast packet to be replicated, and the processing module 88 is further configured to obtain the payload of the multicast packet to be replicated from a buffer address carried by the target packet descriptor to be sent, and splice the target packet descriptor to be sent with the payload of the multicast packet to be replicated.
In an exemplary embodiment, the replication engine 84 is further configured to store the obtained N target packet descriptors in one or more queues after replicating the packet descriptors of the multicast packet to be replicated, and the scheduler 86 is further configured to send the N target packet descriptors stored in the one or more queues to a processing module according to a scheduling result, respectively.
In an exemplary embodiment, the processing module 88 is further configured to send the target multicast packet to a port corresponding to the target multicast packet according to the scheduling result.
In an exemplary embodiment, the scheduler 86 is further configured to determine a scheduling result of the N target packet descriptors, where the scheduling result includes a transmission time interval of transmitting a target packet descriptor to the processing module, obtain corresponding target packet descriptors from the one or more queues according to the scheduling result, and transmit the target packet descriptors to the processing module.
In an exemplary embodiment, the scheduler 86 is further configured to determine a receiving time interval for receiving two adjacent multicast messages to be replicated, determine an average number of replications of the packet descriptor, where the average number of replications is an average number of replications of the target packet descriptor obtained after replicating the packet descriptor, and divide the receiving time interval by the average number of replications to obtain a sending time interval of the target packet descriptor.
In an exemplary embodiment, the scheduler 86 is further configured to determine a primary frequency of a switch chip, and determine a packet forwarding rate of a multicast packet to be replicated, where the packet forwarding rate is used to indicate a number of data packets transmitted by the switch chip in a unit time, and the switch chip is configured to replicate and send the multicast packet, and divide the primary frequency of the switch chip by the packet forwarding rate to obtain the receiving time interval.
In an exemplary embodiment, the scheduler 86 is further configured to determine a first average flow of the multicast message to be replicated and a message size of the multicast message to be replicated, and divide the first average flow by the message size to obtain a packet forwarding rate of the multicast message to be replicated.
In an exemplary embodiment, the scheduler 86 is further configured to determine a first average traffic of the multicast message to be replicated and a second average traffic of the multicast message after replication, and divide the second average traffic by the first average traffic to obtain an average number of replications of the packet descriptor.
In an exemplary embodiment, the scheduler 86 is further configured to obtain a primary frequency and a target data bit width of a switch chip, and obtain a start rate and a step rate for transmitting a target packet descriptor to the processing module, where the target data bit width is a data bit width of a multicast packet that is copied and transmitted by the switch chip, and the switch chip is configured to copy and transmit the multicast packet, determine a remaining capacity of a memory in the processing module when determining a transmission time interval of each target packet descriptor, and determine a transmission time interval of the target packet descriptor according to the remaining capacity of the memory, the primary frequency, the target data bit width, the start rate, and the step rate.
In an exemplary embodiment, the scheduler 86 is further configured to calculate the transmission time interval by the following formula, where t=f×w/(fi+fstep×r×d), where t is the transmission time interval, f is the primary frequency, W is the target data bit width, fi is the start rate, fstep is the step rate, r is a group play large factor, and d is the remaining capacity of the memory.
It should be noted that each of the above modules may be implemented by software or hardware, and the latter may be implemented by, but not limited to, the above modules all being located in the same processor, or each of the above modules being located in different processors in any combination.
Embodiments of the present invention also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.
In an exemplary embodiment, the computer readable storage medium may include, but is not limited to, a U disk, a Read-only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, etc. various media in which a computer program may be stored.
An embodiment of the invention also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
In an exemplary embodiment, the electronic apparatus may further include a transmission device connected to the processor, and an input/output device connected to the processor.
Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.
It will be appreciated by those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention should be included in the protection scope of the present invention.
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| CN202310968425.0A CN119484439A (en) | 2023-07-31 | 2023-07-31 | Multicast message duplication method, switching chip, storage medium and electronic device |
| PCT/CN2024/096823 WO2025025785A1 (en) | 2023-07-31 | 2024-05-31 | Multicast message copying method, and switch chip, storage medium and electronic apparatus |
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| CN104219158A (en) * | 2014-09-03 | 2014-12-17 | 杭州华三通信技术有限公司 | Message copying method and message copying device |
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