CN119480779A - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, wherein the manufacturing method comprises the steps of providing a substrate, wherein the substrate comprises a plurality of bit lines, an initial bit line isolation structure for covering each bit line, and a node contact part positioned between adjacent initial bit line isolation structures; the method comprises the steps of removing part of an initial bit line isolation structure to obtain an intermediate bit line isolation structure, depositing an isolation material layer on a substrate, filling gaps between adjacent intermediate bit line isolation structures, removing the isolation material layer on a node contact portion to obtain a final bit line isolation structure with an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure, and forming a plurality of landing pads arranged at intervals on the isolation widening portion and the node contact portion.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for manufacturing the same.

Background

In semiconductor manufacturing processes, the size of the landing pad affects electrical transmission performance. Due to the shape characteristics of the bottom bit line structure of the landing pad, the situation that short circuit occurs between adjacent landing pads and the landing pad is peeled off often occurs, and the electrical transmission performance and the product yield of the product are affected.

Disclosure of Invention

In view of the above, the present application is directed to a semiconductor structure and a method for manufacturing the same.

In order to achieve the above purpose, the technical scheme of the application is realized as follows:

the embodiment of the application provides a manufacturing method of a semiconductor structure, which comprises the following steps:

Providing a substrate comprising a plurality of bit lines and an initial bit line isolation structure covering each bit line, the substrate further comprising node contacts between adjacent initial bit line isolation structures;

Removing part of the initial bit line isolation structure to obtain an intermediate bit line isolation structure;

Depositing an isolation material layer on the substrate, wherein the isolation material layer fills gaps between adjacent intermediate bit line isolation structures;

Removing the isolation material layer on the node contact to obtain a final bit line isolation structure with an isolation widening on the intermediate bit line isolation structure;

A plurality of spaced landing pads are formed on the isolation widening and the node contact.

In some embodiments, the initial bit line isolation structure includes a first isolation layer covering the bit line, an intermediate isolation layer on a side of the first isolation layer away from the bit line, and a second isolation layer on a side of the intermediate isolation layer away from the bit line;

the removing a portion of the initial bit line isolation structure includes:

and removing at least part of the second isolation layer.

In some embodiments, the material of the isolation material layer is the same as the material of the second isolation layer.

In some embodiments, the removing the layer of isolation material on the node contact to obtain a final bit line isolation structure having an isolation widening on the intermediate bit line isolation structure comprises:

And carrying out chemical mechanical polishing treatment on the isolation material layer, and etching to remove the isolation material layer on the node contact part, so that the difference value between the bottom width and the top width of a bit line structure in the direction parallel to the plane of the substrate is within a preset range, wherein the bit line structure comprises the bit line and the final bit line isolation structure covering the bit line.

In some embodiments, the preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers.

In some embodiments, the forming a plurality of spaced apart landing pads on the isolation widening and the node contact includes:

sequentially depositing a contact material layer and a landing material layer on the isolation widened part and the node contact part, wherein the contact material layer continuously covers the surface of the isolation widened part and the surface of the node contact part, and the landing material layer covers the contact material layer and at least fills a groove formed by the contact material layer;

And removing part of the landing material layer and part of the contact material layer between adjacent isolation widened parts to obtain a plurality of landing pads arranged at intervals.

In some embodiments, the landing pad comprises a first sub-pad, a second sub-pad and a third sub-pad connecting the first sub-pad and the second sub-pad, wherein the first sub-pad is positioned on the top surface of the isolation widening part, the second sub-pad is positioned on the top surface of the node contact part, the third sub-pad is positioned on the side surface of the isolation widening part, the third sub-pad is perpendicular or basically perpendicular to the first sub-pad, the second sub-pad is parallel to the first sub-pad, and the surface of the second sub-pad contacted with one of the final bit line isolation structures is a plane.

The embodiment of the application also provides a semiconductor structure, which comprises a substrate and a plurality of landing pads arranged at intervals, wherein the substrate comprises a plurality of bit lines and a final bit line isolation structure covering each bit line, the substrate further comprises node contact parts positioned between adjacent final bit line isolation structures, the final bit line isolation structures are provided with isolation widening parts, the bit lines and the final bit line isolation structures form a bit line structure, the difference value between the bottom width and the top width of the bit line structure is in a preset range in the direction parallel to the plane of the substrate, and the landing pads arranged at intervals are positioned on the isolation widening parts and the node contact parts.

In some embodiments, the preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers.

In some embodiments, the landing pad comprises a first sub-pad, a second sub-pad and a third sub-pad connecting the first sub-pad and the second sub-pad, wherein the first sub-pad is positioned on the top surface of the isolation widening part, the second sub-pad is positioned on the top surface of the node contact part, the third sub-pad is positioned on the side surface of the isolation widening part, the third sub-pad is perpendicular or basically perpendicular to the first sub-pad, the second sub-pad is parallel to the first sub-pad, and the surface of the second sub-pad contacted with one of the final bit line isolation structures is a plane.

The embodiment of the application provides a manufacturing method of a semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a plurality of bit lines and an initial bit line isolation structure covering each bit line, the substrate further comprises node contact parts positioned between adjacent initial bit line isolation structures, removing part of the initial bit line isolation structures to obtain intermediate bit line isolation structures, depositing an isolation material layer on the substrate, filling gaps between the adjacent intermediate bit line isolation structures with the isolation material layer, removing the isolation material layer positioned on the node contact parts to obtain an end bit line isolation structure with an isolation widened part, positioning the isolation widened part on the intermediate bit line isolation structures, and forming a plurality of landing pads arranged at intervals on the isolation widened parts and the node contact parts.

Drawings

FIGS. 1 a-1 g are schematic views of basic structures of components in a related art semiconductor structure manufacturing process;

Fig. 2 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

Fig. 3a to fig. 3f are schematic views of basic structures of components in a manufacturing process flow of a semiconductor structure according to an embodiment of the present application.

Detailed Description

Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the application are shown in the drawings, it should be understood that the application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the application may be practiced without one or more of these details. In other instances, well-known functions and constructions are not described in detail since they would obscure the application in some of the features that are well known in the art, i.e., not all features of an actual embodiment are described herein.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It should be understood that spatially relative terms, such as "under," "above," "over," and the like, may be used herein for convenience of description to describe one element or feature as illustrated in the figures as compared to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a more complete understanding of the nature and the technical content of the embodiments of the present application, reference should be made to the following detailed description of embodiments of the application, taken in conjunction with the accompanying drawings, which are meant to be illustrative only and not limiting of the embodiments of the application.

Fig. 1a to 1g are schematic views of basic structures of components in a manufacturing process flow of a semiconductor structure in the related art. In the process flow of manufacturing the semiconductor structure of the related art, first, as shown in fig. 1a, a base 100 is provided, the base 100 includes a substrate 11, a plurality of bit lines 12 disposed on the substrate 11, and an initial bit line isolation structure 13 covering each of the bit lines 12, and the base 100 further includes a node contact portion 14 disposed between adjacent ones of the initial bit line isolation structures 13. The substrate 11 includes an active region 110 and an isolation structure 111 between adjacent active regions 110, the bit line 12 is connected to the active region 110 through a bit line contact structure, the node contact 14 is connected to the active region 110, and the node contact 14 is insulated from the bit line 12. The initial bit line isolation structure 13 includes a first isolation layer 130, an intermediate isolation layer 131, and a second isolation layer 132, wherein the first isolation layer 130 covers the bit line 12, the intermediate isolation layer 131 is located on a side of the first isolation layer 130 away from the bit line 12, and the second isolation layer 132 is located on a side of the intermediate isolation layer 131 away from the bit line 12.

Next, as shown in fig. 1b, a portion of the initial bit line isolation structure 13 is removed, resulting in an intermediate bit line isolation structure 15. Specifically, when removing a portion of the initial bit line isolation structure 13, there may be a case where the initial bit line isolation structure 13 is not uniform in removal uniformity, resulting in a non-uniform top width of the intermediate bit line isolation structure 15, and some of the intermediate bit line isolation structures 15 have a particularly small top width (as shown by the labeled bit line isolation structure X in fig. 1 b).

Next, as shown in fig. 1c, a thin layer of isolation material 16 is deposited on the substrate 100, the isolation material layer 16 being located on the surfaces of the intermediate bit line isolation structures 15 and the node contacts 14. The isolation material layer 16 is used to compensate for damage to the top of the intermediate bit line isolation structure 15 due to the removal of a portion of the initial bit line isolation structure 13. The top width of the marker bit line isolation structure X is still small due to the deposition of the thinner isolation material layer 16 in the related art.

Next, as shown in fig. 1d, the isolation material layer 16 on the node contact 14 is removed, leaving only the isolation material layer 16 on the surface of the intermediate bit line isolation structure 15, the isolation material layer 16 on the surface of the intermediate bit line isolation structure 15 being combined with the intermediate bit line isolation structure 15 to form a final bit line isolation structure 17. It will be appreciated that since the landing pad 18 to be subsequently fabricated needs to be connected to the node contact 14, the isolation material layer 16 on the node contact 14 needs to be removed.

Next, as shown in fig. 1e, a contact material layer 180 and a landing material layer 181 are sequentially deposited on the isolation material layer 16 and the node contact 14, the contact material layer 180 continuously covers the surface of the isolation material layer 16 and the surface of the node contact 14, and the landing material layer 181 covers the contact material layer 180 and at least fills the recess formed by the contact material layer 180.

Next, as shown in fig. 1f, a portion of the landing material layer 181 and a portion of the contact material layer 180 between adjacent terminal bit line isolation structures 17 are removed to obtain a plurality of contact layers 1801 disposed at intervals and a landing layer 1811 on the contact layers 1801, wherein one of the contact layers 1801 and the landing layer 1811 on the contact layer 1801 are combined into one landing pad 18. It will be appreciated that, due to the smaller top width of the flag bit line isolation structure X, the contact material layer 180 located on the flag bit line isolation structure X is not located in the target etching region, and when the contact material layer 180 is removed, the contact layer 1801 located on the flag bit line isolation structure X is not etched to be disconnected from the contact layer 1801 located on the adjacent final bit line isolation structure 17, thereby causing a short circuit between the landing pad 18 located on the flag bit line isolation structure X and the adjacent landing pad 18.

In addition, as shown in fig. 1g, due to the smaller top width of the marker bit line isolation structure X, the landing pad 18 on the marker bit line isolation structure X may be stripped during formation.

In view of the foregoing, it can be appreciated that, due to poor uniformity of the top width of the bottom terminal bit line isolation structure 17 of the landing pads 18, short circuits between adjacent landing pads 18 and peeling of the landing pads 18 often occur during the manufacturing process, which affects the electrical performance and yield of the product. The embodiment of the application can solve the defects.

As shown in fig. 2, a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application includes:

S1, providing a substrate, wherein the substrate comprises a plurality of bit lines, an initial bit line isolation structure covering each bit line, and node contact parts between adjacent initial bit line isolation structures;

S2, removing part of the initial bit line isolation structure to obtain an intermediate bit line isolation structure;

s3, depositing an isolation material layer on the substrate, wherein the isolation material layer fills gaps between adjacent intermediate bit line isolation structures;

s4, removing the isolation material layer on the node contact part to obtain a final bit line isolation structure with an isolation widened part, wherein the isolation widened part is positioned on the intermediate bit line isolation structure;

s5, forming a plurality of landing pads which are arranged at intervals on the isolation widened part and the node contact part.

It can be appreciated that the application compensates the uniformity of the top width of the intermediate bit line isolation structure by filling the gap between the adjacent intermediate bit line isolation structures with the isolation material layer, so as to obtain the final bit line isolation structure with the isolation widening part, and the isolation widening part increases the width of the top of the final bit line isolation structure, so that the landing pad can be better fixed on the top of the final bit line isolation structure, the occurrence of short circuit and landing pad stripping between the adjacent landing pads is avoided, the failure proportion is reduced, and the electrical transmission performance and the product yield of the product can be improved, and the stability of the whole process is improved.

Next, a method for manufacturing a semiconductor structure according to an embodiment of the present application will be described in detail with reference to fig. 3a to 3f, where fig. 3a to 3f are schematic basic structures of each component in a manufacturing process flow of the semiconductor structure according to an embodiment of the present application.

In step S1, as shown in fig. 3a, a base 100 is provided, the base 100 comprising a substrate 11, a plurality of bit lines 12 on the substrate 11, and an initial bit line isolation structure 13 covering each of the bit lines 12, the base 100 further comprising node contacts 14 between adjacent ones of the initial bit line isolation structures 13. The substrate 11 includes an active region 110 and an isolation structure 111 between adjacent active regions 110, the bit line 12 is connected to the active region 110 through a bit line contact structure, the node contact 14 is connected to the active region 110, and the node contact 14 is insulated from the bit line 12. The initial bit line isolation structure 13 includes a first isolation layer 130, an intermediate isolation layer 131, and a second isolation layer 132, wherein the first isolation layer 130 covers the bit line 12, the intermediate isolation layer 131 is located on a side of the first isolation layer 130 away from the bit line 12, and the second isolation layer 132 is located on a side of the intermediate isolation layer 131 away from the bit line 12.

The material of the substrate 11 is, for example, silicon, the material of the isolation structure 111 is, for example, silicon oxide, the material of the node contact portion 14 is, for example, polysilicon, the material of the bit line 12 includes a conductive material, the materials of the first isolation layer 130 and the second isolation layer 132 are, for example, silicon nitride, and the material of the intermediate isolation layer 131 is, for example, silicon oxide.

In step S2, as shown in fig. 3b, an etching process is used to remove a portion of the initial bit line isolation structure 13, so as to obtain an intermediate bit line isolation structure 15. Specifically, when removing a portion of the initial bit line isolation structure 13, there may be a case where the initial bit line isolation structure 13 is not uniform in removal uniformity, resulting in a non-uniform top width of the intermediate bit line isolation structure 15, and some of the intermediate bit line isolation structures 15 have a particularly small top width (as shown by the labeled bit line isolation structure X in fig. 3 b).

In some embodiments, the removing a portion of the initial bit line isolation structure 13 includes removing at least a portion of the second isolation layer 132.

It should be noted that, part of the initial bit line isolation structure 13 may be removed, only part of the second isolation layer 132 may be removed, or part of the second isolation layer 132 and part of the intermediate isolation layer 131 may be removed, and in fig. 3b, part of the second isolation layer 132 and part of the intermediate isolation layer 131 are removed as an example. In addition, a portion of the first isolation layer 130 in the tag bit line isolation structure X is also removed, which is a case where it happens that the first isolation layer 130 is not the target removal object.

In step S3, as shown in fig. 3c, an isolation material layer 16 is deposited on the substrate 100, and the isolation material layer 16 fills the gaps between the adjacent intermediate bit line isolation structures 15.

It will be appreciated that the isolation material layer 16 is used to compensate for the damage to the top of the intermediate bit line isolation structure 15 caused by removing a portion of the initial bit line isolation structure 13, and that the deposited isolation material layer 16 fills the gap between adjacent intermediate bit line isolation structures 15 in the present application, so that the top width of the intermediate bit line isolation structure 15 does not have the problem of poor uniformity.

In some embodiments, the material of the isolation material layer 16 is the same as the material of the second isolation layer 132. For example, the material of the isolation material layer 16 and the material of the second isolation layer 132 are both silicon nitride.

In step S4, as shown in fig. 3d, the isolation material layer 16 on the node contact 14 is removed by an etching process to obtain a final bit line isolation structure 17 having an isolation widening 19, the isolation widening 19 being located on the intermediate bit line isolation structure 15. Wherein the isolation widening 19 is combined with the intermediate bit line isolation structure 15 to form the final bit line isolation structure 17. It will be appreciated that since the landing pad 18 to be subsequently fabricated needs to be connected to the node contact 14, the isolation material layer 16 on the node contact 14 needs to be removed. In some embodiments, since the node contact 14 is easily oxidized, it is also necessary to etch away the oxide on the surface of the node contact 14.

It will be appreciated that since the deposited isolation material layer 16 of the present application fills the gaps between adjacent intermediate bit line isolation structures 15, when only the isolation material layer 16 on the node contact 14 is removed, the isolation material layer 16 on the intermediate bit line isolation structures 15 remains, i.e., is an isolation widening 19, and the isolation widening 19 compensates for the uneven top width of the intermediate bit line isolation structures 15, so that the subsequently formed landing pads 18 can be better fixed on top of the final bit line isolation structures 17. In addition, this step of removing the isolation material layer 16 located on the node contact 14 may be performed at the same time in the array region and the peripheral region.

In some embodiments, the removing the isolation material layer 16 on the node contact 14 to obtain a final bitline isolation structure 17 having an isolation widening 19, the isolation widening 19 being on the intermediate bitline isolation structure 15, comprises:

The isolation material layer 16 is subjected to chemical mechanical polishing, and the isolation material layer 16 on the node contact portion 14 is etched and removed, so that the difference between the bottom width and the top width of a bit line structure including the bit line 12 and the final bit line isolation structure 17 covering the bit line 12 is within a predetermined range in a direction parallel to the plane of the substrate 100.

It can be appreciated that the present embodiment facilitates the deposition of a subsequent film layer by performing the chemical mechanical polishing treatment on the isolation material layer 16, so that the surface of the isolation material layer 16 is flatter. In addition, in the embodiment, the difference between the bottom width a and the top width b of the finally formed bit line structure is within the preset range, so that the top width of the bit line structure can be controlled, the uniformity is better, and the failure of the landing pad 18 formed later is avoided.

In some embodiments, the preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers. For example, the difference between the bottom width a and the top width b of the bit line structure is 0.2 nm. It will be appreciated that the smaller the difference between the bottom width a and the top width b of the bit line structure, the lower the risk of failure of the landing pad 18.

In step S5, as shown in fig. 3f, a plurality of landing pads 18 are formed on the isolation widening 19 and the node contact 14 at intervals.

It will be appreciated that since the final bit line isolation structure 17 includes the intermediate bit line isolation structure 15 and the isolation widening 19 on the intermediate bit line isolation structure 15, the width of the top of the final bit line isolation structure 17 is large and the uniformity of the width of the top of the final bit line isolation structure 17 is good, thus not causing a short circuit between the landing pad 18 on the marker bit line isolation structure X and the adjacent landing pad 18, nor causing the landing pad 18 on the marker bit line isolation structure X to be stripped during formation.

In some embodiments, as shown in fig. 3e, the forming a plurality of landing pads 18 spaced apart on the isolation widening 19 and the node contact 14 includes:

Sequentially depositing a contact material layer 180 and a landing material layer 181 on the isolation widening portion 19 and the node contact portion 14, wherein the contact material layer 180 continuously covers the surface of the isolation widening portion 19 and the surface of the node contact portion 14, and the landing material layer 181 covers the contact material layer 180 and at least fills up the grooves formed by the contact material layer 180;

Portions of the landing material layer 181 and portions of the contact material layer 180 between adjacent ones of the isolation widening 19 are removed to obtain a plurality of spaced apart landing pads 18.

It will be appreciated that as shown in fig. 3f, a landing pad 18 includes a contact layer 1801 and a landing layer 1811 on the contact layer 1801, wherein the contact layer 1801 is obtained by removing a portion of the contact material layer 180 between adjacent terminal bit line isolation structures 17, and the landing layer 1811 is obtained by removing a portion of the landing material layer 181 between adjacent terminal bit line isolation structures 17.

The material of the contact material layer 180 is, for example, titanium nitride, the contact material layer 180 is for ohmic contact, and the material of the landing material layer 181 is, for example, tungsten.

It will be appreciated that since the top width of the final bit line isolation structure 17 becomes larger, i.e., the volume occupied by the final bit line isolation structure 17 becomes larger, the amount of the landing material layer 181 can be reduced, thereby saving the production cost.

In some embodiments, as shown in fig. 3f, the landing pad 18 includes a first sub-pad 182, a second sub-pad 183, and a third sub-pad 184 connecting the first sub-pad 182 and the second sub-pad 183, the first sub-pad 182 being located on the top surface of the isolation widening portion 19, the second sub-pad 183 being located on the top surface of the node contact portion 14, and the third sub-pad 184 being located on the side surface of the isolation widening portion 19, wherein the third sub-pad 184 is disposed perpendicular or substantially perpendicular to the first sub-pad 182, the second sub-pad 183 is disposed parallel to the first sub-pad 182, and a surface of the second sub-pad 183 contacting one of the final bit line isolation structures 17 is a plane.

It will be appreciated that the shape of the landing pad 18 of embodiments of the present application is changed compared to the shape of the landing pad 18 of the related art, due to the different shape of the final bit line isolation structure 17 of the present application and the final bit line isolation structure 17 of the related art. The contact area of the landing pad 18 with the node contact 14 is unchanged in embodiments of the present application.

In some embodiments, the edge of the landing pad 18 on the isolation widening 19 is flush with the edge of the isolation widening 19.

Next, as shown in fig. 3f, an embodiment of the present application further provides a semiconductor structure, including a substrate 100 and a plurality of landing pads 18 disposed at intervals, where the substrate 100 includes a plurality of bit lines 12 and a final bit line isolation structure 17 covering each of the bit lines 12, the substrate 100 further includes a node contact portion 14 located between adjacent final bit line isolation structures 17, and the final bit line isolation structures 17 have isolation widened portions 19, the bit lines 12 and the final bit line isolation structures 17 form a bit line structure, and in a direction parallel to a plane of the substrate 100, a difference between a bottom width and a top width of the bit line structure is within a predetermined range, and the plurality of landing pads 18 disposed at intervals are located on the isolation widened portions 19 and the node contact portion 14.

It can be appreciated that the present application improves the shape of the top of the final bit line isolation structure 17 by providing the final bit line isolation structure 17 with the isolation widening portion 19, so that the landing pads 18 are better fixed on the top of the final bit line isolation structure 17, short circuits between adjacent landing pads 18 and peeling of the landing pads 18 are avoided, the failure rate is reduced, and thus, the electrical transmission performance and the product yield of the product can be improved, and the stability of the whole process is improved. In addition, the difference between the bottom width a and the top width b of the bit line structure is in the preset range, so that the top width of the bit line structure can be controlled, the uniformity is good, and the failure of the landing pad 18 is further avoided.

In some embodiments, the preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers. For example, the difference between the bottom width a and the top width b of the bit line structure is 0.2 nm. It will be appreciated that the smaller the difference between the bottom width a and the top width b of the bit line structure, the lower the risk of failure of the landing pad 18.

In some embodiments, the landing pad 18 includes a first sub-pad 182, a second sub-pad 183, and a third sub-pad 184 connecting the first sub-pad 182 and the second sub-pad 183, the first sub-pad 182 being located on the top surface of the isolation widened portion 19, the second sub-pad 183 being located on the top surface of the node contact portion 14, the third sub-pad 184 being located on the side surface of the isolation widened portion 19, wherein the third sub-pad 184 is disposed perpendicular or substantially perpendicular to the first sub-pad 182, the second sub-pad 183 is disposed parallel to the first sub-pad 182, and a surface of the second sub-pad 183 in contact with one of the terminal bit line isolation structures 17 is a plane.

It will be appreciated that the shape of the landing pad 18 of embodiments of the present application is changed compared to the shape of the landing pad 18 of the related art, due to the different shape of the final bit line isolation structure 17 of the present application and the final bit line isolation structure 17 of the related art. The contact area of the landing pad 18 with the node contact 14 is unchanged in embodiments of the present application.

In some embodiments, the edge of the landing pad 18 on the isolation widening 19 is flush with the edge of the isolation widening 19.

In summary, the embodiment of the application provides a semiconductor structure and a manufacturing method thereof, the manufacturing method comprises the steps of providing a substrate, wherein the substrate comprises a plurality of bit lines and an initial bit line isolation structure covering each bit line, the substrate further comprises node contact parts positioned between adjacent initial bit line isolation structures, removing part of the initial bit line isolation structures to obtain intermediate bit line isolation structures, depositing an isolation material layer on the substrate, wherein the isolation material layer fills gaps between adjacent intermediate bit line isolation structures, removing the isolation material layer positioned on the node contact parts to obtain a final bit line isolation structure with an isolation widening part, the isolation widening part is positioned on the intermediate bit line isolation structures, and a plurality of landing pads arranged at intervals are formed on the isolation widening part and the node contact parts.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A method for manufacturing a semiconductor structure, comprising: Providing a substrate, the substrate comprising a plurality of bit lines and an initial bit line isolation structure covering each of the bit lines, the substrate further comprising a node contact portion located between adjacent initial bit line isolation structures; removing part of the initial bit line isolation structure to obtain an intermediate bit line isolation structure; Depositing an isolation material layer on the substrate, wherein the isolation material layer fills the gap between adjacent intermediate bit line isolation structures; removing the isolation material layer located on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure; A plurality of landing pads arranged at intervals are formed on the isolation widening portion and the node contact portion. 2. The manufacturing method according to claim 1, characterized in that the initial bit line isolation structure comprises a first isolation layer, an intermediate isolation layer and a second isolation layer, the first isolation layer covers the bit line, the intermediate isolation layer is located on a side of the first isolation layer away from the bit line, and the second isolation layer is located on a side of the intermediate isolation layer away from the bit line; The removing part of the initial bit line isolation structure comprises: At least a portion of the second isolation layer is removed. 3 . The manufacturing method according to claim 2 , wherein the material of the isolation material layer is the same as that of the second isolation layer. 4. The manufacturing method according to any one of claims 1 to 3, characterized in that the removing of the isolation material layer located on the node contact portion to obtain a final bit line isolation structure having an isolation widening portion, wherein the isolation widening portion is located on the intermediate bit line isolation structure, comprises: The isolation material layer is subjected to chemical mechanical polishing treatment, and the isolation material layer located on the node contact portion is etched away, so that in a direction parallel to the plane where the substrate is located, the difference between the bottom width and the top width of the bit line structure is within a preset range. The bit line structure includes the bit line and the ultimate bit line isolation structure covering the bit line. 5 . The manufacturing method according to claim 4 , wherein the preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers. 6. The manufacturing method according to any one of claims 1 to 3, characterized in that forming a plurality of landing pads spaced apart on the isolation widening portion and the node contact portion comprises: Depositing a contact material layer and a landing material layer on the isolation widening portion and the node contact portion in sequence, wherein the contact material layer continuously covers the surface of the isolation widening portion and the surface of the node contact portion, and the landing material layer covers the contact material layer and at least fills the groove formed by the contact material layer; Part of the landing material layer and part of the contact material layer between adjacent isolation widening portions are removed to obtain a plurality of landing pads arranged at intervals. 7. The manufacturing method according to claim 6, characterized in that the landing pad comprises a first sub-pad, a second sub-pad and a third sub-pad connecting the first sub-pad and the second sub-pad, the first sub-pad is located on the top surface of the isolation widening portion, the second sub-pad is located on the top surface of the node contact portion, and the third sub-pad is located on the side of the isolation widening portion; The third sub-pad is arranged vertically or substantially vertically to the first sub-pad, the second sub-pad is arranged parallel to the first sub-pad, and the surface of the second sub-pad in contact with one of the ultimate bit line isolation structures is a plane. 8. A semiconductor structure, comprising: A substrate, the substrate comprising a plurality of bit lines and an ultimate bit line isolation structure covering each of the bit lines, the substrate further comprising a node contact portion located between adjacent ultimate bit line isolation structures, wherein the ultimate bit line isolation structure has an isolation widening portion, the bit lines and the ultimate bit line isolation structure constitute a bit line structure, and in a direction parallel to the plane where the substrate is located, a difference between a bottom width and a top width of the bit line structure is within a preset range; A plurality of landing pads are disposed at intervals and are located on the isolation widening portion and the node contact portion. 9 . The semiconductor structure according to claim 8 , wherein the preset range is greater than or equal to 0 and less than or equal to 0.5 nanometers. 10. The semiconductor structure according to claim 8 or 9, characterized in that the landing pad comprises a first sub-pad, a second sub-pad and a third sub-pad connecting the first sub-pad and the second sub-pad, the first sub-pad is located on the top surface of the isolation widening portion, the second sub-pad is located on the top surface of the node contact portion, and the third sub-pad is located on the side of the isolation widening portion; The third sub-pad is arranged vertically or substantially vertically to the first sub-pad, the second sub-pad is arranged parallel to the first sub-pad, and the surface of the second sub-pad in contact with one of the ultimate bit line isolation structures is a plane.