CN119479725A

CN119479725A - Storage device and control method thereof, and electronic device

Info

Publication number: CN119479725A
Application number: CN202311016963.6A
Authority: CN
Inventors: 章文强; 景蔚亮; 王正波; 廖恒
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2023-08-11
Filing date: 2023-08-11
Publication date: 2025-02-18
Also published as: WO2025035750A1

Abstract

The application provides a storage device, a control method thereof and electronic equipment, relates to the technical field of storage, and can further improve storage density while increasing current reading margin (SENSE MARGIN). The memory device includes a first memory cell and a differential sense amplifier electrically connected to the first memory cell. The first memory cell includes a first floating gate transistor and a second floating gate transistor. The first floating gate transistor and the second floating gate transistor are located in a subsequent process, and a metal oxide semiconductor ring channel type field effect transistor is adopted. The differential sense amplifier is located in the previous process and is connected to the sources of the first floating gate transistor and the second floating gate transistor simultaneously.

Description

Storage device, control method thereof and electronic equipment

Technical Field

The present application relates to the field of storage technologies, and in particular, to a storage device, a control method thereof, and an electronic apparatus.

Background

The memory cells of the current mainstream DRAM (dynamic random access memory ) products are mainly based on the 1T1C (1transistor 1capacitor) structure, i.e. one memory cell comprises one transistor and one capacitor. As process nodes evolve, memory density increases based on 1T1C structures are limited.

In recent years, in order to increase the memory density, researchers have provided a DRAM product employing a floating gate type transistor in which a single floating gate type transistor is employed for the memory cell C and the floating gate type transistor is manufactured in the preceding process, as shown in fig. 1. As shown in FIG. 2, the memory cell C has a "0" state and a "1" state. Due to process fluctuations, the read current Ird in both states is approximately normally distributed. Wherein, the read current Ird in the "0" state is smaller, and the read current Ird in the "1" state is larger. In performing a read operation, the read current is amplified by the sense amplifier SA (sensing amplifier) by setting the reference current Iref between a maximum read current in the "0" state and a minimum read current in the "1" state, and the read current is compared with the reference current Iref to read out the stored data. In this case, the current read margin (SENSE MARGIN) is small, corresponding to half the current difference between the maximum read current in the "0" state and the minimum read current in the "1" state, thus requiring very accurate sensitivity of the sense amplifier SA and high requirements for the design of the memory device.

Based on this, the present application provides an improved memory device that can further enhance the memory density while increasing the current read margin (SENSE MARGIN).

Disclosure of Invention

The application provides a memory device, a control method thereof and an electronic device, which can increase the current reading margin (SENSE MARGIN) and further improve the memory density.

The application provides a memory device, which comprises a first memory cell and a differential sense amplifier electrically connected with the first memory cell. The first memory cell includes a first floating gate transistor and a second floating gate transistor. The first floating gate transistor and the second floating gate transistor are located in a subsequent process, and an oxide semiconductor ring channel type field effect transistor is adopted. The differential sense amplifier is located in the previous process and is connected to the sources of the first floating gate transistor and the second floating gate transistor simultaneously.

In one aspect, in the memory device provided by the application, the memory cell adopts the first floating gate transistor and the second floating gate transistor, and the two floating gate transistors are connected to the same differential sense amplifier, that is, the memory cell adopts a differential 2T structure. In this way, when data reading operation is performed, the magnitude of the read currents of the two floating gate transistors is directly compared without setting reference currents, so that the stored data in the memory cell can be obtained, the current reading margin can be increased, and the reliability and stability of the reading operation can be well met.

On the other hand, in the memory device provided by the application, the first floating gate transistor and the second floating gate transistor in the memory cell adopt the OS CAA transistor (namely the floating gate oxide semiconductor ring channel type field effect transistor), the OS CAA transistor can meet the requirement of back end of line (BEOL) integration, and the differential sense amplifier is arranged in the front end of line (front end of line, FEOL) on the basis, so that the area cost of the differential sense amplifier is reduced, and the memory density can be further improved. Of course, the OS CAA transistor also has the advantages of small electric leakage, good retention property (relaxation), low-temperature preparation and the like.

In some possible implementations, the memory device includes a first memory array including a plurality of floating gate transistors, a plurality of word lines, a plurality of plate lines, and a plurality of bit lines arranged in an array. In the first memory array, the grid electrodes of the floating gate transistors in different rows are respectively connected with different word lines, the drain electrodes of the floating gate transistors in different rows are respectively connected with different plate lines, and the source electrodes of the floating gate transistors in different columns are respectively connected with different bit lines. Among the plurality of floating gate transistors arranged in an array, two adjacent floating gate transistors in the same row are respectively used as a first floating gate transistor and a second floating gate transistor in a first storage unit, and two bit lines connected with the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier. The first memory cells in different columns are connected to different differential sense amplifiers through bit lines.

In some possible implementations, the storage device includes a first storage array and a second storage array arranged in a same layer. The first storage array and the second storage array comprise a plurality of floating gate transistors, a plurality of word lines, a plurality of plate lines and a plurality of bit lines which are arranged in an array mode. In the first memory array and the second memory array, the grid electrodes of the floating gate transistors in different columns are connected to different word lines, the drain electrodes of the floating gate transistors in different columns are connected to different plate lines, and the source electrodes of the floating gate transistors in different rows are connected to different bit lines. Two floating gate transistors at corresponding positions in the first memory array and the second memory array are respectively used as a first floating gate transistor and a second floating gate transistor in the first memory cell, and two bit lines connected with the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier.

In some possible implementations, the first storage array and the second storage array are located on the same layer.

In some possible implementations, the first storage array and the second storage array are located at different layers.

Compared with the first storage array and the second storage array which can be integrated in the same layer, the storage density can be further improved by arranging the first storage array and the second storage array in different layers.

In some possible implementations, the first floating gate transistor includes a stacked structure, a first trench, a gate, a floating gate, a gate insulating layer, a channel layer. The laminated structure is arranged on the silicon substrate, and comprises a source electrode layer and a drain electrode layer, wherein the source electrode layer is close to the silicon substrate relative to the drain electrode layer. The first trench is disposed on the stacked structure, and extends into at least the source layer. The grid electrode is arranged in the first groove and extends to the depth of the source electrode layer. The floating gate is disposed in the first trench and disposed around the gate. The gate insulating layer is positioned between the gate and the floating gate. The channel layer covers the inner wall of the first trench and connects the source layer and the drain layer.

The present application also provides a control method of a storage device as provided in any one of the foregoing possible implementations, the control method including:

in performing a write operation, a high voltage is applied to the gate of the selected first floating gate transistor, a low voltage is applied to the source and drain, and a high voltage is applied to the source and drain of the selected second floating gate transistor, and a low voltage is applied to the gate. Or a high voltage is applied to the source and drain of the selected first floating gate transistor, a low voltage is applied to the gate, and a high voltage is applied to the gate of the selected second floating gate transistor, a low voltage is applied to the source and drain.

During a read operation, a high voltage is applied to the gates of the selected first and second floating gate transistors, a read voltage is applied to the drains of the selected first and second floating gate transistors, source currents of the selected first and second floating gate transistors are amplified by a differential sense amplifier, and stored data in the selected first memory cell is determined according to the source currents of the selected first and second floating gate transistors.

In some possible implementations, applying a high voltage to the gate, source and drain of the selected first floating gate transistor, and a low voltage to the source and drain of the selected second floating gate transistor, the gate applying a low voltage may include applying a high voltage to the gate, source and drain of the selected first floating gate transistor to write a "1" in the selected first floating gate transistor, applying a high voltage to the source and drain of the selected second floating gate transistor, and gate applying a low voltage to write a "0" in the selected second floating gate transistor, in which case a stored data "1" is written in the selected first memory cell.

In some possible implementations, the applying a high voltage to the source and drain of the selected first floating gate transistor and a low voltage to the gate, the applying a high voltage to the gate of the selected second floating gate transistor and a low voltage to the source and drain may include applying a high voltage to the source and drain of the selected first floating gate transistor and a low voltage to the gate to write a "0" in the selected first floating gate transistor, applying a high voltage to the gate of the selected second floating gate transistor and a low voltage to the source and drain to write a "1" in the selected second floating gate transistor, and in this case, writing a stored data "0" in the selected first memory cell.

In some possible implementations, determining the stored data in the selected first memory cell according to the source current of the selected first floating gate transistor and the second floating gate transistor may include determining that the stored data in the selected first memory cell is "1" when the source current of the selected first floating gate transistor is greater than the source current of the selected second floating gate transistor, and determining that the stored data in the selected first memory cell is "0" when the source current of the selected first floating gate transistor is less than the source current of the selected second floating gate transistor.

The application also provides an electronic device comprising a circuit board and a memory device as provided in any one of the possible implementations described above, the memory device being electrically connected to the circuit board.

Drawings

FIG. 1 is a schematic diagram of a memory cell according to the prior art;

FIG. 2 is a graph showing a read current distribution curve and a current read margin of a memory cell according to the prior art;

FIG. 3 is a schematic diagram of a memory cell according to an embodiment of the present application;

FIG. 4 is a graph showing a read current distribution curve and a current read margin of a memory cell according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a floating gate transistor in a memory cell according to an embodiment of the present application;

FIG. 6 is a circuit diagram of a memory array according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a memory array according to an embodiment of the present application;

FIG. 8 is a circuit diagram of a memory array according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a memory array according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a memory array according to an embodiment of the present application;

FIG. 11 is a schematic diagram illustrating a write operation control of a memory cell according to an embodiment of the present application;

FIG. 12 is a schematic diagram illustrating a write operation control of a memory cell according to an embodiment of the present application;

fig. 13 is a schematic diagram of read operation control of a memory cell according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," and the like in the description and in the claims and drawings are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or order. "and/or" is used to describe an association relationship of an associated object, and indicates that three relationships may exist, for example, "a and/or B" may indicate that only a exists, only B exists, and three cases of a and B exist simultaneously, where a and B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one" means one or more, and "a plurality" means two or more. "mounted," "connected," and the like are to be construed broadly and refer to, for example, an electrical connection or a mechanical connection, a fixed connection or a removable connection or an integral connection, or a direct connection or an indirect connection via an intermediary or a communication between two elements. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a series of steps or elements. The method, system, article, or apparatus is not necessarily limited to those explicitly listed but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus. "upper", "lower", "left", "right", etc. are used merely with respect to the orientation of the components in the drawings, these directional terms are relative terms, which are used for description and clarity with respect thereto, and which may vary accordingly depending on the orientation in which the components are placed in the drawings.

The embodiment of the application provides electronic equipment, which can be electronic products such as mobile phones, tablet computers, personal computers (personal computer, PC) vehicle-mounted computers, intelligent watches, intelligent bracelets, servers and the like.

The electronic device is provided with a circuit board and a storage device electrically connected with the circuit board. Of course, according to actual needs, other devices may also be disposed in the electronic device, such as a processor, an input/output (I/O) device, a positioning module, a bluetooth module, a sensor, a Wi-Fi module, and so on.

In order to solve the problems of small current reading margin (SENSE MARGIN), low storage density and the like of the existing storage device, the embodiment of the application provides a novel storage device, wherein a storage unit in the storage device adopts a differential 2T structure based on a floating gate oxide semiconductor (oxide semiconductor, OS) ring Channel (CAA) field effect transistor (which can be called as a floating gate OS CAA transistor for short), and the storage density can be improved while the current reading margin (SENSE MARGIN) is increased by adopting the storage unit with the differential 2T structure.

The storage device provided by the embodiment of the application can be a device with a storage function such as a DRAM, a cache, a content addressing memory and the like, and the application does not limit the setting form of the storage device. The following embodiments will each take the memory device as a DRAM as an example.

The following describes a specific structure of a memory device according to an embodiment of the present application.

In an exemplary embodiment, a memory device is provided, in which a memory cell (may also be referred to as a first memory cell) with a novel structure is adopted, as shown in fig. 3, the memory cell C1 includes a first floating gate transistor T1 and a second floating gate transistor T2, and the first floating gate transistor T1 and the second floating gate transistor T2 are disposed in a subsequent process (BEOL). Among them, the first floating gate transistor T1 and the second floating gate transistor T2 each employ a ring channel type (CAA) field effect transistor of an Oxide Semiconductor (OS), which may be simply referred to as a floating gate OS CAA transistor.

It should be appreciated that in the fabrication of prior memory devices, the transistors in the memory cells were fabricated by a front end of line (front end of line, FEOL), i.e., a plurality of transistors were fabricated on the substrate by a front end of line (FEOL).

In contrast, the transistors (T1, T2) in the memory cell C1 of the present application employ floating gate OS CAA transistors, which can be integrated in the back end of line (BEOL). In addition, the floating gate OS CAA transistor also has the advantages of small electric leakage, good retention property (relaxation), low-temperature preparation and the like, and has great potential in the application of a 4F ² DRAM. Where F is the feature size at the process node.

Schematically, as shown in fig. 3, in the memory cell C1, gates of the first and second floating gate transistors T1 and T2 may be connected to a word line WL (word line), and drains of the first and second floating gate transistors T1 and T2 may be connected to a plate line PL (plate line). The source of the first floating gate transistor T1 and the source of the second floating gate transistor T2 are connected to the differential sense amplifier 100 through different bit lines BL (bit lines) (DIFFERENTIAL SENSING AMPLIFIER).

In this way, when writing the stored data, the writing of the data in the memory cell C1 can be achieved by writing "0" and "1" in the two transistors (T1, T2), respectively, and reference is made to the following description. When the stored data is read, the differential sense amplifier 100 can compare the read currents of the two transistors (T1, T2), and the stored data in the memory cell C1 can be obtained according to the magnitudes of the read currents of the two transistors (T1, T2).

Referring to fig. 2 and 4, compared with the conventional current read margin (SENSE MARGIN) which is only equivalent to half of the current difference between the maximum read current in the "0" state and the minimum read current in the "1" state of the transistors, the present application is based on the differential 2T structure, without setting the reference current Iref, and can directly compare the magnitudes of the read currents of the two transistors (T1, T2) when the stored data is read, thereby obtaining the stored data in the memory cell C1.

That is, the current read margin (SENSE MARGIN) of the present application is about the difference between the maximum read current in the "0" state and the minimum read current in the "1" state of the transistor, which is equivalent to twice the current read margin of the prior art, with a significant improvement, thereby greatly improving the reliability and stability of the read operation.

In the present application, for the write operation of the memory cell C1 using the differential 2T structure, the data written into the memory cell C1 can be defined by writing "1" and "0" into the first floating gate transistor T1 and the second floating gate transistor T2, respectively.

For example, in some possible implementations, "1" is written in the first floating gate transistor T1, "0" is written in the second floating gate transistor T2, defining the written data in the memory cell C1 as "1", while "0" is written in the first floating gate transistor T1, and "1" is written in the second floating gate transistor T2, defining the written data in the memory cell C1 as "0".

Illustratively, the control process of writing "1" or "0" in the floating gate transistor is described taking the first floating gate transistor T1 as an example. Referring to fig. 3, when writing "1" in the first floating gate transistor T1, a high voltage may be applied to the gate of the first floating gate transistor T1 through the word line WL, a low voltage (e.g., ground) may be applied to the drain and source of the first floating gate transistor T1 through the plate line PL and the bit line BL0, respectively, in which case electron tunneling occurs between the floating gate and the channel (channel), a large amount of electrons enter the channel (channel), the electrons remain in the refloated gate when the voltage is removed, the writing state is 1, when writing "0" in the first floating gate transistor T1, a low voltage (e.g., ground) may be applied to the gate of the first floating gate transistor T1 through the word line WL, and a high voltage may be applied to the drain and source of the first floating gate transistor T1 through the plate line PL and the bit line BL0, respectively, in which case electrons tunnel from the floating gate to the channel (channel) through the oxide layer, the electrons are lost, and the writing state is 0.

Of course, in other possible implementations, "1" may be written in the first floating gate transistor T1, "0" may be written in the second floating gate transistor T2, defining the write data in the memory cell C1 as "0", while "0" may be written in the first floating gate transistor T1, "1" may be written in the second floating gate transistor T2, defining the write data in the memory cell C1 as "1".

It should be understood that, although the threshold voltage (Vt) of the floating gate OS CAA transistor (T1, T2) is easily shifted due to the high temperature effect of the subsequent process, and thus the process deviation of the threshold voltage (Vt) is increased in the present application, the reliability and stability of the read operation can be well satisfied by greatly improving the current read margin (SENSE MARGIN) based on the differential 2T memory cell of the present application.

In the present application, since the floating gate OS CAA transistors (T1, T2) are integrated in the back end of line (BEOL), the differential sense amplifier 100 can be integrated in the front end of line (FEOL). I.e. the differential sense amplifier 100 is fabricated directly on the substrate by a front end of line (FEOL) followed by integrating the memory cell C1 over the differential sense amplifier 100 by a back end of line (BEOL). In this way, the area overhead of the differential sense amplifier 100 can be reduced, and the memory density can be improved.

The structure of floating gate OS CAA transistors (T1, T2) integrated in the subsequent process will be briefly described below.

Schematically, an embodiment of the present application provides a floating gate OS CAA transistor, as shown in fig. 5, which may include a silicon substrate 10 and a stacked structure 20 disposed on the silicon substrate 10.

As shown in fig. 5, the stacked structure 20 includes a source layer S and a drain layer D, and the source layer S is adjacent to the silicon substrate 10 with respect to the drain layer D. The source layer S serves as the source of the floating gate OS CAA transistor and the drain layer D serves as the drain of the floating gate OS CAA transistor. Of course, another film layer such as a dielectric layer may be provided between the source layer S and the drain layer D.

As shown in fig. 5, a first trench 200 is provided on the stacked structure 20, and the first trench 200 extends to a depth region where the source layer S is located. A gate G (gate), a floating gate FG (floating gate), a gate insulating layer 201, and a channel layer 202 of the floating gate OS CAA transistor are disposed in the first trench 200. The floating gate FG is disposed around the gate G. A gate insulating layer 201 is filled between the gate G and the floating gate FG. The channel layer 202 covers the inner wall of the first trench 200 and connects the source layer S and the drain layer D. Of course, according to practical requirements, a portion of the structure (such as the gate G) may extend to the outside of the first trench 200 to be connected with other wirings.

In addition, the memory cell of the differential 2T structure adopted in the present application may be differential in a single memory array or may be differential in two memory arrays, and the two array integration methods will be described below by way of specific embodiments.

Example 1

As shown in fig. 6, the first embodiment provides a memory device including a memory array A1 (may also be referred to as a first memory array), where the memory cells C1 implement a difference in the memory array A1.

Schematically, as shown in FIG. 6, the memory Array A1 (Array) includes a plurality of floating gate transistors, a plurality of word lines (WL 0, WL1, WL2, WL 3), a plurality of plate lines (PL 0, PL1, PL2, PL 3), and a plurality of bit lines (BL 0, BL1, BL2, BL3, BL4, BL 5) arranged in an Array. Among the plurality of floating gate transistors arranged in the array, the plurality of floating gate transistors along the row direction may be first floating gate transistors T1 and second floating gate transistors T2 alternately arranged in sequence, and the first floating gate transistors T1 and the second floating gate transistors T2 adjacently arranged form a memory cell C1. Along the column direction may be a first floating gate transistor T1 or a second floating gate transistor T2. In this case, a plurality of memory cells C1 arranged in an array are formed in the memory array A1.

As shown in reference 6, in the memory array A1:

The gates of the floating gate transistors (T1, T2) located in different rows are connected to different word lines (WL 0, WL1, WL2, WL 3). For example, the gates of the plurality of floating gate transistors (T1, T2) in the first row are connected to the word line WL0, and the gates of the plurality of floating gate transistors (T1, T2) in the second row are connected to the word line WL 1.

Drains of floating gate transistors (T1, T2) located in different rows are connected to different plate lines (PL 0, PL1, PL2, PL 3). For example, drains of the plurality of floating gate transistors (T1, T2) in the first row are connected to the plate line PL0, and drains of the plurality of floating gate transistors (T1, T2) in the second row are connected to the plate line PL 1.

The sources of the floating gate transistors (T1, T2) located in different columns are connected to different bit lines (BL 0, BL1, BL2, BL3, BL4, BL 5). For example, the sources of the first floating gate transistors T1 in the first column are connected to the bit line BL0, and the drains of the second floating gate transistors T2 in the second column are connected to the bit line BL 1.

As shown in fig. 6, two bit lines (BL 0 and BL1, BL2 and BL3, BL4 and BL 5) connected to the same column of memory cells C1 are connected to the same differential sense amplifier 100, and bit lines connected to different memory cells C1 are connected to different differential sense amplifiers 100. For example, two bit lines (BL 0, BL 1) connected to the first column of memory cells C1 are connected to one differential sense amplifier 100, and two bit lines (BL 2, BL 3) connected to the second column of memory cells C1 are connected to the other differential sense amplifier 100.

Fig. 7 is a schematic cross-sectional view of a memory device according to a first embodiment.

Referring to fig. 7, in some possible implementations, for the memory device in the first embodiment, a plurality of differential sense amplifiers 100 may be fabricated on a substrate by a previous process (FEOL), and then the memory array A1 and the related signal lines (word lines WL, plate lines PL, bit lines BL) may be formed by a subsequent process (BEOL) in the direction of the plurality of differential sense amplifiers 100.

Example two

In a second embodiment, a memory device is provided, where the memory device includes a first memory array A1 and a second memory array A2, and the memory cells C1 are differentiated in the two memory arrays (A1, A2).

The arrangement of the first memory array A1 and the second memory array A2 will be described below.

Schematically, as shown in fig. 8, the first memory array A1 includes a plurality of first floating gate transistors T1, a plurality of word lines (WLL 0, WLL1, WLL2, WLL 3), a plurality of plate lines (PLL 0, PLL1, PLL2, PLL 3), and a plurality of bit lines (BLL 0, BLL1, BLL2, BLL3, BLL4, BLL 5) arranged in an array.

In the first memory array A1:

The gates of the first floating gate transistors T1 located in different columns are connected to different word lines (WLL 0, WLL1, WLL2, WLL 3). For example, the gates of the plurality of first floating gate transistors T1 in the first column are connected to the word line WLL0, and the gates of the plurality of first floating gate transistors T1 in the second column are connected to the word line WLL 1.

The drains of the first floating gate transistors T1 located in different columns are connected to different plate lines (PLL 0, PLL1, PLL2, PLL 3). For example, the drains of the plurality of first floating gate transistors T1 in the first column are connected to the word line PLL0, and the drains of the plurality of first floating gate transistors T1 in the second column are connected to the word line PLL 1.

The sources of the first floating gate transistors T1 located in different rows are connected to different bit lines (BLL 0, BLL1, BLL2, BLL3, BLL4, BLL 5). For example, the sources of the plurality of first floating gate transistors T1 in the first row are connected to the bit line BLL0, and the drains of the plurality of first floating gate transistors T1 in the second row are connected to the bit line BLL 1.

Schematically, as shown in fig. 8, the second memory array A2 includes a plurality of second floating gate transistors T2, a plurality of word lines (WLR 0, WLR1, WLR2, WLR 3), a plurality of plate lines (PLR 0, PLR1, PLR2, PLR 3), and a plurality of bit lines (BLR 0, BLR1, BLR2, BLR3, BLR4, BLR 5) arranged in an array.

In the first memory array A2:

The gates of the second floating gate transistors T2 located in different columns are connected to different word lines (WLR 0, WLR1, WLR2, WLR 3). For example, the gates of the plurality of second floating gate transistors T2 located in the first column are connected to the word line WLR0, and the gates of the plurality of second floating gate transistors T2 located in the second column are connected to the word line WLR 1.

The drains of the second floating gate transistors T2 located in different columns are connected to different plate lines (PLR 0, PLR1, PLR2, PLR 3). For example, the drains of the plurality of second floating gate transistors T2 located in the first column are connected to the word line PLR0, and the drains of the plurality of second floating gate transistors T2 located in the second column are connected to the word line PLR 1.

The sources of the second floating gate transistors T2 located in different rows are connected to different bit lines (BLR 0, BLR1, BLR2, BLR3, BLR4, BLR 5). For example, the sources of the plurality of second floating gate transistors T2 located in the first row are connected to the bit line BLR0, and the drains of the plurality of second floating gate transistors T2 located in the second row are connected to the bit line BLR 1.

On this basis, as shown in fig. 8, two floating gate transistors at corresponding positions in the first memory array A1 and the second memory array A2 may be respectively used as the first floating gate transistor T1 and the second floating gate transistor T2 in the first memory cell C1. For example, a first floating gate transistor T1 located in a first row and a first column of the first memory array A1 and a second floating gate transistor T2 located in a first row and a first column of the second memory array A2 form one memory cell C1. The first floating gate transistor T1 located in the first row and the second column of the first memory array A1 and the second floating gate transistor T2 located in the first row and the second column of the second memory array A2 form one memory cell C1.

Of course, the two floating gate transistors (T1, T2) in the memory cell C1 may also be distributed at non-corresponding positions in the two memory arrays (A1, A2), which is not limited in the present application.

In this case, as shown in fig. 8, two bit lines connected to two floating gate transistors (T1, T2) in the same memory cell C1 should be connected to the same differential sense amplifier 100. For example, the bit line BLL0 connected to the first floating gate transistor T1 of the first row and the first column in the first memory array A1 and the bit line BLR0 connected to the second floating gate transistor T2 of the first row and the first column in the second memory array A2 are connected to the same differential sense amplifier 100. The bit line BLL1 connected to the first floating gate transistor T1 of the second row and first column in the first memory array A1 and the bit line BLR1 connected to the second floating gate transistor T2 of the second row and first column in the second memory array A2 are connected to the same differential sense amplifier 100.

In addition, in the second embodiment, the first storage array A1 and the second storage array A2 may be integrated in the same layer or may be integrated in different layers, which is not limited in the present application, and may be actually set as required.

For example, as shown in fig. 9, in some possible implementations, the first storage array A1 and the second storage array A2 may be integrated in the same layer. In this case, a plurality of differential sense amplifiers 100 (only one is shown in fig. 9) may be fabricated on a substrate using a front end of line (FEOL), and then the first and second memory arrays A1 and A2 and associated signal lines (word lines WL, plate lines PL, bit lines BL) and the like provided in the same layer may be formed by a back end of line (BEOL) above the plurality of differential sense amplifiers 100.

As another example, as shown in fig. 10, in some possible implementations, the first memory array A1 and the second memory array A2 may be integrated in different layers, and the second memory array A2 may be located between the first memory array A1 and the differential sense amplifier 100. In this case, a plurality of differential sense amplifiers 100 (only one is shown in fig. 10) may be fabricated on the substrate using a front end of line (FEOL), and then the second memory array A2 is fabricated through a back end of line (BEOL) over the plurality of differential sense amplifiers 100, and then the first memory array A1 is fabricated over the second memory array A2. Of course, the relevant signal lines (word line WL, plate line PL, bit line BL) may be fabricated at the same time in the subsequent process (BEOL).

It is understood that the storage density can be further improved by providing the first storage array A1 and the second storage array A2 at different layers, compared to the case where the first storage array A1 and the second storage array A2 can be integrated at the same layer.

The second embodiment also provides a method for controlling read/write operations of the memory device as illustrated in fig. 8, which may be specifically described as follows (the floating gate transistor marked by the dotted line box represents the selected floating gate transistor)

When a write "1" operation is performed:

Referring to fig. 11, in the first memory array A1, a high voltage (denoted as 1) is applied to the gate of a selected first floating gate transistor T1 through a word line WLL0, and a low voltage (denoted as 0) is applied to the source and drain of the selected first floating gate transistor T1 through a plate line PLL0 and a bit line BLL0, which may be grounded. Other unselected bit lines input a high voltage (1), and other unselected word lines and plate lines may input a low voltage (0). In this case, "1" is written in the selected first floating gate transistor T1.

Referring to fig. 11, in the second memory array A2, a low voltage (0) is applied to the gate of the selected second floating gate transistor T2 through the word line WLR0, which may be grounded. A high voltage (1) is applied to the source and drain of the selected second floating gate transistor T2 through the plate line PLR0 and the bit line BLR 0. Other unselected word lines, plate lines, bit lines may input a low voltage (0). In this case, "0" is written in the selected second floating gate transistor T2.

The selected first floating gate transistor T1 and the selected second floating gate transistor T2 are two transistors in the selected memory cell C1, and when "1" is written in the first floating gate transistor T1 and "0" is written in the second floating gate transistor T2, "1" is written in the selected memory cell C1.

When a write "1" operation is performed:

Referring to fig. 12, in the first memory array A1, a low voltage (0) is applied to the gate of the selected first floating gate transistor T1 through the word line WLL0, which may be grounded. A high voltage (1) is applied to the source and drain of the selected first floating gate transistor T1 through the plate line PLL0 and the bit line BLL 0. Other unselected word lines, plate lines, bit lines may input a low voltage (0). In this case, "0" is written in the selected first floating gate transistor T1.

Referring to fig. 12, in the second memory array A2, a high voltage (denoted as 1) is applied to the gate of the selected second floating gate transistor T2 through the word line WLR0, and a low voltage (denoted as 0) is applied to the source and drain of the selected second floating gate transistor T2 through the plate line PLR0 and the bit line BLR0, which may be grounded. Other unselected bit lines input a high voltage (1), and other unselected word lines and plate lines may input a low voltage (0). In this case, "1" is written in the selected second floating gate transistor T2.

The selected first floating gate transistor T1 and the selected second floating gate transistor T2 are two transistors in the selected memory cell C1, and when "0" is written in the first floating gate transistor T1 and "1" is written in the second floating gate transistor T2, "0" is written in the selected memory cell C1.

Of course, in other possible implementations, in the case where "1" is written in the first floating gate transistor T1 and "0" is written in the second floating gate transistor T2 in the memory cell C1, the stored data written in the memory cell C1 is defined as "0", and in the case where "1" is written in the first floating gate transistor T1 and "0" is written in the second floating gate transistor T2, the stored data written in the selected memory cell C1 is defined as "1".

Referring to fig. 13, when a read operation is performed:

A high voltage is applied to the gates of the selected first and second floating gate transistors T1 and T2 through the word lines WLL0 and WLR0, respectively, and a read voltage is applied to the drains of the selected first and second floating gate transistors T1 and T2 through the plate lines PLL0 and PLR0, respectively.

The source currents of the selected first and second floating gate transistors T1 and T2 are read amplified by the differential sense amplifier 100.

The stored data in the selected memory cell C1 is determined according to the source current magnitudes of the selected first and second floating gate transistors T1 and T2.

Illustratively, in some possible implementations, the source current of the selected first floating gate transistor T1 is greater than the source current of the selected second floating gate transistor T2, which means "1" in the first floating gate transistor T1 and "0" in the second floating gate transistor T2, in which case it may be determined that the stored data in the selected memory cell C1 is "1". Correspondingly, when the source current of the selected first floating gate transistor T1 is smaller than the source current of the selected second floating gate transistor T2, this means that "0" is in the first floating gate transistor T1, and "1" is in the second floating gate transistor T2, in this case, it is determined that the stored data in the selected memory cell C1 is "0".

Of course, in other possible implementations, the source current of the selected first floating gate transistor T1 is greater than the source current of the selected second floating gate transistor T2, and the stored data in the selected memory cell C1 may be determined to be "0", and the stored data in the selected memory cell C1 may be determined to be "1" when the source current of the selected first floating gate transistor T1 is less than the source current of the selected second floating gate transistor T2. In practice, the design can be carried out according to the requirements.

For the memory device employing a single memory array in the first embodiment, the control method of the read/write operation is similar to that in the second embodiment, but only the difference is that the two floating gate transistors (T1, T2) in the selected memory cell C1 can be written with data in two times, for example, the first time "1" is written in the first floating gate transistor T1 and the second time "0" is written in the second floating gate transistor T2, and the detailed description will refer to the corresponding parts in the second embodiment and will not be repeated here.

The connection between the source and the drain of the transistor (T1, T2) according to the present application is merely an example, and in some cases, the source and the drain of the transistor (T1, T2) according to the present application may not be clearly distinguished, and thus the corresponding connection relationship may be interchanged.

It should be further noted that the "rows" and "columns" referred to in the present application are only one set of relative directions, and the present application is not limited thereto. In some cases the "row" direction is transverse, the "column" direction is longitudinal, and in some cases the "row" direction is longitudinal, and the "column" direction is transverse.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A memory device, comprising a first memory cell and a differential sense amplifier;

the first storage unit comprises a first floating gate transistor and a second floating gate transistor which are positioned in a subsequent process, wherein the first floating gate transistor and the second floating gate transistor adopt oxide semiconductor ring channel type field effect transistors;

The source electrode of the first floating gate transistor and the source electrode of the second floating gate transistor are connected to the differential sense amplifier, and the differential sense amplifier is located in the previous procedure.

2. The storage device of claim 1, wherein the memory is configured to store the data,

The memory device includes a first memory array;

the first memory array comprises a plurality of floating gate transistors, a plurality of word lines, a plurality of plate lines and a plurality of bit lines which are arranged in an array manner;

In the first storage array, the grid electrodes of the floating gate transistors positioned in different rows are respectively connected with different word lines, and the drain electrodes of the floating gate transistors positioned in different rows are respectively connected with different plate lines;

among the plurality of floating gate transistors arranged in the array, two adjacent floating gate transistors positioned in the same row are respectively used as the first floating gate transistor and the second floating gate transistor in the first storage unit, and two bit lines connected with the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier;

The first memory cells located in different columns are connected to different ones of the differential sense amplifiers through the bit lines.

3. The storage device of claim 1, wherein the memory is configured to store the data,

The memory device comprises a first memory array and a second memory array which are arranged in the same layer;

the first storage array and the second storage array comprise a plurality of floating gate transistors, a plurality of word lines, a plurality of plate lines and a plurality of bit lines which are arranged in an array manner;

In the first memory array and the second memory array, the grid electrodes of the floating gate transistors positioned in different columns are connected to different word lines, the drain electrodes of the floating gate transistors positioned in different columns are connected to different plate lines;

two floating gate transistors at corresponding positions in the first memory array and the second memory array are respectively used as the first floating gate transistor and the second floating gate transistor in the first memory cell, and two bit lines connected with the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier.

4. The storage device of claim 3, wherein,

The first storage array and the second storage array are located on the same layer.

5. The storage device of claim 3, wherein,

The first storage array and the second storage array are located in different layers.

6. The storage device according to any one of claims 1 to 5, wherein,

The first floating gate transistor includes:

a stacked structure provided on a silicon substrate, the stacked structure including a source layer and a drain layer, the source layer being close to the silicon substrate with respect to the drain layer;

A first trench disposed on the stacked structure, the first trench extending into at least the source layer;

the grid electrode is arranged in the first groove and extends to the depth of the source electrode layer;

The floating gate is arranged in the first groove and surrounds the grid electrode;

a gate insulating layer located between the gate and the floating gate;

and the channel layer covers the inner wall of the first groove and is connected with the source electrode layer and the drain electrode layer.

7. A control method of a storage device according to any one of claims 1 to 6, comprising:

when a write operation is performed:

applying a high voltage to the gate of the selected first floating gate transistor, and applying a low voltage to the source and drain of the selected second floating gate transistor;

applying a high voltage to the source and drain of the selected first floating gate transistor, and applying a low voltage to the gate of the selected second floating gate transistor;

when a read operation is performed:

Applying a high voltage to the gates of the selected first and second floating gate transistors and applying a read voltage to the drains of the selected first and second floating gate transistors;

Amplifying source currents of the selected first floating gate transistor and the second floating gate transistor by the differential sense amplifier;

And determining the stored data in the selected first memory cell according to the source current of the selected first floating gate transistor and the second floating gate transistor.

8. The method for controlling a memory device according to claim 7, wherein,

And applying a high voltage to the selected source and drain of the second floating gate transistor, the gate applying a low voltage comprising:

Applying a high voltage to the gate of the selected first floating gate transistor, and applying a low voltage to the source and drain to write "1" in the selected first floating gate transistor;

Applying a high voltage to the source and drain of the selected second floating gate transistor and a low voltage to the gate to write a "0" in the selected second floating gate transistor;

Writing storage data '1' in the selected first storage unit.

9. The method for controlling a memory device according to claim 7 or 8, wherein,

The method for applying high voltage to the source electrode and the drain electrode of the selected first floating gate transistor and applying low voltage to the gate electrode of the selected second floating gate transistor comprises the following steps:

applying a high voltage to the source and drain of the selected first floating gate transistor and a low voltage to the gate to write a "0" in the selected first floating gate transistor;

applying a high voltage to the gate of the selected second floating gate transistor, and applying a low voltage to the source and drain to write "1" in the selected second floating gate transistor;

Writing storage data '0' in the selected first storage unit.

10. A control method of a storage device according to any one of claims 7 to 9,

The determining the stored data in the selected first memory cell according to the source current magnitude of the selected first floating gate transistor and the second floating gate transistor comprises the following steps:

When the source current of the selected first floating gate transistor is larger than that of the selected second floating gate transistor, determining that the stored data in the selected first memory cell is 1;

And when the source current of the selected first floating gate transistor is smaller than that of the selected second floating gate transistor, determining that the stored data in the selected first memory cell is 0.

11. An electronic device comprising a circuit board and a memory device according to any one of claims 1-6, said memory device being electrically connected to said circuit board.