CN119473939A - Data processing device, method and related equipment - Google Patents
Data processing device, method and related equipment Download PDFInfo
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Abstract
本申请提出一种数据处理装置、方法及相关设备，该装置包括控制模块、第一地址转换旁路缓冲器及多个第二地址转换旁路缓冲器；控制模块被配置为：接收DMA请求，基于第一地址转换旁路缓冲器确定DMA请求对应的描述符物理地址；基于DMA请求对应的描述符物理地址，向内存模块发送DMA请求；接收内存模块回流的描述符；基于描述符内的目标虚拟地址，以及DMA请求对应的第二地址转换旁路缓冲器确定DMA请求对应的目标物理地址；基于目标物理地址对述DMA请求进行处理。本申请根据DMA请求的类型，为不同类型的请求设置不同的第二地址转换旁路缓冲器，在处理请求时，根据请求的类型，基于对应的第二地址转换旁路缓冲器进行地址转换，转换时的效率和成功率均更高。
The present application proposes a data processing device, method and related equipment, the device includes a control module, a first address translation bypass buffer and a plurality of second address translation bypass buffers; the control module is configured to: receive a DMA request, determine the descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer; send a DMA request to a memory module based on the descriptor physical address corresponding to the DMA request; receive the descriptor returned by the memory module; determine the target physical address corresponding to the DMA request based on the target virtual address in the descriptor and the second address translation bypass buffer corresponding to the DMA request; process the DMA request based on the target physical address. The present application sets different second address translation bypass buffers for different types of requests according to the type of DMA request, and when processing a request, performs address conversion based on the corresponding second address translation bypass buffer according to the type of request, and the efficiency and success rate of the conversion are higher.
Description
Technical Field
The present application relates to the field of computers, and in particular, to a data processing apparatus, a data processing method, and related devices.
Background
When a computer system processes a direct memory access (Direct Memory Access, DMA) request, a target virtual address of the DMA request needs to be converted into a target physical address, and then the DMA request is processed based on the target physical address, and the process of converting the target virtual address into the target physical address can be realized through a Page Table (Page Table), wherein the Page Table records the mapping relation between the target virtual address and the target physical address corresponding to various DMA requests, however, the Page Table is larger, and the mapping relation stored in the Page Table is more, so that the efficiency is lower when the traversal query conversion is performed based on the Page Table.
Therefore, currently, an address translation bypass buffer (Translation Lookaside Buffer, TLB) is often used to cache the mapping relationship between the target virtual address and the target physical address that is most recently used or most likely to be accessed, and query translation is preferentially performed based on the TLB during translation, and if the TLB caches the mapping relationship between the target virtual address and the target physical address corresponding to the DMA request, the translation can be performed quickly.
However, the memory space of the TLB is limited, and only a small amount of mapping relationships can be cached, which restricts the success rate of query translation by the TLB.
Disclosure of Invention
The application mainly aims to provide a data processing device, a method and related equipment, and aims to solve the problems that in the prior art, the memory space of a TLB is limited, and the success rate is low when a virtual address and a physical address are inquired and converted based on the TLB.
In order to achieve the above object, the present application provides a data processing apparatus, comprising a control module, a first address translation bypass buffer and a plurality of second address translation bypass buffers;
the first address conversion bypass buffer is used for buffering a first mapping relation, and one first mapping relation comprises a corresponding relation between a source address corresponding to a DMA request and a physical address of a descriptor; each second address conversion bypass buffer is used for caching a second mapping relation, and each second mapping relation comprises a corresponding relation between a target virtual address and a target physical address corresponding to a type of DMA request, wherein descriptors in a memory module are used for storing the target virtual address of the DMA request;
the control module is configured to determine, in response to receiving a DMA request, a descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer;
Transmitting the DMA request to the memory module based on the physical address of the descriptor corresponding to the DMA request;
receiving a descriptor corresponding to the DMA request, which is returned by the memory module;
determining a target physical address corresponding to the DMA request based on a target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request;
and processing the DMA request based on the target physical address.
In an embodiment of the present application, the data processing apparatus further includes a queue module, where the queue module includes a plurality of queue units, each queue unit is configured to cache DMA requests, and types of DMA requests in a same queue unit are the same, and DMA requests in a same queue unit correspond to a same source address.
In the embodiment of the application, the memory module is further configured to store a plurality of descriptors in a storage space corresponding to the same source address and used for storing the descriptors;
the memory module is further configured to determine a number of reflow descriptors to the control module based on a size of target data requested by the DMA request.
In an embodiment of the application, the DMA request comprises the following types of a Magic request, a DIRECT WRITE request, a Infeed request, a Outfeed request and a Debug request;
two second address translation bypass buffers are provided, and the two second address translation bypass buffers are respectively used for caching Infeed the corresponding second mapping relation requested by the request and Outfeed the corresponding second mapping relation requested by the request;
And the data processing device is not provided with a second address translation bypass buffer corresponding to the Magic request, the DIRECT WRITE request and the Debug request.
The queue module is further configured to configure a first number of queue elements for Infeed requests, a second number of queue elements for Outfeed requests, a third number of queue elements for DIRECT WRITE requests, and a fourth number of queue elements for both Magic requests and Debug requests;
The first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number.
In the embodiment of the application, the control module is further configured to, when receiving the descriptor corresponding to the Magic request or the DIRECT WRITE request or the Debug request, look up a page table based on the target virtual address in the descriptor to determine the target physical address corresponding to each DMA request.
The application also provides a data processing method, which comprises the following steps:
Receiving a DMA request, and determining a descriptor physical address corresponding to the DMA request based on a first address translation bypass buffer;
Transmitting the DMA request to a memory module based on the physical address of the descriptor corresponding to the DMA request;
receiving a descriptor corresponding to the DMA request, which is returned by the memory module;
determining a target physical address corresponding to the DMA request based on a target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request;
processing the DMA request based on the target physical address;
The first address conversion bypass buffer is used for caching a first mapping relation, the first mapping relation comprises source addresses of the DMA requests, corresponding relations of descriptors corresponding to the DMA requests and physical addresses in the memory module, each second address conversion bypass buffer is used for caching a second mapping relation, each second mapping relation comprises corresponding relations of a target virtual address corresponding to one type of DMA requests and a target physical address, and the descriptors in the memory module are used for storing the target virtual addresses of the DMA requests.
In an embodiment of the present application, before receiving a DMA request and determining a physical address of a descriptor corresponding to the DMA request based on a first address translation bypass buffer, the method further includes:
the method comprises the steps of pre-configuring a queue module, wherein the queue module comprises a plurality of queue units, configuring DMA requests of the same type in the same queue unit, and setting the same source address for the DMA requests in the same queue unit.
In the embodiment of the application, a plurality of descriptors are stored in a physical address of a storage descriptor corresponding to the same source address;
the number of reflow descriptors to the control module is determined based on the size of the target data requested by the DMA request sent to the memory module.
In an embodiment of the application, the DMA request comprises the following types of a Magic request, a DIRECT WRITE request, a Infeed request, a Outfeed request and a Debug request;
Before receiving the DMA request and determining the physical address of the descriptor corresponding to the DMA request based on the first address translation bypass buffer, the data processing method further comprises:
second address translation bypass buffers are set for the Infeed and Outfeed requests, respectively, to cache the respective second mappings for the Infeed and Outfeed requests, respectively, and there is no need to set second address translation bypass buffers for the Magic, DIRECT WRITE and Debug requests.
In an embodiment of the present application, the pre-configured queue module includes:
And configuring a first number of queue units for the Infeed requests, a second number of queue units for the Outfeed requests, a third number of queue units for the DIRECT WRITE requests, and a fourth number of queue units for both the Magic requests and the Debug requests, wherein the first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number.
In an embodiment of the present application, after receiving a descriptor corresponding to the DMA request and reflowed by the memory module, the method further includes:
When the descriptor corresponding to the Magic request or the DIRECT WRITE request or the Debug request is received, a page table is searched based on the target virtual address in the descriptor corresponding to each DMA request, so as to determine the target physical address corresponding to each DMA request.
The embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, which when being executed by a processor, implements the method of any one of the above.
The embodiment of the application also provides a chip, which comprises the data processing device of any embodiment.
In the embodiment of the application, different second address conversion bypass buffers are arranged for the mapping relation between the target virtual addresses and the target physical addresses corresponding to different types of DMA requests according to the types of the DMA requests, and when the DMA requests are processed, the conversion of the target virtual addresses and the target physical addresses is carried out based on the corresponding second address conversion bypass buffers according to the types of the DMA requests.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an application scenario of a data processing apparatus according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a memory module according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a first mapping relationship according to an embodiment of the application;
FIG. 4 is a schematic diagram of a first memory area according to an embodiment of the application;
FIG. 5 is a diagram of a queue module according to one embodiment of the application;
FIG. 6 is a schematic diagram illustrating a correspondence relationship between a first storage area and a second storage area according to an embodiment of the present application;
FIG. 7 is a step diagram of a data processing method according to an embodiment of the present application;
fig. 8 is a block diagram of a computer-readable storage medium in an embodiment of the application.
The achievement of the objects, functional features and advantages of the present application will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of embodiments of the application and in the foregoing drawings, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules that are expressly listed or inherent to such process, method, article, or apparatus, but may include other steps or modules that may not be listed or inherent to such process, method, article, or apparatus, and may include only one logical division, and may be implemented by other means such as a plurality of modules may be combined or integrated into another system, or some features may be omitted or not implemented. In addition, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling between modules via interfaces, and the communication connection may be in electrical or other similar forms, which are not limited in this embodiment. The modules or sub-modules described as separate components may or may not be physically separate, may or may not be physical modules, or may be distributed in a plurality of circuit modules, and some or all of the modules may be selected according to actual needs to achieve the purposes of the embodiment of the present application.
The principles and spirit of the present application are explained in detail below with reference to several representative embodiments thereof.
Exemplary apparatus
The application proposes a data processing apparatus, as shown in fig. 1, fig. 1 is a schematic view of an application scenario of the data processing apparatus in the embodiment of the application, where the data processing apparatus is applied to a host, for example, a computer, where the host is provided with a CPU and a memory module, the CPU is a processor with a processing function, the memory module is a memory with a read-write function, the control module may process an access request of an external device to the memory module in the host, for example, the control module may be a memory management unit (Memory Management Unit, MMU), the external device is communicatively connected to the host through a PCIe communication protocol, and the external device may be hardware deployed with an application program or means a device connected to a device other than the host, such as an input device (such as a keyboard, a mouse), an output device (such as a display, a printer), an external storage device (such as a hard disk, a usb), and the like.
With continued reference to FIG. 1, in an embodiment of the present application, the data processing apparatus includes a control module, a first address translation bypass buffer, and a plurality of second address translation bypass buffers;
The first address conversion bypass buffer is used for buffering a first mapping relation, and one first mapping relation comprises a corresponding relation between a source address corresponding to a DMA request and a physical address of a descriptor; each second address conversion bypass buffer is used for caching a second mapping relation, and each second mapping relation comprises a corresponding relation between a target virtual address and a target physical address corresponding to a type of DMA request, wherein a descriptor in a memory module comprises the target virtual address of the DMA request;
the control module is configured to determine, in response to receiving a DMA request, a descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer;
transmitting the DMA request to the memory control module based on the physical address of the descriptor corresponding to the DMA request;
receiving a descriptor corresponding to the DMA request, which is returned by the memory module;
determining a target physical address corresponding to the DMA request based on a target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request;
and processing the DMA request based on the target physical address.
In this embodiment of the present application, the data processing device is disposed on a host (such as a computer), and when the external device needs to access the memory module, the external device accesses the memory module through the data processing device.
In the embodiment of the application, the control module can receive DMA requests initiated by external equipment and forward the DMA requests to the memory module based on the received DMA requests, and the address translation bypass buffer (Translation Lookaside Buffer, TLB) can be a buffer for caching the mapping relation between the virtual address and the physical address, which is common in the prior art.
In the embodiment of the application, when the external device needs to access the memory module, the host generates a target virtual address for the DMA request corresponding to the access, where the target virtual address corresponds to a target physical address, and the target physical address is a physical address of target data to be read in the memory module or a physical address of a storage space to be written by the DMA request.
In the embodiment of the application, the corresponding relationship between the target virtual address and the target physical address is the second mapping relationship, and the second mapping relationship is cached in the second address translation bypass buffer. It should be noted that, the number of the second address translation bypass buffers is plural, and the DMA requests of the external device are of plural types, and in the embodiment of the present application, the same second address translation bypass buffer is only used to cache the second mapping relationship that is recently used or commonly used in the DMA requests of the same type.
As shown in fig. 2, in the embodiment of the present application, in order to ensure the security of data transmission, the memory module may be divided into a first memory area and a second memory area, where the first memory area is used to store a target virtual address corresponding to each DMA request, and the target virtual address corresponding to each DMA request is stored in the first memory area in a descriptor form, and the second memory area is used to store data that needs to be read by a read request in the DMA request, or is used to provide a memory space for writing data for a write request in each DMA request. When an external device initiates a DMA request, a target virtual address corresponding to the DMA request in a first storage area needs to be acquired first, and then a target physical address corresponding to the target virtual address is queried in a second address translation bypass buffer corresponding to the DMA request type.
In the embodiment of the application, when the external device sends the DMA requests, the control module generates a source address for each DMA request, the source address and the descriptor of the target virtual address corresponding to the DMA request are located, and the physical address in the memory module has a corresponding relationship, namely a first mapping relationship, and the first mapping relationship is cached in the first address conversion bypass buffer.
Referring to fig. 3, fig. 3 is a schematic diagram of a first mapping relationship according to an embodiment of the present application, which includes a correspondence between source addresses 1-n and descriptor physical addresses 1-n, for example, source address 1 corresponds to descriptor physical address 1 and source address 2 corresponds to descriptor physical address 2. When each external device initiates a DMA request, the control module generates a source address for the DMA request, where different DMA requests may correspond to the same source address, and each source address corresponds to a physical address of a descriptor in the first mapping relationship. As shown in fig. 4, fig. 4 is a schematic diagram of descriptors stored in physical addresses of each descriptor in the first mapping relationship shown in fig. 3, where each descriptor is stored in a first storage area of the storage module, and a plurality of descriptors may be stored in a storage space corresponding to one physical address of the descriptor.
In the embodiment of the application, when an external device initiates a DMA request, a control module determines a descriptor physical address corresponding to the source address based on a first mapping relation according to the source address of the DMA request, and further sends a read request to a memory module according to the descriptor physical address in the DMA request, the memory module reflows a descriptor corresponding to the DMA request to the control module based on the descriptor physical address in the DMA request, after receiving the reflowed descriptor, the control module acquires a target virtual address corresponding to the read request from the descriptor, and then, the control module queries a target physical address corresponding to the target virtual address based on a second address conversion bypass buffer corresponding to the DMA request type, so as to process the DMA request based on the target physical address, for example, write data to the target physical address or read data from the target physical address.
In the embodiment of the application, different second address conversion bypass buffers are arranged for the mapping relation between the target virtual addresses and the target physical addresses corresponding to different types of DMA requests according to the types of the DMA requests, and when the DMA requests are processed, the conversion of the target virtual addresses and the target physical addresses is carried out based on the corresponding second address conversion bypass buffers according to the types of the DMA requests.
As shown in fig. 2, in an embodiment of the present application, the data processing apparatus further includes a queue module, where the queue module includes a plurality of queue units, each queue unit is configured to cache DMA requests, and types of DMA requests in a same queue unit are the same, and DMA requests in a same queue unit correspond to a same source address.
In general, a plurality of external devices are mounted on a host, and the plurality of external devices operate in parallel, so as to increase the operation speed of each external device.
As shown in fig. 5, in an embodiment of the present application, the queue module includes a plurality of queue elements, each for buffering DMA requests of the same type.
For example, in the embodiment of the present application, DMA requests issued by respective external devices may be divided into:
a Magic request refers to a call request to a particular interface when using a Magic-API framework in a programming or development environment.
DIRECT WRITE request, which refers to a request to directly read and write data from the PGA (process global area) to a data file or temporary file without going through the SGA (system global area) when processing the data;
Infeed requests, which refers to requests to write data from an external device to a host;
outfeed requests, which refer to requests to read data from a host;
debug request refers to the process of debugging requests during software development, and is mainly used for tracking and locating problems in code running.
In this embodiment of the present application, the queue module may set five queue units for buffering the second mapping relationships corresponding to the five types of DMA requests, respectively.
In addition, since the frequencies of the DMA requests of different types are different, such as the DMA requests sent by the external device are mostly Infeed requests and Outfeed requests, secondly DIRECT WRITE requests and finally Magic requests and Debug requests, in the embodiment of the present application, the queue module may be further configured to configure a first number of queue units for Infeed requests, a second number of queue units for Outfeed requests, a third number of queue units for DIRECT WRITE requests, and a fourth number of queue units for Magic requests and Debug requests, where the first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number. That is, more queue elements are provided for more frequently issued DMA request types, and a fewer number of queue elements are provided for less frequently issued DMA request types.
In the embodiment of the application, the source addresses of the DMA requests in the same queue unit are the same, for example, a queue source address can be generated for each queue unit, the source address of the DMA request in the same queue unit is set as the queue source address corresponding to the queue unit, and when the DMA request in each queue unit is processed by the control module, the control module can search based on the first address translation bypass buffer according to the queue source address corresponding to the currently processed queue unit, and determine the physical address of the descriptor corresponding to the DMA request.
In addition, in the embodiment of the present application, a queue module is provided, and when the queue module is provided with a plurality of queue units, since source addresses of DMA requests in a same queue unit are queue source addresses, that is, a first mapping relationship is a correspondence between a queue source address and a physical address of a descriptor, a first mapping relationship cached by a first address translation bypass buffer is a mapping relationship between a queue source address and a physical address of a descriptor, at this time, a storage address of a descriptor in a first storage area in a memory module may be maintained by a host, so that a first mapping relationship cached by the first address translation bypass buffer may be kept unchanged. For example, the host may store the target virtual address generated for each DMA request in a corresponding descriptor, thereby keeping the first mapping relationship unchanged at all times.
In the embodiment of the present application, two second address translation bypass buffers are provided, and two second address translation bypass buffer tables are respectively used for buffering Infeed the corresponding second mapping relationships and Outfeed the corresponding second mapping relationships, and the corresponding second address translation bypass buffers are not set to the Magic request, the DIRECT WRITE request and the Debug request.
The DMA requests sent by the external device are usually Infeed requests and Outfeed requests, the Magic requests, DIRECT WRITE requests and Debug requests are fewer, and the space for setting the address translation bypass buffers is limited, i.e. if five address translation bypass buffers are set for caching the second mapping relationships corresponding to the five DMA request types, the space of the five address translation bypass buffers is limited, and for any DMA request type, the corresponding address translation bypass buffers can only cache a small number of common mapping relationships, and the success rate when searching for the translated virtual address and the physical address based on the two mapping relationships is lower.
Therefore, in the embodiment of the present application, for the second mapping relationships corresponding to the Magic request, DIRECT WRITE request and Debug request, the space for setting the address translation bypass buffer is not used for buffering, and all the space for buffering the second mapping relationship corresponding to the Infeed request and the second mapping relationship corresponding to the Outfeed request are used for buffering, so that the buffer space of the address translation bypass buffer corresponding to each Infeed, outfeed request can be increased, the address translation bypass buffer corresponding to Infeed request can buffer more of the second mapping relationships corresponding to Infeed request, and the address translation bypass buffer corresponding to Outfeed request can buffer more of the second mapping relationships corresponding to Outfeed request. Thus, for Infeed, outfeed requests that originate much more frequently than other types of DAM requests, the success rate in performing lookup translations based on their respective address translation bypass buffers is higher when the target virtual address and the target physical address are translated.
In the embodiment of the application, when the second mapping relation corresponding to the Magic request, the DIRECT WRITE request and the Debug request is cached without using an address translation bypass buffer, after the target virtual address is determined by receiving the descriptors corresponding to the Magic request, the DIRECT WRITE request and the Debug request, the control module does not need to search in the second address translation bypass buffer, and can search in a page table directly based on the target virtual address in the descriptors to determine the target physical address corresponding to each DMA request.
In an embodiment of the present application, the memory control module is further configured to determine a number of reflow descriptors to the control module based on a size of the target data requested by the DMA request.
When the control module requests the descriptors from the memory module based on the physical addresses of the descriptors corresponding to the DMA requests, the memory module can determine the size of the target data requested by the control module according to the DMA requests, the target data is stored in the memory module in the form of page frames, and the physical address of each page frame corresponds to the target virtual address in one descriptor, so that the memory module can determine the number of the descriptors corresponding to the DMA requests based on the size of the target data requested by the DMA requests, and then reflux the descriptors with the corresponding number to the control module.
For example, as shown in fig. 6, fig. 6 is a correspondence relationship between descriptors and page frames of a memory module in an embodiment of the application. Wherein the first storage area contains a plurality of descriptor physical addresses, fig. 6 is only exemplified by descriptor physical address 1, in which descriptors 1-7 are stored. In addition, the descriptor physical address 1 corresponds to the queue source address 1 and is stored in the first address translation bypass buffer. Assuming that the queue unit corresponding to the queue source address 1 is the queue unit a, when the control module receives the DMA request in the queue unit a, it can be determined based on the first address translation bypass buffer that the physical address of the descriptor corresponding to the queue source address 1 is the descriptor physical address 1, then the control module sends the DMA request to the memory module based on the descriptor physical address 1, the DMA request includes the size of the requested target data, assuming that the size of the target data is the size of three page frames, after the memory module receives the DMA request sent by the control module, it determines that the physical address of the descriptor requested by the DMA request is the descriptor physical address 1, then it is determined based on the DMA request that the initial target virtual address corresponds to the descriptor 3, then it is determined based on the three page frames according to the size of the target data, namely, three descriptors are needed, at this time, the descriptors 3, 4 and 5 can be returned to the control module, after the control module receives the descriptors 3, 4 and 5, it can determine three virtual addresses included in the descriptors 3, 4 and 5, namely, after the control module receives the three target virtual addresses corresponding to the three target virtual addresses, and then the control module writes the three virtual addresses into the control module corresponding to the control module a corresponding to the three page frames based on the second address 3, namely, the second virtual address corresponding to the target buffer, and the second virtual buffer based on the type 3 and the target buffer, and the second page frame corresponding to the target buffer.
In the embodiment of the application, different second address conversion bypass buffers are arranged according to the mapping relation between the target virtual addresses and the target physical addresses corresponding to different types of DMA requests as the types of the DMA requests, and when the DMA requests are processed, the conversion of the target virtual addresses and the target physical addresses is carried out based on the corresponding second address conversion bypass buffers according to the types of the DMA requests.
Exemplary method
As shown in fig. 7, the present application further proposes a data processing method, which is applied to the data processing apparatus in each embodiment of the above-mentioned exemplary apparatus, and the data processing method includes the following steps:
Step S100, receiving a DMA request, and determining a descriptor physical address corresponding to the DMA request based on a first address translation bypass buffer.
And step 200, based on the physical address of the descriptor corresponding to the DMA request, sending the DMA request to a memory module.
Step S300, receiving a descriptor corresponding to the DMA request, which is returned by the memory control module.
Step S400, determining a target physical address corresponding to the DMA request based on the target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request.
And S500, processing the DMA request based on the target physical address.
The specific implementation method of steps S100 to S500 refers to each embodiment of the data processing apparatus, and is not described herein in detail.
In an embodiment of the present application, the data processing method further includes:
Before receiving a DMA request and determining a physical address of a descriptor corresponding to the DMA request based on a first address translation bypass buffer, the method further comprises:
the method comprises the steps of pre-configuring a queue module, wherein the queue module comprises a plurality of queue units, configuring DMA requests of the same type in the same queue unit, and setting the same source address for the DMA requests in the same queue unit.
In the embodiment of the application, a plurality of descriptors are stored in a physical address of a storage descriptor corresponding to the same source address;
the number of reflow descriptors to the control module is determined based on the size of the target data requested by the DMA request sent to the memory module.
In an embodiment of the application, the DMA request comprises the following types of a Magic request, a DIRECT WRITE request, a Infeed request, a Outfeed request and a Debug request;
Before receiving the DMA request and determining the physical address of the descriptor corresponding to the DMA request based on the first address translation bypass buffer, the data processing method further comprises:
second address translation bypass buffers are set for the Infeed and Outfeed requests, respectively, to cache the respective second mappings for the Infeed and Outfeed requests, respectively, and there is no need to set second address translation bypass buffers for the Magic, DIRECT WRITE and Debug requests.
In an embodiment of the present application, the pre-configured queue module includes:
And configuring a first number of queue units for the Infeed requests, a second number of queue units for the Outfeed requests, a third number of queue units for the DIRECT WRITE requests, and a fourth number of queue units for both the Magic requests and the Debug requests, wherein the first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number.
In an embodiment of the present application, after receiving a descriptor corresponding to the DMA request and reflowed by the memory module, the method further includes:
When the descriptor corresponding to the Magic request or the DIRECT WRITE request or the Debug request is received, a page table is searched based on the target virtual address in the descriptor corresponding to each DMA request, so as to determine the target physical address corresponding to each DMA request.
The data processing method according to the embodiment of the present application is applied to the data processing device according to any of the above embodiments, and therefore, all the beneficial effects of the data processing device according to any of the above embodiments are included, and are not described in detail herein.
Exemplary Medium
Having described the method and apparatus of the exemplary embodiment of the present application, reference is next made to fig. 8 for describing a computer readable storage medium of the exemplary embodiment of the present application, and referring to fig. 8, the computer readable storage medium is shown as an optical disc 70, on which a computer program (i.e., a program product) is stored, where the computer program, when executed by a processor, implements the steps described in the above method embodiment, for example, receiving a DMA request, determining a descriptor physical address corresponding to the DMA request based on a first address translation bypass buffer, sending the DMA request to a memory module based on the descriptor physical address corresponding to the DMA request, receiving a descriptor corresponding to the DMA request returned by the memory module, determining a target physical address corresponding to the DMA request based on a target virtual address in the descriptor, and a second address translation buffer corresponding to the DMA request, and processing the DMA request based on the target physical address. The specific implementation of each step is not repeated here. It should be noted that examples of the computer readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical and magnetic storage media, which are not described herein in detail.
Exemplary chip
Having described the apparatus, method, and medium of the exemplary embodiments of the present application, the chips of the exemplary embodiments of the present application are described next.
The chip provided in the embodiment of the present application includes the data processing device described in any one of the above embodiments, so that the chip has all the beneficial effects of the data processing device described in the above embodiments, which are not described in detail herein.
It should be noted that the foregoing embodiments are merely illustrative embodiments of the present application, and not restrictive, and the scope of the application is not limited to the embodiments, and although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that any modification, variation or substitution of some of the technical features of the embodiments described in the foregoing embodiments may be easily contemplated within the scope of the present application, and the spirit and scope of the technical solutions of the embodiments do not depart from the spirit and scope of the embodiments of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Furthermore, although the operations of the methods of the present application are depicted in the drawings in a particular order, this is not required or suggested that these operations must be performed in this particular order or that all of the illustrated operations must be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform.
Claims (14)
1. A data processing apparatus includes a control module, a first address translation bypass buffer, and a plurality of second address translation bypass buffers;
the first address conversion bypass buffer is used for buffering a first mapping relation, and one first mapping relation comprises a corresponding relation between a source address corresponding to a DMA request and a physical address of a descriptor; each second address conversion bypass buffer is used for caching a second mapping relation, and each second mapping relation comprises a corresponding relation between a target virtual address and a target physical address corresponding to a type of DMA request, wherein descriptors in a memory module are used for storing the target virtual address of the DMA request;
the control module is configured to determine, in response to receiving a DMA request, a descriptor physical address corresponding to the DMA request based on the first address translation bypass buffer;
Transmitting the DMA request to the memory module based on the physical address of the descriptor corresponding to the DMA request;
receiving a descriptor corresponding to the DMA request, which is returned by the memory module;
determining a target physical address corresponding to the DMA request based on a target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request;
and processing the DMA request based on the target physical address.
2. The data processing apparatus according to claim 1, further comprising a queue module including a plurality of queue units, each queue unit being for buffering DMA requests, the DMA requests in a same queue unit being of a same type, the DMA requests in a same queue unit corresponding to a same source address.
3. The data processing apparatus according to claim 2, wherein the memory module is further configured to store a plurality of descriptors in a storage space for storing descriptors corresponding to a same source address;
the memory module is further configured to determine a number of reflow descriptors to the control module based on a size of target data requested by the DMA request.
4. The data processing apparatus according to claim 3, wherein the DMA request includes a type of a Magic request, a DIRECT WRITE request, a Infeed request, a Outfeed request, and a Debug request;
two second address translation bypass buffers are provided, and the two second address translation bypass buffers are respectively used for caching Infeed the corresponding second mapping relation requested by the request and Outfeed the corresponding second mapping relation requested by the request;
And the data processing device is not provided with a second address translation bypass buffer corresponding to the Magic request, the DIRECT WRITE request and the Debug request.
5. The data processing apparatus of claim 2, wherein the queue module is further configured to configure a first number of queue elements for Infeed requests, a second number of queue elements for Outfeed requests, a third number of queue elements for DIRECT WRITE requests, and a fourth number of queue elements for both Magic requests and Debug requests;
The first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number.
6. The data processing apparatus according to claim 4, wherein the control module is further configured to, when receiving the descriptor corresponding to the Magic request or the DIRECT WRITE request or the Debug request, look up a page table based on a target virtual address within the descriptor to determine a target physical address corresponding to each DMA request.
7. A method of data processing, the method comprising:
Receiving a DMA request, and determining a descriptor physical address corresponding to the DMA request based on a first address translation bypass buffer;
Transmitting the DMA request to a memory module based on the physical address of the descriptor corresponding to the DMA request;
receiving a descriptor corresponding to the DMA request, which is returned by the memory module;
determining a target physical address corresponding to the DMA request based on a target virtual address in the descriptor and a second address translation bypass buffer corresponding to the DMA request;
processing the DMA request based on the target physical address;
The first address conversion bypass buffer is used for caching a first mapping relation, the first mapping relation comprises source addresses of the DMA requests, corresponding relations of descriptors corresponding to the DMA requests and physical addresses in the memory module, each second address conversion bypass buffer is used for caching a second mapping relation, each second mapping relation comprises corresponding relations of a target virtual address corresponding to one type of DMA requests and a target physical address, and the descriptors in the memory module are used for storing the target virtual addresses of the DMA requests.
8. The data processing method of claim 7, wherein prior to receiving a DMA request, determining a physical address of a descriptor corresponding to the DMA request based on a first address translation bypass buffer, the method further comprises:
the method comprises the steps of pre-configuring a queue module, wherein the queue module comprises a plurality of queue units, configuring DMA requests of the same type in the same queue unit, and setting the same source address for the DMA requests in the same queue unit.
9. The data processing method as claimed in claim 7, wherein a plurality of descriptors are stored in a storage descriptor physical address corresponding to the same source address;
the number of reflow descriptors to the control module is determined based on the size of the target data requested by the DMA request sent to the memory module.
10. The data processing method as claimed in claim 8, wherein the DMA request includes a type of a Magic request, a DIRECT WRITE request, a Infeed request, a Outfeed request, and a Debug request;
Before receiving the DMA request and determining the physical address of the descriptor corresponding to the DMA request based on the first address translation bypass buffer, the data processing method further comprises:
second address translation bypass buffers are set for the Infeed and Outfeed requests, respectively, to cache the respective second mappings for the Infeed and Outfeed requests, respectively, and there is no need to set second address translation bypass buffers for the Magic, DIRECT WRITE and Debug requests.
11. The data processing method of claim 10, the pre-configured queue module comprising:
And configuring a first number of queue units for the Infeed requests, a second number of queue units for the Outfeed requests, a third number of queue units for the DIRECT WRITE requests, and a fourth number of queue units for both the Magic requests and the Debug requests, wherein the first number is greater than the second number, the second number is greater than the third number, and the third number is greater than the fourth number.
12. The data processing method of claim 10, after receiving the descriptor corresponding to the DMA request that is reflowed by the memory module, the method further comprising:
When the descriptor corresponding to the Magic request or the DIRECT WRITE request or the Debug request is received, a page table is searched based on the target virtual address in the descriptor corresponding to each DMA request, so as to determine the target physical address corresponding to each DMA request.
13. A computer readable storage medium comprising instructions which, when run on a computer, cause the computer to perform the data processing method of any of claims 7-12.
14. A chip comprising a data processing apparatus as claimed in any one of claims 1 to 6.
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