CN1194714A - Audio Storing and reproducing apparatus - Google Patents

Abstract

An audio storage/reproduction device comprising a semiconductor chip having a semiconductor memory having a plurality of storage areas; a storage specifying input terminal to be used to designate a storage area of a storage area to be stored and reproduced in the storage area a designation signal and a storage designation signal for designating storage of audio data are input thereto; a reproduction designation input terminal to which a reproduction designation signal for designating reproduction of audio data is input; The designation signal designates a storage area to be stored and reproduced and stores audio data in the designated storage area according to the storage designation signal, and reads the audio data stored in the designated storage area according to the reproduction designation signal. A controller includes a control circuit for sending a storage area designation signal to a storage designation input terminal when a storage designation switch is operated, and for sending a storage designation signal to a storage designation input terminal when a recording designation switch is operated and then sending a storage designation signal to a storage designation input terminal. The specified signal, and the regeneration specified signal is sent to the regeneration specified input terminal when the regeneration specified switch is operated.

Description

Audio storage and reproduction device

technical field

The present invention relates to an audio storage and reproduction device which stores audio data and reproduces the stored audio data.

Background technique

There is an audio storage and reproduction apparatus which encodes (A/D converts) an audio signal supplied from the outside, stores the resulting signal in a semiconductor memory such as a RAM, and reads it from the RAM by operating a reproduction switch or the like. The encoded signal is taken and the read signal is decoded (D/A converted) thereby providing an audio output as disclosed in US Patent No. 4,368,988.

With a conventional audio storage and reproduction device, when a single semiconductor memory is used as a single recording and reproduction device, addressing is performed from the first address in a recording or reproduction operation. However, if a single semiconductor memory is divided into blocks, and some blocks are selected for recording or reproduction, addressing must be performed from the start address of the selected block. To do this, it is necessary to transfer the data at the start address of the selected block to the address control section from the start address, preset it, and update the address. When encoded data is stored in volatile memory, such as RAM, the stored content is lost when the battery reaches end of life, is replaced, or if a power failure occurs. To avoid losing stored data, consider using non-volatile memory such as EEPROM. However, EEPROMs require very high drive voltages compared to, for example, CMOS circuits that operate on about 1V. For this reason, circuits operating at relatively low voltages for controlling recording and reproducing operations and circuits including nonvolatile memories have to be formed of separate chips, which need to be controlled by different voltages, respectively. As described above, when the main circuit part and the circuit including the nonvolatile memory are assembled from separate chips, and a single nonvolatile memory is divided into a plurality of blocks as described above, and some blocks are selected for recording and reproduction, direct addressing is necessary. The start address of each block, as a result, requires a plurality of terminals as input terminals of address data, which causes a problem that the chip size including the nonvolatile memory becomes large.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an audio storage and reproduction apparatus which divides memory into blocks and which can selectively store data into or reproduce data from blocks on a block basis without complicating the circuit configuration change.

Above-mentioned object is realized by providing following audio storage and reproducing device, and it comprises: a semiconductor chip, this chip comprises the semiconductor memory that has a plurality of memory areas; Among them, a storage area designation signal for designating a storage area to be stored or reproduced and a storage designation signal for designating storage of audio data are input thereto; a reproduction designation input terminal, to which a reproduction designation signal for designating reproduction of audio data is input and a storage medium control device, not only used for designating a storage area to be stored or reproduced according to a storage area designation signal and storing audio data in the designated storage area according to the storage designation signal, but also reading and storing the audio data in the designated storage area according to the reproduction designation signal. Audio data of the storage area; and control means, which includes storage area designation switch means, recording designation switch means, reproduction designation switch means and control circuit, when the storage area designation switch means is operated, the control circuit sends the storage area designation signal to the storage designation The control circuit sends a storage area designation signal to the storage designation input terminal when the record designation switch means is operated, and then sends a record designation signal to the reproduction designation input terminal when the reproduction designation switch means is operated.

Since the storage designation input terminal for inputting the storage area designation signal and the storage designation signal and the reproduction designation input terminal for inputting the reproduction designation signal connect the semiconductor chip with the control circuit, the audio storage and reproduction device of the present invention has the following advantages: the semiconductor memory can be divided into blocks and can select blocks to be recorded and reproduced block by block without complicating the circuit configuration or increasing the number of terminals of the semiconductor chip.

Brief description of the drawings

1 is a block diagram of a portable electronic device according to an embodiment of the present invention;

Fig. 2 is the conceptual diagram of the data structure of RAM9 among Fig. 1;

Fig. 3 is a circuit diagram of the control part 20 in Fig. 1;

Fig. 4 is a conceptual diagram explaining the relationship between the recording control signal S1 (256 Hz) and the clock  (32 Hz) in Fig. 3;

Fig. 5 is a flowchart explaining the main operation;

Fig. 6 is an operational flowchart for explaining key processing in Fig. 5;

Fig. 7 is a flow chart explaining the operation of key processing in Fig. 5;

Fig. 8 is a reproduction mode display diagram on the LCD display 14 in Fig. 1; and

FIG. 9 is a diagram showing a playback mode displayed on the LCD display 14 in FIG. 1. Referring to FIG.

Best Mode for Carrying Out the Invention

Hereinafter, an electronic watch, a portable electronic device according to an embodiment of the present invention will be explained with reference to the accompanying drawings.

A. The configuration of the embodiment

Fig. 1 is a block diagram of an electronic wristwatch according to an embodiment of the present invention. In the figure, the electronic watch of this embodiment has the function of a watch, a calculation function, a database function of storing many data items of names and telephone numbers and others and displaying them, and a memo function of recording a voice supplied from the outside in a memory and reproducing it. . The electronic watch includes a chip control integrated circuit 1 and a chip memory control integrated circuit 2. The control integrated circuit 1 is composed of, for example, a C-MOS device and a control device for controlling recording and reproducing voices. The C-MOS device includes a watch function , a processing circuit for computing functions and database functions; and the memory control integrated circuit 2 includes a non-volatile memory, such as a transient EEPROM for storing audio data and a control device for controlling the non-volatile memory and address. The control integrated circuit 1 and the memory control integrated circuit 2 work under different driving voltages, but both obtain the power supply from the same battery. They are designed to generate the voltage required in the power supply circuit in each integrated circuit.

First, the control integrated circuit 1 and its peripheral circuits are explained. The key input section 3 includes numeric keys and character keys (not shown) for inputting various data, a recording key 3a for recording audio data, a playback key 3b for reproducing recorded audio data, and a selection key 3c, and the selection The key is used to select a block in which data is stored or reproduced from among memory blocks (eight) of the EEPROM 25 to be explained later. Each key input signal from the key input section 3 is sent to the control section 7, which then detects the key input.

The oscillation circuit 4 generates a reference clock of a specific frequency and supplies it to the frequency division circuit 5 . The frequency division circuit 5 generates and outputs a system clock and various timing clocks in accordance with the reference clock to operate the time keeping circuit 6, the control section 7 and each of the other sections. On the basis of the one-second signal from the timing clock of the frequency division circuit 5, that is, the reference signal for keeping the time, the time keeping circuit 6 counts the current time (date, day of the week, hour, minute, second), and It is supplied to the control section 7 .

The control section 7 is a CPU (Central Processing Unit) which realizes the above-mentioned various functions of the electronic watch by executing specific microprograms stored in the ROM 8 to be explained later. In this embodiment, in particular, the control section records audio data into blocks obtained by dividing the EEPROM 25 to be explained later and reproduces audio data therefrom through processing to be explained later. Specifically, the control section 7 causes the blocks to be recorded and reproduced to be cyclically shifted by one block each time the selection key 3c is pressed, thereby causing a desired block to be selected. When the record key 3a is pressed, the control section causes audio data on voice input from the microphone 5 to be stored in a selected block in the EEPROM. The control section reproduces the audio data stored in the selected block in the EEPROM 25 when the reproduction key 3b is pressed. When the recording key 3a and reproduction key 3b are simultaneously pressed, the control section causes various flags and date and time data items stored in the RAM 9 to be explained below to be deleted.

ROM 8 stores microprograms executed by control section 7 and various initial parameters. The RAM 9 is used as a register and a work area for storing various data items generated as a result of executing programs by the control section 7 .

FIG. 2 is a conceptual diagram of the data structure of RAM9. In FIG. 2, the display register is a register for storing data for displaying various data items on an LCD display (liquid crystal display) to be explained below. The register M is a register for specifying a specified recording/reproducing block in which audio data is to be stored among the eight blocks of the EEPROM 25 .

Flag P is a flag indicating that voice is being recorded. When the flag is at "1", voice input from the microphone 5 to be explained below is accepted by the encoding section (encoding circuit) 6 and stored in the EEPROM 25 as audio data. Flag L is a flag indicating that voice is being reproduced. When this flag is at "1", the audio data read out from the EEPROM 25 is output to the speaker 11 explained below via the decoding section (decoding circuit) 10 explained below.

Each register R0, R1, . . . , R7 has an area (register T) for storing the date and time at which audio data was recorded and a flag F indicating whether or not it has been recorded to the block. These registers R0, R1, . . . R7 are provided for blocks (eight in the embodiment) in the EEPROM 25, respectively. The flag F is "0" when no audio data is recorded. The flag F is "1" when audio data is recorded. In this embodiment, since the EEPROM 25 has been divided into 8 blocks as described above, the register M specifies the block to be stored and reproduced with 3-bit block specifying data.

In FIG. 1, a driver 13 displays various data items on an LCD (liquid crystal) display 14 supplied from the control section 7 regarding time, calculation data, name and telephone number data, and audio data stored in the EEPROM 25. The LCD display 14 includes a dot matrix or segment electrodes. In clock mode, the LCD display shows the date, current time and which block has been recorded. During recording or reproduction of audio data, the LCD display displays at least the current time, the block being recorded and the recording time, as shown in the display examples to be explained below.

In accordance with the operations of the recording key 3a, reproduction key 3b and selection key 3c, the control section 7 sets or resets the flip-flops F1 and F2 in the following three ways.

(1) When the selection key 3c is pressed each time, the control part sets the set terminal of the flip-flop F1 to "1", and then sets its reset terminal to "1", thereby sending a signal from the output terminal Q of the flip-flop F1. 1/256 cycle (256Hz) pulse. In the control section 20 of the memory control IC 2, this pulse is supplied to the block control section 21 as a block specifying signal BL for specifying a block in the EEPROM 25.

(2) When the record key 3a is pressed, first set and reset the flip-flop F1 seven times in 1/256 cycle (256Hz), and then the control part sets the set end to "1" to force the output end Q to be " 1". When the record key 3a is released, the control section sets the reset terminal of the flip-flop F1 to "1" to force the output terminal Q to "0".

(3) When the regeneration key 3b is pressed, the trigger F2 is first set and reset seven times in 1/256 cycle (256Hz), and then the control part sets the set end to "1" to force the output end Q to be " 1". When the regeneration key 3b is released, the control section sets the reset terminal of the flip-flop F2 to "1" to force the output terminal Q to "0".

Each flip-flop F1 and F2 supplies an output Q to the control section 20 of the memory control integrated circuit 2, the output level of which is turned on and off under the control of the control section 7. The power supply section 15 converts the supply voltage from the common battery BT into a driving voltage for operating the control integrated circuit 1, and supplies the driving voltage to each of the above-mentioned sections.

Next, the memory control integrated circuit 2 and its peripheral circuits will be explained. On the basis of the output Q supplied from the flip-flop F1 in the control integrated circuit 1 and the output Q supplied from the flip-flop F2, the control section 20 generates a block signal for specifying a block in the EEPROM 25, a recording signal indicating recording, a recording signal indicating The reproduced reproduced signal and the erase signal for erasing the recorded audio data, and the block signal and the erase signal are supplied to the block control section 21, and the recording signal, the reproduce signal, and the erase signal are supplied to the address control section 22.

FIG. 3 is a circuit diagram of the control section 20 . In the figure, the "OR" circuit 20a generates a block signal BL which becomes "1" when the output Q of the flip-flop F1 or the output Q of the flip-flop F2 is "1" and supplies the block signal BL to the block Control part 21. Specifically, when the flip-flop F1 or the flip-flop F2 supplies one pulse to the OR circuit, the OR circuit supplies one pulse block signal to the block control section 21 . The AND circuit 20b generates a clear signal CL which becomes "1" and supplies the clear signal to the address control section 22 when both the output Q of the flip-flop F1 and the output Q of the flip-flop F2 become "1". The clear signal CL is inverted by a NOT circuit 20c, and the inverted signal is supplied to AND circuits 20d and 20h.

The AND circuit 20d supplies the output Q of the flip-flop F1 to the 3-bit shift register 20e when the clear signal CL is "0" and the clock ? (1/32 second cycle: 32 Hz) is "1". Every time the AND circuit 20d supplies the recording control signal S1, the 3-bit shift register 20e sequentially shifts the stored bits and supplies one bit to the set terminal S of the flip-flop F3. As a result, when the fourth clock of the clock  is supplied to the AND circuit 20d, the 3-bit shift register 20e sets the flip-flop F3. In other words, flip-flop F3 is not set until the fourth clock of clock  has been supplied to flip-flop F3.

When a clock is supplied from the 3-bit shift register 20e to the flip-flop F3, the flip-flop F3 is set (Q=1). Since the reset signal is supplied to the flip-flop F3 via the NOT circuit 20f when the output Q of the flip-flop F1 becomes "0", the flip-flop F3 is reset (Q=0).

Since the clock  is determined to be 32Hz, even if the flip-flop F1 in Figure 1 supplies the clock with a period of 1/256 to the flip-flop F3, the flip-flop F3 will not be set immediately (Q=1), only between 2/32 to It is not set until 3/32 seconds later (Q=1).

An output Q of the flip-flop F3 is supplied to one input terminal of an AND circuit 20g. When the outputs of flip-flops F1 and F3 are both "1", that is, at a time 2/32 seconds to 3/32 seconds later than the time when flip-flop F1 is first supplied with a clock having a period of 1/256 to reset the flip-flop During the time F1, the AND circuit 20g produces an output "1" by ANDing the output Q of the flip-flop F1 and the output Q of the flip-flop F3. The AND circuit supplies an output of "1" to the address control section 22 in FIG. 1 as a recording control signal S1.

As described above, when the record key 3a is pressed, the control section 7 sets the flip-flop F1 to turn on the record mode. In this embodiment, since a block is previously selected using the same flip-flop F1 and then recording is specified, the block signal BL is supplied to the block control section 21 via the OR circuit 20a when the recording mode is turned on, and the selected block is changed. To avoid this, in the present embodiment, between 2/32 and 3/32 seconds after the record key 3a is pressed, by repeatedly setting and resetting the flip-flop F1 for a certain number of times (the number of blocks) in a 1/256 cycle -1: 7 times in this embodiment), the block set in the block control section 21 is made to be the block immediately before the selected block. Flip-flop F1 is thereafter set.

As a result, setting the flip-flop F1 to turn on the recording mode causes the recording control signal S1 for turning on the recording mode to be supplied to the control section 20, and causes the block in the block control section 21 to be incremented by 1, which in turn causes the preselected block to be set up. In this embodiment, since the flip-flop F1 is set and reset in 1/256 cycle, and the record control signal S1 is sent at the fourth clock of the clock  of 1/32 cycle (32Hz), so as long as the set and reset are repeated Resetting the flip-flop F1 does not send the recording control signal S1. Therefore, blocks and records can be specified using a single line.

Next, when the clear signal CL is "0" and the clock φ (1/32 cycle: 32 Hz) is "1", the AND circuit 20h supplies the output Q of the flip-flop F2 to the 3-bit shift register 20i. The 3-bit shift register 20i sequentially shifts the stored bits every time the AND circuit 20h supplies the regeneration control signal S2, and supplies them to the set terminal S of the flip-flop F4. As a result, the 3-bit shift register 20i sets the flip-flop F4 when the fourth clock of the clock  as shown in FIG. 4 has been supplied to the AND circuit 20h. In other words, flip-flop F4 is not set until the fourth clock of clock  has been supplied to AND circuit 20h.

A clock is supplied from the 3-bit shift register 20i to the flip-flop F4, and the flip-flop F4 is set (Q=1). When the output of the flip-flop F2 becomes "0", a reset signal is supplied to the flip-flop F4 via the NOT circuit 20j, thereby resetting the flip-flop F4 (Q=0). Since the flip-flop F4 uses a 32Hz clock , even if it is supplied with a clock with a period of 1/256 from the flip-flop F2 shown in Figure 1, it will not be set immediately (Q=1), but will be set at 2/32 It is set (Q=1) after 3/32 seconds.

An output Q of the flip-flop F4 is supplied to one input terminal of an AND circuit 20k. When the output Q of the flip-flop F2 and the output Q of the flip-flop F4 are both "1", that is, at 2/32 second to 3/32 second later than the time when the clock having a period of 1/256 is first supplied to the flip-flop F2 Between the time when the flip-flop F2 is reset, the AND circuit 20k ANDs the output Q of the flip-flop F2 with the output Q of the flip-flop F4, thereby generating an output of "1". The AND circuit 20k supplies an output of "1" as a reproduction control signal S2 to the address control section 22, as shown in FIG.

As described above, when the regeneration key 3b is pressed, the control section 7 sets the flip-flop F2 to start the regeneration mode. In this embodiment, since a block is previously selected using the same flip-flop F2, and then reproduction is designated, the block signal BL is supplied to the block control section 21 via the OR circuit 20a when the reproduction mode is turned on, and the thus selected block is changed. To avoid this, in this embodiment, as in the record mode, between 2/32 second and 3/32 second after pressing the record key 3b, by repeatedly setting and resetting the flip-flop F2 in a 1/256 cycle For a certain number of times (the number of blocks - 1: 7 times in the embodiment), the block set in the block control section 21 is made to be the block immediately before the selected block. Flip-flop F2 is thereafter set.

As a result, as in the recording mode, setting the flip-flop F2 to turn on the recording mode causes the reproduction control signal S2 for turning on the reproduction mode to be supplied to the control section 20, and causes the block in the block control section 21 to be incremented by 1, which This in turn causes the preselected block to be set again. Also in this case, since the flip-flop F2 is set and reset in 1/256 cycle, and the regeneration control signal S2 is sent at the 4th clock having a clock  of 1/32 cycle (32Hz), as long as the flip-flop F2 is repeatedly set bit and reset flip-flop F2, the regeneration control signal S2 is not sent. Therefore, a single line is sufficient for regeneration.

In FIG. 1, the block control section 21 is a 3-bit register which counts the block signal BL supplied from the control section 20, and supplies the resulting signal to the address control section 22 as block specifying data (3 bits) BD, to represent a block to be recorded into or reproduced from. The address control section 22 performs addressing and access in accordance with the recording control signal S1 , reproduction control signal S2 , clear signal CL and block designation data BD supplied from the control section 20 . The microphone 23 collects a user's voice and supplies an audio signal to the encoding section 24 . The encoding section 24 includes amplifiers, filters, and A/D conversion circuits (not all shown), converts audio signals into digital signals (audio data), and supplies the converted signals to the EEPROM 25 . The decoding section 26 converts the audio data supplied from the storage area of the block in the EEPROM 25 accessed by the address control section 22 into an analog signal, and then outputs it from the speaker 27 as voice.

EEPROM 25 is mainly composed of about 2 megabits of flash memory, which has 8 blocks 25a to 25h. The audio data received via the microphone 23 and the encoding section 24 are stored in specific blocks in the order of access by the address control section 22 . The oscillating circuit 28 generates a clock , which is a specific clock for operating the EEPROM 25 and others, and supplies the clock to various parts, including the control part 20 , the address control part 22 and the EEPROM 25 . The power supply section 29 converts the voltage supplied from the common battery BT into a driving voltage for operating the memory control integrated circuit 2, and supplies the driving voltage to the respective sections.

B, the operation of the embodiment

Next, the operation of the electronic wristwatch of this embodiment will be explained. The clock function, calculation function and database function are all the same as those of the traditional electronic watch, so no further explanation will be given. Next, the operation of recording audio data to and reproducing audio data from the EEPROM 25 will be explained.

(1) Main process

Fig. 5 is a flowchart explaining the main operation of the embodiment.

Steps S10 to S24 explained below are steps of determining a key input at the key input section 3, jumping to a step to be performed with or without key input, and displaying various data items on the LCD display 14. In step S10, it is judged whether any key has been pressed in the key input section 3 or not. If any key is pressed, control will go to step S12. In step S12, key processing to be explained later will be performed in accordance with the pressed key (record key 3a, reproduction key 3b, selection key 3c, or other key). If the key has not been pressed, control will go to step S14 where it is determined whether the key has not been pressed within a specified time limit. If the key is not pressed within this specified time limit, the recording flag P and the regeneration flag L will be cleared in step S16, and flip-flops F1 and F2 will be reset. In this embodiment, recording or reproduction is performed when the record key 3a is pressed or the reproduction key 3b is pressed. Recording or reproduction is terminated when the record key 3a or reproduction key 3b is released. Step S16 or S18 is a process of terminating recording or reproduction when the record key 3a or reproduction key 3b is released.

When the key processing of step S12 is finished, or if any key is pressed within the specified time limit in step S14 or if step S18 terminates, then control will proceed to step S20, where it will be judged whether the regeneration flag L is "1". When the regeneration flag L is "1", that is, in the regeneration mode, the control will go to step S22, where the recording date and time, the block where the data has been stored and the selected (designated) block will be displayed on the LCD display . Specifically, in the reproduction mode, as shown in FIG. 8, the LCD display displays numbers 1 to 8 representing blocks in the EEPROM 25 at the top and rectangular symbols representing blocks storing audio data below the respective numbers. In FIG. 8, illuminated rectangular symbols (the first, second and eighth blocks in the figure) indicate blocks in which data has been stored. A blinking rectangle symbol (the fourth block in the figure) indicates a selected block that has stored data and is being reproduced. Also, the LCD display shows the date (3-10) and time (18:10) stored in the register R3 in the RAM9, which represents the recording date and time of the voice stored in the fourth block.

When the regeneration flag L is "0", that is, when the mode is not the regeneration mode, the control will go to step S24, where the current date and time, the block of stored data and the selected block will be displayed on the LCD display. Specifically, as shown in Figure 9, on the LCD display, the illuminated rectangular symbols (the second, fourth, and eighth blocks in the figure) represent blocks of stored data, while the blinking rectangular symbols (the first block in the figure) Indicates the block into which data is being recorded. And the LCD display also shows the day (Sunday), date (3-17) and time (10:5825) in a week, namely the current time obtained by the time holding circuit 6.

(2) Key processing process

Next, the above-mentioned key processing procedure will be explained. 6 and 7 are flowcharts explaining the operation of key processing.

2-1. Block selection process

Steps S30 to S36 explained below are a process of determining a block into which audio data is to be recorded or from which audio data is to be reproduced. First, in step S30, it is determined whether or not the selection key 3c has been pressed. If the selection key 3c has been pressed, control will go to step S32, where it will be determined whether the recording flag P and the reproduction flag L are "0". If the recording flag P and the reproduction flag L are all "0", that is, neither the recording mode nor the reproduction mode, the control will go to step S34, where the flip-flop F1 will be set and reset, so that the flip-flop F1 can send A pulse with a period of 1/256 (256Hz). This causes the output of the OR circuit 20a shown in FIG. 3 to become "1", forcing the count in the block control section 21 to increase by one. Next, at step S36, the recording/reproducing block designation data in the register M of the RAM 9 is incremented by one. Then, key processing is terminated.

As above, the block is incremented by position by 1 each time flip-flop F1 is set and reset. Each time the selection key 3c is pressed, the blocks are cyclically moved in the following order: 1→2→3→...→6→7→8→1→2→.... At this time, since the reproduction flag L is "0", when the control returns to the main routine shown in Fig. 5, the display shown in Fig. 8 will appear at step S24. The user selects the desired block by pressing the selection key 3c until reaching the desired block. When either the recording flag P or the reproduction flag L is "1", that is, when in the recording mode or the reproduction mode, the judgment result at S32 is "No", so even if the selection key 3c is pressed, the designated block will not Change.

2-2. Recording mode

Steps S40 to S52 explained below are a recording process: the address control section 22 stores audio data input from the microphone 23 and converted in the encoding circuit 24 into a block designated by the block designation data BD. In step S30, when the selection key 3c has not been pressed, control goes to step S40, where it is determined whether the record key 3a has been pressed. If the record key 3a has been pressed, control will go to step S42, where it will be judged whether the reproduction flag L is "1". If the playback flag L is "1", it means that the playback key 3b is also pressed when the record key 3a is pressed. If the reproduction flag L is "0", this means that the recording mode for storing audio data in the EEPROM 25 has been selected.

When the reproduction flag L is "0" at step S42, this means that the reproduction key 3b has not been pressed, so control goes to step S44, where it is determined whether the recording flag P is "0". If the record flag is "0", this means that the record key has been pressed, so control will go to step S46.

In step S46, the set and reset flip-flop F1 is repeated seven times within 1/256 cycle (256 Hz). The reason for this is to prevent changes in the set flip-flop F1 for recording that have been selected in the block selection process described above. Since in the present embodiment, the EEPROM 25 is divided into eight blocks, the block specifying data BD in the block control section 21 is set to just at In the block before the selected block. Next, in step S48, the flip-flop F1 is set. This makes the block in which audio data is to be recorded the selected block. Next, in step S50, the current date and time in the time holding circuit 6 are stored in the date and time area (register T) of the corresponding block in the RAM9. At the same time, the corresponding flag F is set to "1". Then, the recording flag P is set to "1", and the current program is terminated. Forcing the record flag to "1" when the record key 3a is pressed makes the judgment result of step S44 "No", so that steps S46 to S52 are performed only once when the record key 3a is pressed.

As a result, in the memory control integrated circuit 2 , the recording control signal S1 is supplied from the control section 20 to the address control section 22 . Also, the 3-bit block designation data BD set in the block control section 21 is supplied to the address control section 22 in the block selection process. This enables the address control section 22 to store the audio data input from the microphone 23 and converted in the encoding circuit 24 into the block specified by the block specifying data BD. At this time, since the reproduction flag L is "0", when the control returns to the main routine shown in Fig. 5, the display image of Fig. 9 will appear in step S24.

Audio data is continuously stored in the EEPROM 5 while the record key 3a is pressed. When the record key 3a is released, the record flag P (=0) is cleared in step S16 of FIG. 5, and then the flip-flop F1 is reset in step S18, which resets the flip-flop F3 in FIG. 3 and terminates recording audio data.

2-3. Regeneration mode

Steps S62 to S72 explained below are reproduction processes that cause the decoding circuit 26 to convert the audio data stored in the block in the EbPROM 25 designated by the block designation data in the address control section 22 into an analog signal when the reproduction key 3a is pressed. , and the voice is output from the speaker 27 as an audio signal. When the selection key 3c or the recording key 3a are not pressed, control will pass through steps S30 and S40 to step S62 in FIG. 7, where it is determined whether the reproduction key 3b has been pressed. If the reproduction key 3b is pressed, control will go to step S64, where it will be judged whether the recording flag P is "1". If the record flag is "1", it means that the record key 3a was also pressed while the reproduction key 3b was pressed. If the recording flag P is "0", it means that the reproduction mode for reproducing the audio data stored in the EEPROM 25 has been selected.

When the record flag P is "0" at step S64, the record key 3a is not pressed. Then, control goes to step S66. In step S66, it is determined whether the reproduction flag L is "0". If the regeneration flag L is "0", this means that the regeneration key 3b has been pressed, and control will go to step S68.

In step S68, the set and reset flip-flop F2 is repeated seven times within 1/256 cycle (256 Hz). The reason for this is to prevent the block which has been selected in the above-mentioned block selection process from changing during the above-mentioned process of setting the flip-flop F2 and sending the regeneration control signal S2. The block specifying data BD in the block control section 21 is set in the block immediately before the selected block by repeating setting and resetting the flip-flop F2 up to 7 times in advance within 1/256 cycle (256 Hz). Next, in step S70, the flip-flop F2 is set. This makes the block in which audio data is to be recorded the selected block. Next, in step S72, the reproduction flag L is set to "1", and the current process is terminated. Forcing the reproduction flag to "1" at the time of pressing the reproduction key 3b makes the judgment result of step S66 "No", so that steps S46 to S52 are performed only once when the record key 3b is pressed.

As a result, in the memory control integrated circuit 2, the reproduction control signal S2 is supplied from the control section 20 to the address control section 22. Also, the 3-bit block designation data BD set in the block control section 21 is supplied to the address control section 22 in the block selection process. This enables the decoding circuit 26 to convert the audio data stored in the block designated by the block designation data BD in the address control section 22 into an analog signal, which is then output from the speaker 27 . At this time, since the reproduction flag L is "1", when the control returns to the main routine shown in Fig. 5, the display image of Fig. 8 appears in step S22.

While the reproduction key 3b is pressed, the audio data continues to be reproduced. When the record key 3b is released, the reproduction flag L is cleared (=0) at step S16 of FIG. 5, and thereafter the flip-flop F2 is reset at step S18, which terminates the reproduction of audio data.

2-4. Clearing process

Steps S44 to S50 explained below are a clearing process that deletes various marks and data items when the record key 3a and the reproduction key 3b are pressed simultaneously. In the case where the reproduction flag L has been set to "1" (step S42) when the record key 3a is pressed, or in the case where the record flag P has been set to "1" when the reproduction key 3b is pressed (step S64), execution Step 80 and subsequent cleaning processes are shown in FIG. 6 . In other words, the reproduction key 3b is pressed while the record key 3a is pressed, or the record key 3a is pressed while the reproduction key 3b is pressed, which means that the record key 3a and the reproduction key 3b are pressed together, thus performing the clearing process.

At step 80 , flip-flop F1 is set, and at step 82 flip-flop F2 is set. When both the flip-flops F1 and F2 are set, the output of the AND circuit 20b in the control circuit 20 in FIG. This causes audio data in specific chunks to be cleared at the same time. Next at step S84, the flip-flops F1 and F2 are reset. In step S86, the recording/reproducing block specifying data M, recording flag P, reproduction flag L, date and time, and flag F stored in the RAM 9 are cleared. Then, terminate the current program.

Although in the present embodiment, the block control signal BL is input to the control section 20 via the port T1 to which the recording designation signal is input, the block control signal may be input to the control section 20 via the port T2 to which the reproduction designation signal is input.

Although in this embodiment, it is only an example of applying the present invention to a portable electronic watch, the present invention can also be applied to various parts of electronic equipment other than an electronic watch. For example, the present invention can be applied to information devices such as portable phones, pagers, or electronic notebooks, or to various non-portable desktop electronic devices. The memory storing audio data is not limited to flash EEPROM. Other types of volatile or non-volatile memory may be used.

Claims (28)

1. An audio storage and reproduction device comprising: A semiconductor chip, the chip includes: A semiconductor memory having a plurality of storage areas for storing audio data; a storage designation input terminal to which a storage designation signal for designating a storage region to be stored and reproduced among a plurality of storage regions of said semiconductor memory and a storage designation signal for designating storage of audio data are input thereto; a reproduction designation input terminal to which a reproduction designation signal for designating reproduction of audio data is input; and storage medium control means for not only designating a storage area to be stored and reproduced among a plurality of storage areas of said semiconductor memory in accordance with said storage area designation signal and storing audio data in a storage area designated by said storage designation signal storage area, and read audio data stored in the storage area designated by the reproduction designation signal; and A control device comprising: storage area designation switchgear; record the designated switchgear; regenerative designated switchgear; and a control circuit that transmits a storage area designation signal to storage medium control means in the semiconductor chip via the storage designation input terminal when operating the storage designation switch means, and sends the A storage area specifying signal is sent to the storage medium control means in the semiconductor chip via the storage specifying input terminal and then the storage specifying signal is sent, and when the regeneration specifying switch means is operated, the reproduction specifying signal is passed through the The reproduction designation input terminal is sent to the storage medium control device in the semiconductor chip. 2. The audio storage and reproduction apparatus according to claim 1, wherein said control circuit sends a pulse signal as said storage area specifying signal, and said storage medium control means is to perform storage and reproduction every time said pulse signal is supplied The memory area moves one position. 3. The audio storage and reproduction apparatus according to claim 1, wherein said control circuit sends (the number of storage areas - 1) pulse signals as the storage area correction signal within a certain period before specifying storage or reproduction of said audio data. 4. The audio storage and reproduction apparatus according to claim 3, wherein said storage medium control means at least "ANDs" a pulse signal having a cycle greater than (specific cycle x number of storage areas) with said pulse signal having a specific cycle , and distinguish the storage designation signal or the reproduction designation signal from the storage area designation signal or the storage area correction signal on the basis of the result of the logical multiplication. 5. The audio storage and reproduction apparatus according to claim 1, wherein said semiconductor memory comprises a nonvolatile memory. 6. The audio storage and reproduction apparatus according to claim 1, wherein said control circuit and said semiconductor chip operate at different voltages. 7. The audio storage and reproduction apparatus according to claim 1, wherein said control circuit is mounted on a semiconductor chip different from said semiconductor chip, and the two semiconductor chips are driven at different voltages. 8. An audio storage and reproduction device comprising: A semiconductor chip, the chip includes: A semiconductor memory having a plurality of storage areas for storing audio data; A storage designation input terminal is input to it with a storage designation signal used to designate storage of audio data; a reproduction designation input terminal to which a storage area designation signal for designating a storage area to be stored and reproduced among a plurality of storage areas of said semiconductor memory and a reproduction designation signal for designating reproduction audio data are input thereto; and storage medium control means for not only designating a storage area to be stored and reproduced among a plurality of storage areas of the semiconductor memory in accordance with the storage area designation signal and storing audio data in a specific memory in accordance with the storage designation signal area, and read audio data stored in a specific storage area in accordance with said reproduction designation signal; and control device, which includes: storage area designation switchgear; record the designated switchgear; regenerative designated switchgear; and a control circuit for sending a storage area designation signal to storage medium control means in the semiconductor chip via the reproduction designation input terminal when operating the storage area designation switch means, and via the recording designation switch means when operating the the storage designation input terminal sends the storage designation signal, and when the regeneration designation switch means is operated, the storage area designation signal is sent to the storage medium control means in the semiconductor chip via the regeneration designation input terminal, and thereafter The reproduction designation signal is transmitted. 9. The audio storage and reproduction apparatus according to claim 8, wherein said control circuit sends a pulse signal as said storage area specifying signal, and said storage medium control means moves one by one to store each time said pulse signal is supplied. and regenerated storage areas. 10. The audio storage and reproduction apparatus according to claim 8, wherein said control circuit transmits (the number of storage areas - 1) pulse signals as the storage area correction signal within a certain period before specifying storage or reproduction of said audio data. 11. The audio storage and reproduction apparatus according to claim 10, wherein said storage medium control means at least "ANDs" a pulse signal having a cycle greater than (specific cycle x number of storage areas) with said pulse signal having a specific cycle , and distinguish the storage designation signal or the reproduction designation signal from the storage area designation signal or the storage area correction signal on the basis of the result of the logical multiplication. 12. The audio storage and reproduction apparatus according to claim 8, wherein said semiconductor memory comprises a nonvolatile memory. 13. The audio storage and reproduction apparatus according to claim 8, wherein said control circuit and said semiconductor chip operate at different voltages. 14. The audio storage and reproduction apparatus according to claim 8, wherein said control circuit is mounted on a semiconductor chip different from said semiconductor chip, and the two semiconductor chips are driven at different voltages. 15. An audio storage and reproduction device comprising: A semiconductor chip including a semiconductor memory having a plurality of storage areas for storing audio data, and storage medium control means for not only storing audio data in specific storage areas in accordance with a storage designation signal designating storage of audio data And read audio data stored in a specific storage area according to a reproduction designation signal designating reproduction of audio data; and a control circuit which sends a storage area designation signal for designating storage or reproduction among said plurality of storage areas storage area, and then transmit the storage designation signal or the regeneration designation signal, wherein the semiconductor chip further includes a storage designation input terminal, and transmits the storage designation signal and the storage designation signal sent from the control circuit A signal is input to it, and a regeneration designation input terminal, the regeneration designation signal is input to it, and the storage designation input terminal and the regeneration designation input terminal are connected to the control circuit. 16. The audio storage and reproduction apparatus according to claim 15, wherein said control circuit sends a pulse signal as said storage area specifying signal, and said storage medium control means is to perform storage and reproduction each time said pulse signal is supplied. The buckets are moved one by one. 17. The audio storage and reproduction apparatus according to claim 15, wherein said control circuit sends (the number of storage areas - 1) pulse signals as the storage area correction signal within a certain period before designating storage or reproduction of said audio data. 18. The audio storage and reproduction apparatus according to claim 17, wherein said storage medium control means at least "ANDs" a pulse signal having a cycle greater than (specific cycle x number of storage areas) with said pulse signal having a specific cycle , and distinguish the storage specifying signal or the regeneration specifying signal from the storage area specifying signal or the storage area correction signal on the basis of the result of the logical multiplication. 19. The audio storage and reproduction apparatus according to claim 15, wherein said semiconductor memory comprises a nonvolatile memory. 20. The audio storage and reproduction apparatus according to claim 15, wherein said control circuit and said semiconductor chip operate at different voltages. 21. The audio storage and reproduction apparatus according to claim 15, wherein said control circuit is mounted on a semiconductor chip different from said semiconductor chip, and the two semiconductor chips are driven at different voltages. 22. An audio storage and reproduction device comprising: A semiconductor chip including a semiconductor memory having a plurality of storage areas for storing audio data, inputting a storage designation input terminal for designating a storage designation signal for storing audio data, inputting a reproduction designation signal for designating reproduction of audio data A designation input terminal, and storage medium control means for not only storing audio data in a specific storage area according to a storage designation signal input from said storage designation input terminal, but also according to a reproduction designation input from said reproduction designation input terminal signal reads audio data stored in a specific memory area; and a control circuit that not only designates storage and reproduction by sending the storage designation signal supplied to the storage designation input terminal or the reproduction designation signal supplied to the reproduction designation input terminal in the form of a pulse signal having a specific cycle. storage area for audio data, and transmits either the storage designation signal or the reproduction designation signal as a constant level signal. 23. The audio storage and reproducing apparatus according to claim 22, wherein said control circuit sends a pulse signal as said storage area specifying signal, and said storage medium control means moves one by one to be stored each time said pulse signal is supplied. and regenerated storage areas. 24. The audio storage and reproduction apparatus according to claim 22, wherein said control circuit sends (the number of storage areas - 1) pulse signals as the storage area correction signal within a certain period before specifying storage or reproduction of said audio data. 25. The audio storage and reproduction apparatus according to claim 24, wherein said storage medium control means at least "ANDs" a pulse signal having a cycle greater than (specific cycle x number of storage areas) with said pulse signal having a specific cycle , and distinguish the storage designation signal or the reproduction designation signal from the storage area designation signal or the storage area correction signal on the basis of the result of the logical multiplication. 26. The audio storage and reproduction apparatus according to claim 22, wherein said semiconductor memory comprises a nonvolatile memory. 27. The audio storage and reproduction apparatus according to claim 22, wherein said control circuit and said semiconductor chip operate on different voltages. 28. The audio storage and reproduction apparatus according to claim 22, wherein said control circuit is mounted on a semiconductor chip different from said semiconductor chip, and the two semiconductor chips are driven at different voltages.

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