CN119471067A - Baud rate detection method, baud rate detection device and serial port communication system - Google Patents
Baud rate detection method, baud rate detection device and serial port communication system Download PDFInfo
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Abstract
The invention provides a baud rate detection method, a baud rate detection device and a serial port communication system, which can automatically detect edges, capture pulse widths and judge signal waveforms of serial port communication signals, and continuously calculate the baud rate by adopting at least 1 low-level pulse width and at least 1 high-level pulse width, so that slope errors can be eliminated. Further, the target frame header data can be automatically analyzed to obtain the pulse number threshold value and the ratio of the low-level pulse width to the high-level pulse width, so that the operation is simplified, and the efficiency is improved.
Description
Technical Field
The present invention relates to the field of serial port communications technologies, and in particular, to a baud rate detection method, a baud rate detection device, and a serial port communications system.
Background
In the fields of industrial measurement, automatic control, communication, system test and the like, people often use a serial communication (also called serial communication) mode to complete data transmission between two communication parties (such as a host and a terminal or two equipment systems) and the like.
When two communication parties communicate through serial ports, especially asynchronous serial communication, the two communication parties have to agree on and follow the same baud rate due to no synchronous clock, so that the correct transmission and reception of data, instructions and the like can be realized. The baud rate refers to the data bit transmission rate in the serial communication process, and refers to the number of transmission bits per second (bit/s). The asynchronous serial communication protocol is, for example, universal asynchronous receiver/Transmitter UART (Universal Asynchronous Receiver/Transmitter) or the like.
In the case where both parties agree on the baud rate, the receiving party can normally parse the data without any error as long as the duration of each bit transmitted by the transmitting party (i.e., the inverse of the baud rate) is accurate. However, in practical application, there may be a problem that the baud rate is deviated and matched due to clock precision errors, data interference and other conditions, and further, the communication between the two parties is interrupted or failed.
Therefore, it is necessary to accurately detect the baud rate of serial communication.
Disclosure of Invention
The invention aims to provide a baud rate detection method, a baud rate detection device and a serial port communication system, which can obtain the accurate baud rate of serial port communication.
In order to achieve the above object, the present invention provides a baud rate detection method, comprising the steps of:
S1, determining a pulse number threshold value of a signal waveform of target frame header data of a serial port communication protocol;
s2, carrying out edge detection on the corresponding serial communication signals to capture low-level pulse width and high-level pulse width of the serial communication signals;
S3, judging whether the captured signal waveform is the signal waveform of the target frame header data or not according to the captured low-level pulse width and high-level pulse width when the captured pulse number reaches the pulse number threshold value;
If so, S4 is performed to select at least one low-level pulse width and at least one high-level pulse width in succession from all the captured low-level pulse widths and high-level pulse widths to calculate the baud rate.
Optionally, in step S1, corresponding target frame header data is received and analyzed, and a pulse width ratio between pulses in a signal waveform corresponding to the target frame header data and the pulse number threshold are obtained, where the signal waveform has at least one low level pulse and at least one high level pulse, and a pulse width of each pulse is at least 1 bit.
Optionally, in step S1, the step of parsing the target frame header data includes parsing the target frame header data into a corresponding binary sequence, subtracting a value of 1 from a total number of times data frame signals of the binary sequence are flipped as the pulse number threshold, and recording a number of bits of each segment of the binary sequence in high level and low level, wherein a ratio of the number of bits of the high level to the number of bits of the low level is a pulse width ratio between pulses between corresponding high level pulses and low level pulses.
Optionally, in step S1, at least one of the pulse number threshold, the pulse width ratio between the individual pulses in the signal waveform of the target frame header data is directly configured by a configuration register or a modified code parameter.
Optionally, in step S2, the low-level pulse width and the high-level pulse width of the serial communication signal are captured, and the captured pulses are counted, and capturing is ended when the count within a specified time threshold reaches the pulse number threshold, or capturing is ended when the count exceeds the time threshold.
Optionally, in step S3, comparing the ratio between the captured high-level pulse width and the low-level pulse width with a corresponding ratio threshold, if the comparison result is within the allowable range, determining that the captured signal waveform is the signal waveform of the target frame header data, and if the comparison result is beyond the allowable range, determining that the captured signal waveform is not the signal waveform of the target frame header data;
Or in step S3, comparing the ratio of the time between two adjacent falling edges and two adjacent rising edges in the captured signal waveforms with the corresponding ratio threshold, if the comparison result is within the allowable range, determining that the captured signal waveform is the signal waveform of the target frame header data, and if the comparison result is beyond the allowable range, determining that the captured signal waveform is not the signal waveform of the target frame header data.
Optionally, in step S4, the sum of the pulse widths of a low pulse width and a high pulse width and the total number of bits are calculated, and the sum of the pulse widths is divided by the total number of bits to obtain a time width of one bit, so as to calculate the baud rate.
Optionally, the baud rate detection method further includes, after step S4:
step S5, comparing the baud rate with an ideal baud rate;
and S6, judging whether the baud rate is abnormal or not according to the comparison result, or performing baud rate self-adaptive adjustment according to the comparison result.
Based on the same inventive concept, the present invention also provides a baud rate detection device, which includes:
the pre-configuration module is used for determining a pulse number threshold value of a signal waveform of target frame header data of the serial port communication protocol;
The capture analysis module is used for carrying out edge detection on the corresponding serial communication signals so as to capture low-level pulse width and high-level pulse width of the serial communication signals;
The judging module is used for judging whether the signal waveform captured by the capture analysis module is the signal waveform of the target frame head data or not according to the captured low-level pulse width and high-level pulse width when the number of the pulses captured by the capture analysis module reaches the pulse number threshold value;
And the baud rate calculation module is used for selecting at least one continuous low-level pulse width and at least one continuous high-level pulse width from all low-level pulse widths and high-level pulse widths captured by the capture analysis module to calculate the baud rate after the judgment module determines that the captured signal waveform is the signal waveform of the target frame header data.
Optionally, the pre-configuration module is configured to receive and analyze corresponding target frame header data, and obtain a pulse width ratio between pulses in a signal waveform corresponding to the target frame header data and the pulse number threshold, where the signal waveform has at least one low-level pulse and at least one high-level pulse, and a pulse width of each pulse is at least 1 bit;
Or the pre-configuration module is used for directly configuring at least one of the pulse number threshold value and the pulse width ratio between each pulse in the signal waveform through a configuration register or a modified code parameter.
Optionally, the capture analysis module further comprises at least one of the following circuits:
The edge detection circuit is used for detecting rising edges and falling edges of the serial communication signals so as to generate rising edge trigger signals and falling edge trigger signals;
The capturing circuit is connected with the edge detection circuit and is used for capturing low-level pulse width and high-level pulse width of the serial communication signal according to the rising edge trigger signal and the falling edge trigger signal;
A counting circuit for counting pulses captured by the capturing circuit while the capturing circuit captures a low-level pulse width and a high-level pulse width of the serial communication signal;
The timing circuit is used for timing while the capturing circuit captures the low-level pulse width and the high-level pulse width of the serial communication signal;
and the storage register is used for storing the low-level pulse width and the high-level pulse width captured by the capturing circuit.
Optionally, the baud rate detection device further includes:
An interrupt module for ending the capturing of the capturing circuit when the count of the counting circuit within a prescribed time threshold reaches the pulse number threshold, or when the timing of the timing circuit exceeds the time threshold, or when a prescribed capturing interrupt condition is triggered;
A CPU, wherein at least one of the pre-configuration module, the determination module, and the baud rate calculation module is integrated in the CPU;
And the DMA channel is used for directly carrying the data stored in the storage register into the random access memory for caching so as to be read by the CPU.
Optionally, the judging module is further configured to compare a ratio between the captured high-level pulse width and the captured low-level pulse width with a corresponding ratio threshold, or compare a ratio between two adjacent falling edges and two adjacent rising edges in the captured signal waveform with a corresponding ratio threshold, and when the comparison result is within an allowable range, judge that the captured signal waveform is the signal waveform of the target frame header data.
Optionally, the baud rate calculating module is further configured to calculate a sum of pulse widths of a low pulse width and a high pulse width and a total number of bits, and divide the sum of pulse widths by the total number of bits to obtain a time width of one bit, thereby calculating the baud rate.
Optionally, the baud rate detection device further includes:
the baud rate comparison module is used for comparing the baud rate obtained by the baud rate calculation module with an ideal baud rate;
And the correction module is used for carrying out the baud rate self-adaptive adjustment on the serial port communication signal according to the comparison result of the baud rate comparison module.
Based on the same inventive concept, the invention also provides a serial port communication system, which comprises the baud rate detection device according to the invention.
Optionally, the serial communication system further includes:
the chip to be tested is communicated with the baud rate detection device through a serial port,
The baud rate detection device is used for carrying out baud rate test or correction on the chip to be tested.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. The method can automatically detect the edge, capture the pulse width and judge the signal waveform of the serial communication signal, and continuously calculate the baud rate by adopting 'at least 1 low-level pulse width + at least 1 high-level pulse width', so that the slope error can be eliminated.
2. The target frame header data can be analyzed to obtain the pulse number threshold value and the ratio of the low-level pulse width to the high-level pulse width, so that the operation is simplified, and the efficiency is improved.
3. The user can freely configure the pulse number threshold value corresponding to the target frame header data and the proportion of the low-level pulse width to the high-level pulse width so as to realize the configuration of the personalized target frame header data and the detection of the baud rate corresponding to the personalized target frame header data.
Drawings
Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Wherein:
fig. 1 is a flow chart of a baud rate detection method according to an embodiment of the invention.
Fig. 2 is a schematic flow chart of an example of step S1 in the baud rate detection method shown in fig. 1.
Fig. 3A shows a signal waveform and a pulse number threshold and a pulse width ratio of the target frame header data analyzed in step S1 in the baud rate detection method shown in fig. 1.
Fig. 3B to 3D are 3 exemplary diagrams of capturing signal waveforms that are not target frame header data at step S2 in the baud rate detection method shown in fig. 1.
Fig. 4A and 4B are schematic diagrams of a principle of determining whether the captured signal waveform is the signal waveform of the target frame header data at step S3 in the baud rate detection method shown in fig. 1.
Fig. 5 is a schematic diagram illustrating an exemplary configuration of a baud rate detection apparatus according to an embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating an exemplary structure of a baud rate detecting apparatus according to another embodiment of the present invention.
Fig. 7 is a schematic diagram of the workflow of the baud rate detection device shown in fig. 6.
Fig. 8 is a schematic diagram showing an exemplary structure of a baud rate detecting apparatus according to still another embodiment of the present invention.
Fig. 9 and fig. 10 are schematic structural diagrams of two exemplary serial communication systems according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention. It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element is referred to as being "connected to," "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The technical scheme provided by the invention is further described in detail below with reference to the attached drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Referring to fig. 1, an embodiment of the present invention provides a baud rate detection method, which includes the following steps:
S1, determining a pulse number threshold value of a signal waveform of target frame header data of a serial port communication protocol;
s2, carrying out edge detection on the corresponding serial communication signals to capture low-level pulse width and high-level pulse width of the serial communication signals;
S3, judging whether the captured signal waveform is the signal waveform of the target frame header data or not according to the captured low-level pulse width and high-level pulse width when the captured pulse number reaches the pulse number threshold value;
If yes, executing S4, and selecting at least one continuous low-level pulse width and at least one high-level pulse width from all the captured low-level pulse widths and high-level pulse widths to calculate the baud rate;
if not, returning to S2, continuing to detect the subsequent signals until the target frame header data (namely, the data corresponding to the signal waveform with specific requirements) is found, so that the accuracy of the finally obtained baud rate result can be ensured.
In step S1, the target frame header data is different, and the corresponding signal waveforms (patterns) are also different.
In an embodiment of the present invention, the target frame header data may be preset fixed.
In an embodiment of the present invention, the target frame header data may also allow the user to freely configure as needed. In this case, the target frame header data may be configured by, for example, a User directly configuring at least one of the pulse number threshold and the pulse width ratio of the high and low level pulses by configuring a register or modifying a code parameter, or may be, for example, a result of a program parsing after a User inputs via a User Interface (UI), which has at least the target "high and low level pulse width ratio" and "pulse number threshold". For example, the user inputs format data 0xFB on the UI interface by means of a keyboard or voice input, and step S1 performs format analysis on "0xFB", so as to obtain a pulse number threshold and pulse width ratios of high and low level pulses.
That is, in step S1, the characteristics of the pulse number threshold, the high-low level pulse width ratio, and the like of the signal waveform of the target frame header data of the serial communication protocol may be determined by receiving the preset fixed target frame data or receiving the format data of which the user freely configures. The method for freely configuring the user is suitable for special communication scenes of personalized customized target frame header data of the user, and the method for presetting fixed target frame data is suitable for conventional communication scenes of automatically generating or receiving the fixed target frame header data.
As an example, referring to fig. 2, in step S1, the process of determining the pulse number threshold of the signal waveform of the target frame header data of the serial communication protocol includes:
S11, receiving corresponding target frame header data, wherein the target frame header data can be any suitable data which can be converted into a binary sequence, and can be octal, decimal, hexadecimal or other numerical values;
s12, analyzing the obtained target frame header data into a corresponding binary sequence;
S13, taking the value of 1 subtracted from the total number of times of data frame signal inversion of the binary sequence as the pulse number threshold N;
s14, recording the bit number of each section of high level and low level in the binary sequence, wherein the ratio of the bit number of the high level to the bit number of the low level is the pulse width ratio between corresponding high level pulses and low level pulses;
S15, forming a signal waveform of the target frame header data, and storing related data such as pulse number threshold values and pulse width ratios among pulses, wherein the signal waveform is provided with at least one low-level pulse and at least one high-level pulse, and the pulse width of each pulse is at least 1 bit.
In step S2, the actually transmitted serial communication signal is received to perform edge detection and pulse width capturing.
In an embodiment of the present invention, the edge detection may be started after the idle (high level) time of the serial communication signal reaches the corresponding time threshold, so as to capture the low level pulse width and the high level pulse width of the serial communication signal. For example, the first pulse of the serial communication signal is a low level pulse, and thus the capture of the low level pulse width and the high level pulse width of the serial communication signal begins after the first falling edge is detected.
Optionally, in step S2, the low-level pulse width and the high-level pulse width of the serial communication signal are captured, and the captured pulses are counted, and (1) when the count (i.e. the counted number of pulses) within the specified time threshold Tmax reaches the pulse number threshold N, the timing is ended (i.e. the capturing is interrupted), and the subsequent step S3 is performed, so as to avoid capturing other unnecessary pulses, and improve the efficiency, that is, when M (pulse number threshold) pulses are detected within the specified time in step S2, step S3 is performed to determine whether the captured signal waveform is the signal waveform of the target frame header data according to the low-level pulse width and the high-level pulse width captured in step S2, or (2) when the count exceeds the time threshold Tmax, the capturing is ended (i.e. the capturing is interrupted) in time, and the number of captured pulses is less than the pulse number threshold N, and the interrupt mechanism can prevent the state of waiting for the next pulse or edge for a long time, so as to avoid wasting time.
Optionally, the interrupt (i.e., end) mechanism (i.e., interrupt mechanism) captured in step S2 includes (1) whether the number of pulses captured (i.e., count) reaches a pulse number threshold N, (2) whether the capture time (i.e., timing) exceeds a specified time threshold Tmax, and (3) whether other capture interrupt conditions are triggered. And the interrupt mechanisms are arranged in order of priority from low to high as (1) > (2) > (3).
As an example, please refer to fig. 3A, assuming that the target frame header data received in step S1 is 0x1e, the signal waveform that can be obtained after format parsing of the target frame header data is "2 bits low level+4 bits high level+3 bits low level", that is, the number of edges is 4, the threshold of pulse number n=4-1=3, the first pulse is a low level pulse with bit number T [0] =2, the second pulse is a high level pulse with bit number T [1] =4, the third pulse is a low level pulse with bit number T [2] =3, and the pulse width ratio (that is, the ratio threshold) of the target frame header data is T [0]: T [1]: T [2] =2:4:3. In the edge detection and pulse width capture in step S2, the following cases may occur:
(1) Referring to fig. 3B, in step S2, the number of edges of the actually input serial communication signal frame header is the same as the number of edges of the target frame header data, when the edge detection is performed, N (pulse number threshold) pulses can be detected within a specified time threshold, but when step S3 is performed, it is determined that the bit number T [1] =3 of the captured second pulse is different from the bit number T [1] =4 of the second pulse obtained by parsing the target frame header data, or it is determined that the pulse width ratio of the captured signal waveform is T [0]: T [1]: T [2] =2:3:3 ], when the edge detection is performed, the pulse width ratio of the signal waveform different from the parsing the target frame header data is T [0]: T [2 ]:4:3 ], or it is determined that the pulse width ratio of the captured signal waveform is T [0]: T [2 ]:2:3:3, and compared with the signal waveform obtained by parsing the target frame header data (i.e., the signal waveform is not captured within a specified time threshold of the time threshold, i.e., the signal is not captured until the pulse width ratio T [0]: T [2] =2:3:3:3:is detected).
(2) Referring to fig. 3C, in step S2, when the number of edges of the actually input serial communication signal frame header (6) is greater than the number of edges obtained by analyzing the target frame header data, n=3 (threshold of pulse number) pulses can be detected within a specified time threshold when the actually input serial communication signal is edge-detected, but in step S3, it is determined that the bit number T [1] =3 of the captured second pulse is different from the bit number T [1] =4 of the second pulse obtained by analyzing the target frame header data, or that the pulse width ratio of the captured signal waveform is T [0]: T [1]: T [2] =2:3:3, and that the pulse width ratio T [0]: T [1]: T [2] =2:4:3 of the signal waveform obtained by analyzing the target frame header data is different from the threshold of the signal waveform, or that the pulse width ratio of the captured signal waveform is T [0]: T [1]: T [2 ]:2:4:3 ] is judged, and the signal is captured within a specified time threshold (the time frame header data is not required to be stopped) is stopped, and the signal is stopped, and the time is stopped, and the signal is stopped, for example, the signal is stopped, and the threshold is stopped, and the signal is stopped.
(3) Referring to fig. 3D, in step S2, the number of edges (2) of the frame header of the actually input serial communication signal is less than the number of edges obtained by analyzing the target frame header data, n=3 (threshold pulse number) pulses cannot be detected until the timing exceeds the predetermined time threshold when the actually input serial communication signal is edge-detected, so that the timeout interrupt mechanism is directly triggered without executing step S3, capturing is ended, timing is reset, pulse counting is performed, and the next pulse (i.e., waiting for the next edge) is waited.
As another example, please refer to fig. 4A, assume that the target frame header data set in step S1 is 0XFB, and the signal waveform obtained by parsing the target frame header data is "1 bit low level+2 bit high level+1 bit low level+6 bit high level", and the determined pulse number threshold n=4, where the ratio of these low level pulse widths to high level pulse widths (i.e. the ratio threshold) is 1:2:1:6. When the edge detection and pulse width capture are performed in step S2, 4 pulses are captured in a predetermined time, and the bit number of the last high level pulse allowed to be captured is not less than 6 due to possible discontinuity of communication, then step S3 is performed, and whether the signal waveform captured in step S2 is the signal waveform of the target frame header data in the predetermined time or not is determined by any suitable determination condition, that is, whether the data captured in step S2 in the predetermined time is correct frame header data 0xFB is determined. In this case, since there may be a case where the high-low level pulse width time may be unequal in the same bit width due to the slope error, the judgment condition may be appropriately relaxed in step S3.
In step S3, for example, please refer to fig. 4A, it is determined whether the ratio of the pulse widths of the captured four pulses to the ratio threshold 1:2:1:6 is within the allowable range (e.g. 10% of the ratio error), instead of strictly requiring that the ratio of the captured pulse widths to the pulse widths of the target frame header data is completely equal, if so, the captured signal waveform is considered to be the signal waveform of the target frame header data, i.e. the captured data may be considered to be the correct frame header data 0xFB, and if not, the captured signal waveform is not considered to be the signal waveform of the target frame header data, i.e. the captured data may be considered to be the incorrect frame header data 0xFB.
In another determination manner in step S3, for example, please refer to fig. 4B, the ratio of the time between two adjacent falling edges and two adjacent rising edges in the captured signal waveform is compared with a corresponding proportional threshold (may be 1), for example, the ratio of the time between the first falling edge and the second falling edge and the time between the first rising edge and the second rising edge is compared with a corresponding proportional threshold, that is, the ratio (l0+l1)/(l1+l2) between the sum of the pulse widths of the first pulse and the second pulse and the sum of the pulse widths of the second pulse and the third pulse is compared with a proportional threshold 1, and if the difference equal to 1 or (l0+l1)/(l1+l2) and 1 is within the allowable range (for example, within ±5%) the captured signal waveform is considered to be the signal waveform of the target frame header data, that is, the captured data may be considered to be the correct frame header data 0xFB, and if the captured signal is not considered to be the correct frame header data.
After confirming that the captured signal waveform is the signal waveform of the target frame header data (for example, the captured data may be regarded as the correct frame header data 0xFB as described above) in step S3, in step S4, a continuous one low-level pulse width and one high-level pulse width may be selected from the respective pulse widths captured in step S2, added, and further divided by the total bit number of both, to obtain a one-bit time width (abbreviated as bit time BT), that is, the time required for transmitting one-bit data. For example, a first low-level pulse width is selected and added to a first high-level pulse width thereafter, a time width of 1 bit (also referred to as bit time) bt= (l0+l1)/(1+2) =104 μs is calculated, and the available baud rate BR is further calculated (for example, the reciprocal of BT is taken), that is, br=1/BT.
It should be appreciated that in other embodiments of the present invention, in step S4, it is also possible to select a continuous at least one low level pulse width and at least one high level pulse width from the respective pulse widths captured in step S2, add them, and further divide the total bit number of these pulse widths to obtain a bit time (bit time). For example, referring to fig. 4B, a first low level pulse width and a second low level pulse width are selected, and a first high level pulse width sandwiched between the two is further selected, and the three pulse widths are added and further divided by the total bit number of the three pulse widths, so as to calculate the bit time bt= (l0+l1+l2)/(1+2+1). For another example, referring to fig. 4B, the calculated bit time bt= (l0+l1+l2+l3)/(1+2+1+6) is calculated by selecting the pulse width addition of 4 consecutive pulses and dividing by the total bit number of the 4 pulses.
Optionally, after step S4, step S5 may be further performed to compare the baud rate calculated in step S4 with the ideal baud rate, and step S6 may further include determining whether the baud rate is abnormal according to the comparison result, or performing baud rate adaptive adjustment according to the comparison result.
Based on the same inventive concept, please refer to fig. 5, an embodiment of the present invention further provides a baud rate detection apparatus 1, which can implement the baud rate detection method of the present invention, and may include a pre-configuration module 11, a capture analysis module 12, a judgment module 13, and a baud rate calculation module 14.
The pre-configuration module 11 is configured to implement step S1 of the baud rate detection method of the present invention, that is, determine a pulse number threshold of a signal waveform of target frame header data of a serial communication protocol. Optionally, the pre-configuration module 11 may receive corresponding target frame header data (the target frame header data may be freely configured by a user according to needs, or may be preset fixed target frame header data sent by an external device such as a chip to be tested), and parse the target frame header data to obtain a signal waveform corresponding to the target frame header data, and a pulse width ratio between the pulse number threshold value of the signal waveform and each pulse, where the signal waveform has at least one low level pulse and at least one high level pulse, and a pulse width of each pulse is at least 1 bit, or the pre-configuration module directly configures at least one of the pulse number threshold value and the pulse width ratio between each pulse in the signal waveform corresponding to the target frame header data through a configuration register or a modified code parameter, so as to implement information such as the pulse number threshold value to be configured in the pre-configuration module 11. The working principle of the pre-configuration module 11 may be described with reference to the content of step S1, which is not described herein.
The capture analysis module 12 is configured to implement step S2 of the baud rate detection method of the present invention, that is, perform edge detection on a corresponding serial communication signal to capture a low-level pulse width and a high-level pulse width of the serial communication signal.
Optionally, the capture analysis module 12 includes at least one of the following circuits:
an edge detection circuit 121, configured to detect a rising edge and a falling edge of the serial communication signal, so as to generate a rising edge trigger signal and a falling edge trigger signal;
the capturing circuit 122 is connected with the edge detecting circuit 121 and is used for capturing a low-level pulse width and a high-level pulse width of the serial communication signal according to the rising edge trigger signal and the falling edge trigger signal;
A counting circuit 123, connected to the edge detection circuit 121, and configured to trigger when the edge detection circuit 121 detects an edge (e.g., a first edge) corresponding to the serial communication signal, so as to count pulses captured by the capturing circuit 122 while capturing a low-level pulse width and a high-level pulse width of the serial communication signal;
a timing circuit 124, connected to the edge detection circuit 121, for triggering when the edge detection circuit 121 detects an edge (e.g., a first edge) corresponding to the serial communication signal, so as to perform timing while the capturing circuit 122 captures a low-level pulse width and a high-level pulse width of the serial communication signal;
A storage register 125 for storing the low-level pulse width and the high-level pulse width captured by the capturing circuit 122. In an embodiment of the present invention, the storage register 125 may further include a configuration register to store a pulse number threshold value of a signal waveform of the target frame header data configured or determined in the pre-configuration module 11, a pulse width ratio between the respective pulses.
The determining module 13 is configured to determine whether the signal waveform captured by the capturing and analyzing module 12 is the signal waveform of the target frame header data according to the low-level pulse width and the high-level pulse width captured by the capturing and analyzing module 12 when the number of pulses captured by the capturing and analyzing module 12 reaches the threshold value of the number of pulses in step S3 of the baud rate detecting method of the present invention. For example, the determining module 13 is further configured to compare the ratio between the high-level pulse width and the low-level pulse width captured by the capturing and analyzing module 12 with a corresponding ratio threshold, or compare the ratio between the time between two adjacent falling edges and two adjacent rising edges in the captured signal waveforms with a corresponding ratio threshold, and determine that the signal waveform captured by the capturing and analyzing module 12 is the signal waveform of the target frame header data when the comparison result is within the allowable range. The working principle of the determining module 13 may be described with reference to the content of step S3, which is not described herein.
Optionally, the judgment module 13 resets the counting circuit 123 and the timing circuit 124 in the capture analysis module 12 after determining that the captured signal waveform is not the signal waveform of the target frame header data.
The baud rate calculating module 14 is configured to implement step S4 of the baud rate detecting method of the present invention, namely, after the determining module 13 determines that the captured signal waveform is the signal waveform of the target frame header data, select at least one continuous low-level pulse width and at least one continuous high-level pulse width from all low-level pulse widths and high-level pulse widths captured by the capturing analysis module 12 to calculate the baud rate. For example, the baud rate calculation module 14 calculates the sum of the pulse widths of a low pulse width and a high pulse width and the total number of bits, divides the sum of the pulse widths by the total number of bits to obtain a time width BT of one bit, and further calculates the baud rate (for example, taking the inverse of BT) based on the time width to one bit. The operating principle of the baud rate calculating module 14 may be described with reference to the above content of step S4, which is not described herein.
Referring to fig. 6, in another embodiment of the present invention, the baud rate detection device further includes, in addition to the pre-configuration module 11, the capture analysis module 12, the judgment module 13, and the baud rate calculation module 14, the following steps:
An interrupt module 15 for ending the capturing of the capturing circuit when the count of the capturing circuit within a prescribed time threshold reaches the pulse number threshold, or when the count exceeds the time threshold, or when a prescribed capturing interrupt condition is triggered.
A CPU 18 in which at least one of the pre-configuration module 11, the judgment module 13, and the baud rate calculation module 14 is integrated;
A DMA channel 17 and a random access memory (e.g., RAM) 16, the DMA channel 17 being configured to directly transfer data stored in the storage register 125 to the random access memory 16 for caching, not by the CPU.
The operating principle of the baud rate detection device of the present embodiment is shown in fig. 7, and includes the following operations:
First, determining a pulse number threshold value N of a signal waveform of target frame header data and the like by the pre-configuration module 11;
Next, the maximum count value of the counter circuit 123 (or the maximum count value in the DMA 17) dma_cnt maximum value is configured to N according to the pulse number threshold value N obtained in the pre-configuration module 11;
Then, the maximum timing value in the timing circuit 124 is configured to Tmax according to the information such as the pulse number threshold N configured in the pre-configuration module 11;
after that, the setting edge detecting circuit 121 starts the capturing circuit 122 and resets the counting circuit 123 and the timer circuit 124 when detecting the first rising edge or falling edge;
Waiting for the count value dma_cnt of the counting circuit 123 (or the count value in the DMA 17) to reach N, triggering a timeout interrupt mechanism if the timer circuit 124 times out, resetting the count value dma_cnt of the counting circuit 123 (or the count value in the DMA 17) to wait for the next baud rate detection, and if N is reached and not timed out, reading the data (i.e. the pulse width of the corresponding pulse) in the RAM16 by the judging module 13 to judge whether the data (i.e. the signal waveform) captured by the capturing circuit 122 is the target frame header data. If it is determined that the data (i.e., the signal waveform) captured by the capturing circuit 122 is not the target frame header data, the count value dma_cnt (or the count value in the DMA 17) of the count circuit 123 is reset to wait for the next baud rate detection;
If the determining module 13 determines that the data (i.e. the signal waveform) captured by the capturing circuit 122 is the target frame header data, the baud rate calculating module 14 reads the corresponding data (such as a continuous low pulse width and a continuous high pulse width) in the RAM 16, and calculates the baud rate according to the data.
In an embodiment of the present invention, referring to fig. 8, the baud rate detection device further includes:
the baud rate comparing module 19 is configured to compare the baud rate obtained by the baud rate calculating module 14 with an ideal baud rate;
and the correction module 10 is used for carrying out baud rate self-adaptive adjustment on the serial communication signal according to the comparison result of the baud rate comparison module 19.
It should be understood that, in the baud rate detecting apparatus of the present invention, the pre-configuration module 11, the capture analysis module 12, the judgment module 13, the baud rate calculation module 14, the interrupt module 15, the CPU 18, the DMA channel 17 and the random access memory 16, the baud rate comparison module 19, the correction module 10, and the like may be combined in one module, or any one of the circuit modules may be split into a plurality of modules, or at least part of the functions or circuits of one or more of the circuit modules may be combined with at least part of the functions or circuits of other circuit modules and implemented in one module. According to an embodiment of the present invention, at least one of the pre-configuration module 11, the capture analysis module 12, the determination module 13, the baud rate calculation module 14, the interrupt module 15, the CPU 18, the DMA channel 17, and the random access memory 16, the baud rate comparison module 19, the correction module 10, etc. may be implemented at least partially as hardware circuitry, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or any other reasonable way of integrating or packaging the circuitry, or as hardware or firmware, or as a suitable combination of three implementations of software, hardware and firmware. Or at least one of the pre-configuration module 11, the capture analysis module 12, the judgment module 13, the baud rate calculation module 14, the interrupt module 15, the CPU 18, the DMA channel 17, the random access memory 16, etc. may be at least partially implemented as a computer program module, which when executed by a computer, may perform the functions of the corresponding module.
For example, referring to fig. 6 and 8, the pre-configuration module 11, the capture analysis module 12, the judgment module 13, the baud rate calculation module 14 and the interrupt module 15, the baud rate comparison module 19, and the correction module 10 are all integrated in the CPU 18, or one or more of the pre-configuration module 11, the capture analysis module 12, the judgment module 13, the baud rate calculation module 14 and the interrupt module 15, the baud rate comparison module 19, and the correction module 10 are disposed outside the CPU 18.
It should be understood that the baud rate detection device of the present invention is applicable to any scenario requiring detection of baud rate or correction and adaptive adjustment of baud rate under a serial communication protocol.
Based on this, referring to fig. 9, an embodiment of the present invention further provides a serial communication system, which includes the baud rate detecting device 1 according to the present invention.
In an embodiment of the present invention, the serial communication system further includes a chip to be tested 2, which communicates with the baud rate detecting device 1 through a serial port (having a signal transmitting module TX and a signal receiving module RX). The baud rate detection device 1 performs baud rate test or correction on the chip 2 to be tested.
As an example, referring to fig. 10, the baud rate detecting device 1 may be directly used as a test/correction device for performing baud rate detection on a corresponding chip 2 to be tested (for example, an MCU chip, etc.), or the baud rate detecting device 1 may be integrated as a module in a test/correction device for performing a correlation test on a corresponding chip 2 to be tested, the chip 2 to be tested and the baud rate detecting device 1 may be in serial communication, and the baud rate detecting device 1 may be placed in the test/correction device and powered from the test/correction device.
An RC oscillator (RC oscillator) 21, a serial port module 22 and a clock bias correction module 23 are disposed in the chip 2. The RC oscillator 21 is used as a clock source to configure a working clock of the system, and the clock is also provided for peripheral modules of the chip 2 to be tested, such as the serial port module 22. The serial port module 22 further divides the frequency of the peripheral bus clock with a frequency divider (e.g., PLL) with small digits to obtain a target baud rate, and the device (e.g., baud rate detection device 1) coupled to the serial port module 22 communicates with the chip 2 to be tested through the target baud rate. However, the accuracy of the RC oscillator 21 decreases within a certain period of time, and the deviation of the clock may cause the baud rate to decrease compared with the expected one, which may cause the baud rate of the serial port communication to decrease, and if the deviation between the actual baud rate and the target baud rate is too large, the communication performance of the system may be affected. Therefore, when the baud rate detection device 1 of the present invention receives the data transmitted by the chip 2 to be detected, the baud rate detection device 1 can calculate the corresponding baud rate according to the received data, and further judge whether the baud rate of the chip 2 to be detected is abnormal or not. In a further embodiment, the baud rate detection result of the baud rate detection device 1 may be fed back to the clock bias correction module 23 in the chip 2 to be detected through the serial port, the clock bias correction module 23 compares the actual baud rate detected by the baud rate detection device 1 with the target baud rate, calculates the bias of the actual baud rate and the target baud rate, and thus reversely derives the specific bias proportion of the clock, and further corrects the clock bias of the RC oscillator 21, so as to ensure that the baud rate used by the serial port module 22 is accurate.
Alternatively, the clock skew correction module 23 may include a fractional divider (e.g., PLL) or the like to correct the operating clock of the RC oscillator 21 to an accurate clock having the target baud rate.
Alternatively, the test/correction apparatus may also show the range of deviation of the calculated baud rate from the target baud rate to the user, or indicate whether the baud rate is abnormal or not, based on the result of the baud rate detection apparatus 1.
In summary, the baud rate detection device and the serial port communication system of the invention can accurately detect the baud rate, eliminate the slope error, and are suitable for any suitable serial port communication scene.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention in any way, and any changes and modifications made by those skilled in the art in light of the foregoing disclosure will be deemed to fall within the scope and spirit of the present invention.
Claims (17)
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