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CN119451163A - GaN HEMT based on superlattice back barrier structure and preparation method thereof - Google Patents

GaN HEMT based on superlattice back barrier structure and preparation method thereof Download PDF

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CN119451163A
CN119451163A CN202510031997.5A CN202510031997A CN119451163A CN 119451163 A CN119451163 A CN 119451163A CN 202510031997 A CN202510031997 A CN 202510031997A CN 119451163 A CN119451163 A CN 119451163A
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gan
superlattice
back barrier
ingan
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崔鹏
齐开发
韩吉胜
汉多科·林纳威赫
徐现刚
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Shandong University
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Shandong University
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Abstract

The invention relates to a GaN HEMT based on superlattice back barrier structure and a preparation method thereof, belonging to the technical field of microelectronics, comprising a substrate, an AlN nucleation layer, a GaN buffer layer, an InGaN/GaN superlattice back barrier layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer and a GaN cap layer from bottom to top, a drain electrode and a source electrode are respectively arranged at two ends above the GaN channel layer, a gate electrode is arranged above a GaN cap layer close to the source electrode, and a SiN passivation layer is arranged between the drain electrode and the source electrode above the GaN cap layer. The superlattice structure formed by InGaN and GaN is used as the back barrier layer, so that electric leakage can be restrained, the energy band is obviously lifted, and the breakdown characteristic of the HEMT device is improved.

Description

GaN HEMT based on superlattice back barrier structure and preparation method thereof
Technical Field
The invention relates to a GaN HEMT based on a superlattice back barrier structure and a preparation method thereof, belonging to the technical field of microelectronics.
Background
The development of silicon-based power devices has become increasingly mature, and the performance approaches the physical limits of the materials. The limitation of the material performance becomes a key factor for restricting the further improvement of the performance of the silicon-based power device. The third generation semiconductor materials represented by gallium nitride are becoming a research hot spot of new generation power devices due to their excellent characteristics of wide band gap, high critical breakdown field strength, low dielectric constant, etc.
AlGaN/GaN HEMT devices benefit from their unique heterojunction structure and material properties, the ability to form two-dimensional electron gas to achieve higher channel mobility and their own large critical breakdown field strength, which make their application in the high power switching field very attractive. However, the commercialization of the GaNHEMT device is mainly implemented in the field of medium-low voltage power devices, and is mainly limited by the reasons of fringe electric field concentration effect, leakage current and the like, so that breakdown occurs in advance when the voltage resistance of the device is far less than the theoretical limit of the material.
In the past researches, in order to inhibit the leakage of devices and improve the withstand voltage of the devices, the growth process of epitaxial materials is optimized, the quality of the materials is improved or specific epitaxial layers and other technologies are introduced, such as an InGaN back barrier layer is introduced, but In order to prevent the precipitation of In components, the InGaN back barrier layer cannot grow very thick, so that the leakage of the devices is limited.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a GaN HEMT based on a superlattice back barrier structure and a preparation method thereof, and the superlattice structure formed by InGaN and GaN is used as a back barrier layer, so that electric leakage can be inhibited, an energy band can be obviously lifted, and the breakdown characteristic of an HEMT device can be improved.
The invention adopts the following technical scheme:
The GaN HEMT based on the superlattice back barrier structure comprises a substrate, an AlN nucleation layer, a GaN buffer layer, an InGaN/GaN superlattice back barrier layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer and a GaN cap layer from bottom to top in sequence, wherein a drain electrode and a source electrode are respectively arranged at two ends above the GaN channel layer, a gate electrode is arranged above the GaN cap layer close to the source electrode, and a SiN passivation layer is arranged between the drain electrode and the source electrode above the GaN cap layer.
Preferably, the substrate is one of Si, siC, al 2O3, preferably a SiC substrate, wherein the Si substrate is produced by a relatively mature process, at a low cost but with poor quality of GaN due to a large lattice mismatch with GaN, with excellent quality but expensive quality of epitaxially grown crystals, and the Al 2O3 substrate is interposed between them.
The AlN nucleation layer has a thickness of 5-1000 nm, the AlN nucleation layer can reduce the lattice mismatch problem between the GaN buffer layer and the substrate, the crystal quality is improved, and the AlN nucleation layer preferably has a thickness of 100 nm.
The thickness of the GaN buffer layer is 0.1-20 μm, preferably, the thickness of the GaN buffer layer is 1.5 μm;
preferably, the In mass percent of the InGaN/GaN superlattice back barrier layer is 1% -40%. Further preferably, the InGaN/GaN superlattice back barrier layer has an In mass percentage of 5%.
Preferably, the total thickness of the InGaN/GaN superlattice back barrier layer is 5-500 nm, wherein the thickness of the InGaN layer is 1-10 nm, and the thickness of the GaN layer is 1-30 nm.
Preferably, the total thickness of the InGaN/GaN superlattice back barrier layer is 30nm, wherein the thickness of the InGaN layer is 1nm, the thickness of the GaN layer is 5nm, and the cycle period of the InGaN layer and the GaN layer is 5.
In the material growth process, in order to prevent the In from precipitating out of the too thick InGaN layer which cannot be grown, and the InGaN layer has strong polarization, a higher potential barrier can be obtained by a thinner InGaN layer. Secondary channel potential wells (primary channel potential wells formed at the interface of the AlGaN barrier layer and the GaN channel layer) may be formed at the interface of InGaN and GaN when the InGaN layer is interposed, the formation of the secondary channel potential wells may reduce the ability of the gate to control channel two-dimensional electron gas under high drain bias, while thinner InGaN may inhibit the formation of secondary channels. The thickness of the GaN layer is not too thick, and the too thick layer can lead to the overlarge distance between two adjacent layers of InGaN, so that the gas limitation of two-dimensional electrons is weakened. And In order to prevent the In component from being separated out, the GaN growth temperature is low, the quality of GaN crystal is deteriorated, and it is not suitable for thick growth.
The superlattice structure is formed when the cycle period of the InGaN layer and the GaN layer is more than 1, and the band lifting effect can be increased by multiple times of cycle growth. However, as can be seen in connection with fig. 11, the limiting effect on electrons after 5 cycles is already more pronounced and the increase in cycle period is continued to be less productive. And because of the low temperature alternate growth of two different materials, inGaN and GaN, excessive cycling may lead to poor crystal quality.
Preferably, the thickness of the GaN channel layer is 5-50 nm, and preferably, the thickness of the GaN channel layer is 10 nm;
the thickness of the AlN intercalation is 0.2-10 nm, and preferably, the thickness of the AlN intercalation is 1 nm;
the Al mass percentage of the AlGaN barrier layer is 5% -30%, more preferably, the Al mass percentage of the AlGaN barrier layer is 20%, and the thickness of the AlGaN barrier layer is 5-40 nm, preferably, 20 nm.
Preferably, the thickness of the GaN cap layer is 0-100 nm, preferably 2 nm;
The drain electrode and the source electrode are made of Ti/Al/Ni/Au electrodes, and the gate electrode is made of Ni/Au electrodes;
The SiN passivation layer has a thickness of 10-3000 nm, preferably 200 nm a.
The InGaN/GaN superlattice layer structure is grown between the channel layer and the buffer layer, and potential barriers are formed through the polarization action of the InGaN and the GaN, so that energy bands are lifted, the limiting field of two-dimensional electron gas is enhanced, and the breakdown voltage of the device is improved.
The preparation method of the GaN HEMT based on the superlattice back barrier structure comprises the following steps:
s1, sequentially epitaxially growing an AlN nucleation layer, a GaN buffer layer, an InGaN/GaN superlattice back barrier layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer and a GaN cap layer on a substrate;
s2, removing a GaN cap layer, an AlGaN barrier layer and an AlN intercalation layer below the drain electrode and the source electrode through ICP etching until reaching the top of the GaN channel layer to form a drain electrode and a source electrode region;
s3, evaporating metal Ti/Al/Ni/Au in the drain electrode and source electrode areas, and annealing to form ohmic contact;
S4, evaporating metal Ni/Au on the gate electrode area above the GaN cap layer to form Schottky contact;
And S5, growing a SiN passivation layer between the source electrode and the drain electrode above the GaN cap layer.
Preferably, in the step S3, the method for evaporating metal Ti/Al/Ni/Au is an electron beam evaporation or magnetron sputtering technology, the annealing temperature is 700-1000 ℃ and the annealing time is 20-600S, and further, the method for evaporating metal Ti/Al/Ni/Au is a magnetron sputtering technology, and the annealing condition is that the annealing is 40S at 850 ℃ in N 2.
Preferably, in step S1, the epitaxial growth method is a liquid phase epitaxial growth method (LPE), a metal organic chemical vapor deposition Method (MOCVD), or a molecular beam epitaxy Method (MBE), preferably a metal organic chemical vapor deposition Method (MOCVD);
in step S5, the SiN passivation layer is grown by Low Pressure Chemical Vapor Deposition (LPCVD), plasma enhanced chemical deposition (PECVD), or Atomic Layer Deposition (ALD).
The invention is not exhaustive and can be seen in the prior art.
The beneficial effects of the invention are as follows:
1. Greater band lifting
When InGaN material has a narrower forbidden bandwidth than GaN, the InGaN back barrier layer and the underlying GaN buffer layer have a significantly increased energy band due to the effect of the polarization electric field that tilts the energy band when InGaN is In a compressive strain state, and when InGaN back barrier layer is used as the back barrier layer, the InGaN back barrier layer is usually grown to be very thin and not more than 10nm In order to prevent In precipitation, so the effect of raising the energy band of the buffer layer is limited. The superlattice structure is formed by alternately growing InGaN and GaN, and higher energy band lifting can be realized by growing multiple layers of InGaN.
2. Higher breakdown voltage
The energy band of the buffer layer is raised due to the fact that the energy band of the buffer layer is raised by the introduction of the InGaN/GaN superlattice back barrier layer, the limitation of two-dimensional electron gas (2 DEG) is enhanced, the diffusion of the two-dimensional electron gas to the buffer layer is restrained under the off state of the device, the leakage current of the buffer layer is weakened, the withstand voltage of the device is improved, and the device has higher breakdown voltage.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application.
FIG. 1 is a schematic view of a substrate of the present invention;
FIG. 2 is a schematic diagram of a device structure obtained in step S1 of the present invention;
FIG. 3 is a schematic diagram of a device structure obtained in step S2 of the present invention;
FIG. 4 is a schematic diagram of a device structure obtained in step S3 of the present invention;
FIG. 5 is a schematic diagram of the device structure obtained in step S4 of the present invention;
fig. 6 is a schematic diagram of a GaN HEMT structure based on a superlattice back barrier structure obtained in step S5 in the present invention;
Fig. 7 is a schematic diagram of an InGaN/GaN superlattice back barrier layer in accordance with an embodiment of the invention;
Fig. 8 is a schematic diagram of breakdown images of a non-back barrier HEMT device, a single layer InGaN back barrier HEMT device, and an InGaN/GaN superlattice back barrier HEMT device;
Fig. 9 is an image of electron concentration distribution in the off state of a HEMT device without a back barrier layer;
Fig. 10 is an image of electron concentration distribution in an off state of a single InGaN back barrier HEMT device;
fig. 11 is an image of electron concentration distribution in an off state of an InGaN/GaN superlattice back barrier layer HEMT device according to an embodiment of the invention;
fig. 12 is a schematic diagram of energy band images of a non-back barrier HEMT device, a single layer InGaN back barrier HEMT device, and an InGaN/GaN superlattice back barrier HEMT device;
In the figure, a 1-substrate, a 2-AlN nucleation layer, a 3-GaN buffer layer, a 4-InGaN/GaN superlattice back barrier layer, a 5-GaN channel layer, a 6-AlN intercalation layer, a 7-AlGaN barrier layer, an 8-GaN cap layer, a 9-SiN passivation layer, a 10-drain electrode, an 11-source electrode and a 12-gate electrode.
Detailed Description
In order to better understand the technical solutions in the present specification, the following description will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the implementation of the present specification, but not limited thereto, and the present invention is not fully described and is according to the conventional technology in the art.
Example 1
The GaN HEMT based on the superlattice back barrier structure comprises a substrate 1, an AlN nucleation layer 2, a GaN buffer layer 3, an InGaN/GaN superlattice back barrier layer 4, a GaN channel layer 5, an AlN intercalation layer 6, an AlGaN barrier layer 7 and a GaN cap layer 8 from bottom to top, wherein a drain electrode 10 and a source electrode 11 are respectively arranged at two ends above the GaN channel layer 5, a gate electrode 12 is arranged above the GaN cap layer 8 close to the source electrode 11, and a SiN passivation layer 9 is arranged between the drain electrode and the source electrode above the GaN cap layer 8.
The substrate 1 is a SiC substrate, and the AlN nucleation layer 2 has a thickness of 100 nm.
The thickness of the GaN buffer layer 3 was 1.5. Mu.m;
The In mass percentage of the InGaN/GaN superlattice back barrier layer 4 is 5%.
The total thickness of the InGaN/GaN superlattice back barrier layer 4 was 30nm, in which the thickness of the InGaN layer was 1nm, the thickness of the GaN layer was 5nm, and the cycle period of the InGaN layer and the GaN layer was 5, as shown in fig. 7.
In the material growth process, in order to prevent the In from precipitating out of the too thick InGaN layer which cannot be grown, and the InGaN layer has strong polarization, a higher potential barrier can be obtained by a thinner InGaN layer. Secondary channel potential wells (primary channel potential wells formed at the interface of the AlGaN barrier layer and the GaN channel layer) may be formed at the interface of InGaN and GaN when the InGaN layer is interposed, the formation of the secondary channel potential wells may reduce the ability of the gate to control channel two-dimensional electron gas under high drain bias, while thinner InGaN may inhibit the formation of secondary channels. The thickness of the GaN layer is not too thick, and the too thick layer can lead to the overlarge distance between two adjacent layers of InGaN, so that the gas limitation of two-dimensional electrons is weakened. And In order to prevent the In component from being separated out, the GaN growth temperature is low, the quality of GaN crystal is deteriorated, and it is not suitable for thick growth.
The superlattice structure is formed when the cycle period of the InGaN layer and the GaN layer is more than 1, and the band lifting effect can be increased by multiple times of cycle growth. However, as can be seen in connection with fig. 11, the limiting effect on electrons after 5 cycles is already more pronounced and the increase in cycle period is continued to be less productive. And because of the low temperature alternate growth of two different materials, inGaN and GaN, excessive cycling may lead to poor crystal quality.
The thickness of the GaN channel layer 5 is 10 nm;
The thickness of AlN intercalation 6 is 1 nm;
the Al mass percentage of the AlGaN barrier layer 7 is 20 percent, and the thickness of the AlGaN barrier layer 7 is 20 nm;
The thickness of the GaN cap layer 8 is 2 nm;
The materials of the drain electrode 10 and the source electrode 11 are Ti/Al/Ni/Au electrodes, and the materials of the gate electrode 12 are Ni/Au electrodes;
the SiN passivation layer 9 has a thickness of 200 nm a.
Example 2
A GaN HEMT based on a superlattice back barrier structure as described in example 1, except that AlN nucleation layer 2 has a thickness of 5 nm a.
Example 3
A GaN HEMT based on a superlattice back barrier structure as described in example 1, except that AlN nucleation layer 2 has a thickness of 1000 nm a.
Example 4
A GaN HEMT based on a superlattice back barrier structure, as described in example 1, except that the GaN buffer layer 3 has a thickness of 0.1 μm.
Example 5
A GaN HEMT based on a superlattice back barrier structure, as described in example 1, except that the GaN buffer layer 3 has a thickness of 20 μm.
Example 6
A GaN HEMT based on a superlattice back barrier structure is described In example 1, except that the InGaN/GaN superlattice back barrier layer 4 has an In mass percentage of 1%.
Example 7
A GaN HEMT based on a superlattice back barrier structure is described In example 1, except that the InGaN/GaN superlattice back barrier layer 4 has an In mass percentage of 40%.
Example 8
A GaN HEMT based on a superlattice back barrier structure is described in example 1, except that the total thickness of the InGaN/GaN superlattice back barrier layer 4 is 6nm, wherein the InGaN layer thickness is 1nm and the GaN layer thickness is 2nm.
Example 9
A GaN HEMT based on a superlattice back barrier structure is described in example 1, except that the total thickness of the InGaN/GaN superlattice back barrier layer 4 is 500nm, wherein the InGaN layer thickness is 2nm and the GaN layer thickness is 8nm.
Example 10
A GaN HEMT based on a superlattice back barrier structure is different from that of embodiment 1 in that the GaN channel layer 5 has a thickness of 5 nm.
Example 11
A GaN HEMT based on a superlattice back barrier structure is as described in example 1, except that the GaN channel layer 5 has a thickness of 50 nm a.
Example 12
A GaN HEMT based on a superlattice back barrier structure as described in example 1, except that the AlN interlayer 6 has a thickness of 0.2 nm a.
Example 13
A GaN HEMT based on a superlattice back barrier structure as described in example 1, except that the AlN interlayer 6 has a thickness of 10 nm a.
Example 14
A GaN HEMT based on a superlattice back barrier structure as described in example 1, except that the GaN cap layer 8 has a thickness of 100 nm a.
Example 15
A GaN HEMT based on a superlattice back barrier structure as described in example 1, except that the SiN passivation layer 9 has a thickness of 10 nm a.
Example 16
A GaN HEMT based on a superlattice back barrier structure as described in example 1, except that the SiN passivation layer 9 has a thickness of 3000 nm a.
Example 17
The preparation method of the GaN HEMT based on the superlattice back barrier structure in embodiment 1 comprises the following steps:
S1, sequentially epitaxially growing an AlN nucleation layer 2, a GaN buffer layer 3, an InGaN/GaN superlattice back barrier layer 4, a GaN channel layer 5, an AlN intercalation layer 6, an AlGaN barrier layer 7 and a GaN cap layer 8 on a substrate 1 by adopting an MOCVD method;
S2, removing the GaN cap layer 8, the AlGaN barrier layer 7 and the AlN intercalation layer 6 below the drain electrode and the source electrode through ICP etching until reaching the top of the GaN channel layer 5 to form a drain electrode 10 and a source electrode 11 region;
s3, evaporating metal Ti/Al/Ni/Au in the drain electrode and source electrode areas, and annealing to form ohmic contact, wherein the method for evaporating metal Ti/Al/Ni/Au is a magnetron sputtering technology, and the annealing condition is that annealing is performed at 850 ℃ in N 2 for 40S;
s4, evaporating metal Ni/Au on the gate electrode 12 area above the GaN cap layer 8 to form Schottky contact;
And S5, growing a SiN passivation layer 9 between the source electrode 11 and the drain electrode 10 above the GaN cap layer 8 by a plasma enhanced chemical deposition (PECVD) method.
Comparative example 1
A HEMT device without a back barrier layer is characterized in that a GaN channel layer is directly grown on a GaN buffer layer, an InGaN/GaN superlattice back barrier layer is not present, and other structures are the same as in the embodiment 1.
Comparative example 2
A single-layer InGaN back barrier layer HEMT device has only one InGaN layer in the back barrier layer, no GaN layer, and other structures are the same as those in embodiment 1.
Fig. 8 is a graph showing the breakdown images of the non-back barrier layer HEMT device of comparative example 1, the single-layer InGaN back barrier layer HEMT device of comparative example 2, and the InGaN/GaN superlattice back barrier layer HEMT device of example 1, in fig. 8, the abscissa is the drain voltage, and the ordinate is the source-drain current, wherein the drain voltage corresponding to the abrupt change of the source-drain current is the breakdown voltage of the device, and it can be observed that the abrupt change of the source-drain current of the InGaN/GaN superlattice back barrier layer HEMT device occurs at the latest along with the rise of the drain voltage, which indicates that the breakdown voltage is higher than that of the non-back barrier layer HEMT device and the single-layer InGaN back barrier layer HEMT device.
Fig. 9 to 11 are electron concentration distribution patterns in the off state of the non-back barrier layer HEMT device of comparative example 1, the single-layer InGaN back barrier layer HEMT device of comparative example 2, and the InGaN/GaN superlattice back barrier layer HEMT device of example 1, respectively, in which the dark portion is the electron distribution of the channel region, it can be found that the width of the dark region of the InGaN/GaN superlattice back barrier layer HEMT device of example 1 is the narrowest, because electrons are limited by the superlattice back barrier layer, and diffusion of electrons at the channel to the buffer layer is suppressed. The InGaN/GaN superlattice back barrier layer has obvious effect of lifting the energy band of the barrier layer and plays a role of limiting the two-dimensional electron gas.
Fig. 12 is a schematic diagram of energy band images of the non-back barrier layer HEMT device of comparative example 1, the single layer InGaN back barrier layer HEMT device of comparative example 2, and the InGaN/GaN superlattice back barrier layer HEMT device of example 1, wherein the dashed line represents the fermi level, in which the fermi level can be considered as a hypothetical level that is occupied by 50% probability when the thermodynamics are balanced, the state above the fermi level is generally considered as empty, the state below the fermi level is generally considered as filled by electrons, the abscissa is the longitudinal distance, and the energy band energy of the InGaN/GaN superlattice back barrier layer HEMT device is higher than that of the non-back barrier layer HEMT device and the single layer InGaN back barrier layer HEMT device, which means that the introduction of the InGaN/GaN superlattice back barrier layer causes the device buffer layer energy band to be raised.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims (10)

1.一种基于超晶格背势垒结构的GaN HEMT,其特征在于,从下至上依次包括衬底、AlN成核层、GaN缓冲层、InGaN/GaN超晶格背势垒层、GaN沟道层、AlN插层、AlGaN势垒层和GaN帽层,在GaN沟道层上方的两端分别设置有漏电极和源电极,在靠近源电极的GaN帽层上方设置有栅电极,GaN帽层上方在漏电极和源电极之间设置SiN钝化层。1. A GaN HEMT based on a superlattice back barrier structure, characterized in that it includes, from bottom to top, a substrate, an AlN nucleation layer, a GaN buffer layer, an InGaN/GaN superlattice back barrier layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer and a GaN cap layer, wherein a drain electrode and a source electrode are respectively arranged at both ends above the GaN channel layer, a gate electrode is arranged above the GaN cap layer close to the source electrode, and a SiN passivation layer is arranged between the drain electrode and the source electrode above the GaN cap layer. 2.根据权利要求1所述的基于超晶格背势垒结构的GaN HEMT,其特征在于,衬底为Si、SiC、Al2O3中的一种;2. The GaN HEMT based on the superlattice back barrier structure according to claim 1, characterized in that the substrate is one of Si, SiC, and Al 2 O 3 ; AlN成核层厚度为5~1000 nm;The thickness of the AlN nucleation layer is 5~1000 nm; GaN缓冲层的厚度为0.1~20μm。The thickness of the GaN buffer layer is 0.1~20μm. 3.根据权利要求2所述的基于超晶格背势垒结构的GaN HEMT,其特征在于,InGaN/GaN超晶格背势垒层的In质量百分比为1%~40%。3. The GaN HEMT based on the superlattice back barrier structure according to claim 2, characterized in that the mass percentage of In in the InGaN/GaN superlattice back barrier layer is 1% to 40%. 4.根据权利要求3所述的基于超晶格背势垒结构的GaN HEMT,其特征在于,InGaN/GaN超晶格背势垒层的总厚度为5~500nm,其中InGaN层厚度为1~10nm,GaN层厚度为1~30nm。4. The GaN HEMT based on the superlattice back barrier structure according to claim 3, characterized in that the total thickness of the InGaN/GaN superlattice back barrier layer is 5-500 nm, wherein the thickness of the InGaN layer is 1-10 nm, and the thickness of the GaN layer is 1-30 nm. 5.根据权利要求4所述的基于超晶格背势垒结构的GaN HEMT,其特征在于,InGaN/GaN超晶格背势垒层的总厚度为30nm,其中InGaN层的厚度为1nm,GaN层的厚度为5nm,InGaN层和GaN层的循环周期为5。5. The GaN HEMT based on the superlattice back barrier structure according to claim 4, characterized in that the total thickness of the InGaN/GaN superlattice back barrier layer is 30 nm, wherein the thickness of the InGaN layer is 1 nm, the thickness of the GaN layer is 5 nm, and the cycle period of the InGaN layer and the GaN layer is 5. 6.根据权利要求5所述的基于超晶格背势垒结构的GaN HEMT,其特征在于,GaN沟道层的厚度为5~50 nm;6. The GaN HEMT based on the superlattice back barrier structure according to claim 5, characterized in that the thickness of the GaN channel layer is 5 to 50 nm; AlN插层的厚度为0.2~10 nm;The thickness of the AlN intercalation layer is 0.2~10 nm; AlGaN势垒层的Al质量百分比为5%~30%,AlGaN势垒层的厚度为5~40 nm。The Al mass percentage of the AlGaN barrier layer is 5% to 30%, and the thickness of the AlGaN barrier layer is 5 to 40 nm. 7.根据权利要求6所述的基于超晶格背势垒结构的GaN HEMT,其特征在于,GaN帽层的厚度为0~100 nm;7. The GaN HEMT based on the superlattice back barrier structure according to claim 6, characterized in that the thickness of the GaN cap layer is 0-100 nm; 漏电极和源电极的材料为Ti/Al/Ni/Au电极,栅电极的材料为Ni/Au电极;The materials of the drain electrode and the source electrode are Ti/Al/Ni/Au electrodes, and the material of the gate electrode is Ni/Au electrode; SiN钝化层的厚度为10~3000 nm。The thickness of the SiN passivation layer is 10~3000 nm. 8.一种权利要求7所述的基于超晶格背势垒结构的GaN HEMT的制备方法,其特征在于,包括如下步骤:8. A method for preparing a GaN HEMT based on a superlattice back barrier structure according to claim 7, characterized in that it comprises the following steps: S1:在衬底上依次外延生长AlN成核层、GaN缓冲层、InGaN/GaN超晶格背势垒层、GaN沟道层、AlN插层、AlGaN势垒层和GaN帽层;S1: epitaxially growing an AlN nucleation layer, a GaN buffer layer, an InGaN/GaN superlattice back barrier layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer and a GaN cap layer on a substrate in sequence; S2:通过ICP刻蚀去除漏电极和源电极下方的GaN帽层、AlGaN势垒层、AlN插层,直到GaN沟道层顶部,形成漏电极和源电极区域;S2: Remove the GaN cap layer, AlGaN barrier layer, and AlN intercalation layer under the drain electrode and the source electrode by ICP etching until the top of the GaN channel layer to form the drain electrode and the source electrode region; S3:在漏电极和源电极区域蒸镀金属Ti/Al/Ni/Au,退火形成欧姆接触;S3: evaporate metal Ti/Al/Ni/Au in the drain electrode and source electrode regions, and anneal to form ohmic contacts; S4:在GaN帽层上方栅电极区域蒸镀金属Ni/Au形成肖特基接触;S4: Vapor depositing metal Ni/Au in the gate electrode region above the GaN cap layer to form a Schottky contact; S5:在GaN帽层上方源电极与漏电极之间生长SiN钝化层。S5: growing a SiN passivation layer between the source electrode and the drain electrode above the GaN cap layer. 9.根据权利要求8所述的基于超晶格背势垒结构的GaN HEMT的制备方法,其特征在于,步骤S3中,蒸镀金属Ti/Al/Ni/Au的方法为电子束蒸发或磁控溅射技术,退火温度为700-1000℃,退火时间为20~600s。9. The method for preparing a GaN HEMT based on a superlattice back barrier structure according to claim 8, characterized in that in step S3, the method of evaporating metal Ti/Al/Ni/Au is electron beam evaporation or magnetron sputtering technology, the annealing temperature is 700-1000° C., and the annealing time is 20-600 s. 10.根据权利要求9所述的基于超晶格背势垒结构的GaN HEMT的制备方法,其特征在于,步骤S1中,外延生长方法为液相外延生长法、金属有机化学气相沉积法或分子束外延法;10. The method for preparing a GaN HEMT based on a superlattice back barrier structure according to claim 9, characterized in that in step S1, the epitaxial growth method is a liquid phase epitaxial growth method, a metal organic chemical vapor deposition method or a molecular beam epitaxy method; 步骤S5中,SiN钝化层的生长方式为低压力化学气相沉积法、等离子体增强化学沉积法或原子层沉积法。In step S5, the SiN passivation layer is grown by low pressure chemical vapor deposition, plasma enhanced chemical deposition or atomic layer deposition.
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