CN119446083A - A field sequential display pixel circuit - Google Patents
A field sequential display pixel circuit Download PDFInfo
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- CN119446083A CN119446083A CN202411721625.7A CN202411721625A CN119446083A CN 119446083 A CN119446083 A CN 119446083A CN 202411721625 A CN202411721625 A CN 202411721625A CN 119446083 A CN119446083 A CN 119446083A
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Abstract
本发明公开一种场序显示像素电路，包括呈多行和多列分布的多个像素单元；多条沿水平方向延伸的扫描信号线和多条沿竖直方向延伸的数据信号线；以及设置在外围电路的多个级联的GOA单元，每一级GOA单元分别与多条扫描信号线连接以输入扫描信号至每条扫描线。本发明达到的有益效果是：通过多级扫描线信号打开控制开关和多通道数据线写入，实现了刷新率的提升。
The present invention discloses a field sequential display pixel circuit, comprising a plurality of pixel units distributed in multiple rows and columns; a plurality of scanning signal lines extending in the horizontal direction and a plurality of data signal lines extending in the vertical direction; and a plurality of cascaded GOA units arranged in a peripheral circuit, wherein each level of GOA units is respectively connected to a plurality of scanning signal lines to input scanning signals to each scanning line. The present invention has the beneficial effect that the refresh rate is improved by opening a control switch and writing a multi-channel data line through a multi-level scanning line signal.
Description
Technical Field
The invention relates to the technical field of display, in particular to a field sequential display pixel circuit.
Background
The field sequential (or color sequential) display driving technology directly utilizes the color mixing of RGB three-color light sources through the human vision pause residual effect to achieve the full-color display effect. The color filter is not needed, so that the utilization rate of the light source is improved, and the power consumption of the light source is reduced. After all picture data are written, the backlight can be started after the liquid crystal is deflected to a stable state, otherwise, the phenomenon of picture confusion occurs, so that a large amount of time is reserved for the liquid crystal to deflect and then the backlight is lightened. This makes it difficult to achieve high luminance and high frequency display within an average time, while increasing the backlight luminance specification and lifetime requirements, and increasing costs.
In order to achieve a high refresh rate, the present invention provides a field sequential display pixel circuit.
Disclosure of Invention
The invention aims to provide a field sequential display pixel circuit which realizes high refresh rate.
The invention aims to realize a field sequential display pixel circuit by the following technical scheme, which comprises a plurality of pixel units distributed in a plurality of rows and a plurality of columns, wherein two adjacent pixel units in the same column have opposite polarities, and two adjacent pixel units in the same row have opposite polarities;
The display device comprises a pixel unit, a plurality of scanning signal lines extending along the horizontal direction, a plurality of data signal lines extending along the vertical direction and used for being connected with the pixel unit to input data signals to the pixel unit, and a plurality of data signal lines extending along the horizontal direction and used for being connected with the pixel unit to transmit driving signals to the pixel unit;
And a plurality of cascaded GOA units arranged on the peripheral circuit, wherein the GOA units are integrated gate driving units of the array substrate, the nth stage GOA units are used for outputting nth stage scanning signals, and each stage GOA unit is respectively connected with a plurality of scanning signal lines so as to input the scanning signals to pixel units of each row.
Further, when the nth stage GOA unit is connected to m scan signal lines, the pixel circuit is provided with m data signal lines;
The x-th data signal line is used for inputting data signals to pixel units in an mn- (m-x) row of an n-th GOA unit, x=1, 2.
Further, the pixel unit comprises a first transistor, a second transistor, a third transistor, a pre-storage capacitor, a holding capacitor and a pixel electrode;
The grid electrode of the first transistor is coupled to the scanning signal line, the second source-drain electrode of the first transistor is coupled to one end of the pre-storage capacitor and the first source-drain electrode of the second transistor, the other end of the pre-storage capacitor is coupled to the common signal line, the grid electrode of the second transistor is coupled to the transfer signal line, the second source-drain electrode of the second transistor is coupled to one end of the pixel electrode and one end of the holding capacitor, the other end of the pixel electrode and the other end of the holding capacitor are coupled to the common signal line, the first source-drain electrode of the third transistor is coupled to the second source-drain electrode of the second transistor, and the grid electrode of the third transistor is coupled to the reset signal line.
Further, when the nth-stage GOA unit controls any two rows of pixel units, the m data signal lines include a first data signal line and a second data signal line;
the first transistor of the pixel unit of the 2n-1 row controlled by the GOA unit of the nth stage receives a data signal of a first data signal line, and the second source drain electrode of the third transistor of the pixel unit of the 2n-1 row is coupled to a second data signal line;
the first source drain electrode of the first transistor of the pixel unit of the 2n row controlled by the GOA unit of the n-th stage is coupled to a second data signal line, the second source drain electrode of the third transistor of the pixel unit of the 2n row is coupled to the first data signal line, and the second data signal line inputs reset signals to the pixel unit of the 2n-1 row and the pixel unit of the 2n row.
Further, when the nth-stage GOA unit controls any three rows of pixel units, the plurality of data signal lines include a first data signal line, a second data signal line and a third data signal line;
The first transistor of the pixel unit of the 3n-2 th row controlled by the GOA unit of the nth stage receives a data signal of the first data signal line, and the second source drain electrode of the third transistor of the pixel unit of the 3n-2 th row is coupled to the third data signal line;
The first source and drain of the first transistor of the pixel unit of the 3n-1 th row controlled by the GOA unit of the nth stage are coupled to the second data signal line, and the second source and drain of the third transistor of the pixel unit of the 3n-1 th row are coupled to the first data signal line.
The first transistors of the pixel units of the 3n row controlled by the GOA unit of the n-th stage are coupled to a third data signal line, the second source drain electrodes of the third transistors of the pixel units of the 3n row are coupled to a third data signal line, and the third data signal inputs reset signals to the pixel units of the 3n-2 row, the 3n-1 row and the 3n row.
Further, the third data signal line may be replaced with a reset signal line and a transfer signal line, and the third data signal line may be replaced with a reset signal line or a transfer signal line.
Further, the nth row of pixel units and the n+1th row of pixel units are arranged in a mirror symmetry mode, and the nth row of pixel units and the n+1th row of pixel units are coupled to the same scanning signal line, the same transferring signal line and the same resetting signal line.
The invention has the advantages that:
The invention is provided with a multi-stage GOA unit and a plurality of data signal lines, wherein the GOA unit can simultaneously input scanning signals to a plurality of rows of scanning signal lines to drive a plurality of rows of pixel units, and simultaneously control the on-off of a plurality of first transistors through the scanning signal lines;
the data signal lines can be multiplexed into the reset signal lines or the transfer signal lines or the reset signal lines, and the data signal lines have multiplexing functions, so that the number of the signal lines is saved, and the aperture opening ratio of the display pixel circuit is improved;
The invention also provides a circuit, which comprises an n-th row of pixel units and an n+1-th row of pixel units, wherein the n-th row of pixel units and the n+1-th row of pixel units are arranged in a mirror symmetry mode and are coupled to the same scanning signal line, the same transferring signal line and the same resetting signal line, so that the number of a plurality of signal lines is saved, and the aperture opening ratio of the circuit is improved.
Drawings
FIG. 1 is a circuit diagram of a first embodiment of the present invention;
FIG. 2 is a circuit diagram of a first embodiment of the present invention;
FIG. 3 is a timing diagram of a first embodiment of the present invention;
FIG. 4 is a circuit diagram of a second embodiment of the present invention;
fig. 5 is a circuit diagram of a third embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.
It should be noted that, the azimuth or positional relationship indicated by "left", "right", etc. is based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship conventionally put in use of the inventive product, or the azimuth or positional relationship conventionally understood by those skilled in the art, such terms are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present invention.
It should be noted that, under the condition of no conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other.
Examples
The invention provides a field sequential display pixel circuit, which comprises a plurality of pixel units distributed in a plurality of rows and a plurality of columns, wherein two adjacent pixel units in the same column have the same polarity, and two adjacent pixel units in the same row have opposite polarities;
a plurality of Scan signal lines Scan extending in a horizontal direction, the plurality of Scan signal lines being connected to the pixel units to transmit driving signals to the pixel units, and a plurality of Data signal lines Data extending in a vertical direction, the plurality of Data signal lines Data being connected to the pixel units to input Data signals to the pixel units, the Data signal lines Data also inputting reset signals to the pixel units;
The Array substrate integrated Gate driving unit comprises a plurality of cascaded GOA units arranged in a peripheral circuit (non-display area), wherein 'GOA' in the GOA units is short for Gate On Array, each GOA unit is an Array substrate integrated Gate driving unit, each GOA unit is respectively connected with a plurality of scanning signal lines Scan to input scanning signals to each scanning signal line Scan, when the n-th GOA unit is connected with m scanning signal lines Scan, the pixel circuit is provided with m Data signal lines Data, the x-th Data signal line is used for inputting Data signals to the mn- (m-x) row pixel units driven by the n-th GOA unit, and x=1, 2. In some embodiments, referring to fig. 1, when the nth stage GOA unit controls any two rows of pixel units, the m Data signal lines include a first Data signal line Data1 and a second Data signal line Data2;
The first transistor T1 of the pixel unit of the 2n-1 th row controlled by the GOA unit of the nth stage receives a Data signal of the first Data signal line Data1, and the second source drain electrode of the third transistor T3 of the pixel unit of the 2n-1 th row is coupled to the second Data signal line Data2;
The first source and drain of the first transistor T1 of the pixel unit of the nth stage of GOA unit control of the nth stage are coupled to the second Data signal line Data2, and the second source and drain of the third transistor T3 of the pixel unit of the 2nth column are coupled to the first Data signal line Data1.
In still other embodiments, when the nth stage GOA unit is connected to the m Scan signal lines Scan, the nth stage GOA unit controls any m rows through the m Scan signal lines Scan, referring to fig. 2, when m=2, the nth stage GOA unit controls the pixel units of the first row and the pixel units of the third row, and the n+1th stage GOA unit controls the pixel units of the second row and the pixel units of the fourth row. With this embodiment, the selected control rows for each level of GOA units may be allocated as needed.
In some embodiments, the pixel unit includes a first transistor T1, a second transistor T2, a third transistor T3, a pre-storage capacitor Cs1, a holding capacitor Cs2, and a pixel electrode Clc;
the gate of the first transistor T1 is coupled to the Scan signal line Scan, the second source/drain of the first transistor T1 is coupled to one end of the pre-storage capacitor Cs1 and the first source/drain of the second transistor T2, the other end of the pre-storage capacitor Cs1 is coupled to the common signal line Com, the gate of the second transistor T2 is coupled to the transfer signal line Tran, the second source/drain of the second transistor T2 is coupled to one end of the pixel electrode Clc and one end of the holding capacitor Cs2, the other end of the pixel electrode Clc and the other end of the holding capacitor Cs2 are coupled to the common signal line Com, the first source/drain of the third transistor T3 is coupled to the second source/drain of the second transistor T2, and the gate of the third transistor T3 is coupled to the Reset signal line Reset.
In operation, referring to FIG. 3, during positive polarity frames, the n-th GOA circuit outputs a driving signal, and the Scan signal lines Scan of the pixel units of the 2n-1 row and the pixel units of the 2n row receive the driving signal, so that the first transistor T1 of each pixel unit is turned on, and at this time, the first Data signal line Data1 and the second Data signal line Data2 input Data signals to the pixel units of the 2n-1 row and the pixel units of the 2n row respectively;
In the Reset phase, the level of the Reset signal line Reset transitions to a high level, and the third transistor T3 is turned on. At this time, the second Data signal line Data2 inputs the reset signal vcom+vop_max so that the pixel cells of the 2n-1 th row and the holding capacitances Cs2 of the pixel cells of the 2 n-th row and the pixel electrode Clc are reset, and thus the second Data signal line Data2 is multiplexed as a signal line having a reset function, completing the reset of the pixel electrode Clc;
After the reset is completed, the level of the transfer signal line Tran jumps to a low level, the second transistors T2 of the pixel units of the 2n-1 row and the pixel units of the 2n row are turned on, and the respective pre-storage capacitors Cs1 transfer the data signals to the holding capacitors Cs2 and the pixel electrodes Clc, so that the pixel electrode points reach the preset potential.
In the negative frame, the first Data signal line Data1 and the second Data signal line Data2 write the Data signal of the negative frame, and in the reset stage, the second Data signal line Data2 inputs the second reset signal Vcom-vop_max, and the rest processes are the same as those in the positive frame.
The invention realizes the opening and closing of a plurality of rows of pixel units by arranging the multi-stage GOA units, simultaneously arranges a plurality of Data signal lines, and can write Data signals into the pixel units which are opened in a plurality of rows at the same time, thereby improving the refresh rate, and simultaneously, the Data signal lines Data can also be used as the signal lines for resetting the pixel electrodes Clc to output reset signals in the resetting stage, so that the holding capacitor Cs2 and the pixel electrodes Clc finish resetting, thereby saving the number of the signal lines, and improving the aperture ratio of a display area.
Examples
Referring to fig. 4, in some embodiments, when the nth stage GOA unit controls any three rows of pixel units, the plurality of Data signal lines includes a first Data signal line Data1, a second Data signal line Data2, and a third Data signal line Data3;
the first transistor T1 of the pixel unit of the 3n-2 th row controlled by the GOA unit of the nth stage receives a Data signal of the first Data signal line Data1, and the second source drain electrode of the third transistor T3 of the pixel unit of the 3n-2 th row is coupled to the third Data signal line Data3;
The first source and drain of the first transistor T1 of the pixel unit of the 3n-1 th row controlled by the GOA unit of the nth stage are coupled to the second Data signal line Data2, and the second source and drain of the third transistor T3 of the pixel unit of the 3n-1 th row are coupled to the first Data signal line Data1;
The first transistor T1 of the pixel unit of the 3 n-th row controlled by the GOA unit of the n-th stage is coupled to the third Data signal line Data3, and the second source-drain of the third transistor T3 of the pixel unit of the 3 n-th row is coupled to the third Data signal line Data3.
When the frame with positive polarity works, the nth stage GOA circuit outputs a driving signal, and the scanning signal lines Scan of the pixel units of the 3n-2 row, the pixel units of the 3n-1 row and the pixel units of the 3n row respectively receive the driving signal, so that the first transistor T1 of each pixel unit is opened, and at the moment, the first Data signal line Data1, the second Data signal line Data2 and the third Data signal line Data3 respectively input Data signals to the pixel units of the 3n-2 row, the pixel units of the 3n-1 row and the pixel units of the 3n row;
In the Reset phase, the level of the Reset signal line Reset transitions to a high level, and the third transistors T3 of the pixel units of three rows are turned on. At this time, the third Data signal line Data3 inputs the reset signal Vcom+Vop_max, so that the pixel units of the 3n-2 th row, the pixel units of the 3n-1 th row and the pixel units of the 3 n-th row are reset respectively, and the holding capacitor Cs2 and the pixel electrode Clc are reset respectively;
after the reset is completed, the level of the transfer signal line Tran jumps to a low level, the second transistors T2 of the pixel units of the 3n-2 th row, the pixel units of the 3n-1 th row and the pixel units of the 3 n-th row are turned on, and the respective pre-storage capacitors Cs1 transfer the data signals to the storage capacitors Cs2 and the pixel electrodes Clc so that the pixel electrode points reach the preset potential.
In the negative frame, the first Data signal line Data1, the second Data signal line Data2 and the third Data signal line Data3 write the Data signal of the negative frame, at this time, the third Data signal line Data3 inputs the second reset signal Vcom-vop_max in the reset stage, and the rest processes are the same as those in the positive frame. In this embodiment, the third Data signal line Data3 also outputs the reset signal, and increasing the number of Data signal lines Data increases the refresh rate of the circuit.
Examples
As shown in fig. 5, in some embodiments, the nth row of pixel units and the n+1th row of pixel units are disposed in a mirror symmetry manner, and the nth row of pixel units and the n+1th row of pixel units are coupled to the same Scan signal line Scan, the same transfer signal line Tran and the same Reset signal line Reset.
The upper and lower mirror image pixel units enable the pixel units to share the control signal lines, so that the signal lines are saved, and the aperture opening ratio of the circuit is improved.
The foregoing examples represent only preferred embodiments, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that variations and modifications could be made by those skilled in the art without departing from the scope of the invention.
Claims (7)
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| CN202411721625.7A CN119446083A (en) | 2024-11-28 | 2024-11-28 | A field sequential display pixel circuit |
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| CN202411721625.7A CN119446083A (en) | 2024-11-28 | 2024-11-28 | A field sequential display pixel circuit |
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