CN119440625A

CN119440625A - Operation method, device, computer equipment and storage medium of custom instruction code

Info

Publication number: CN119440625A
Application number: CN202510024999.1A
Authority: CN
Inventors: 胡振波; 彭剑英; 蔡骏; 吴黎明
Original assignee: Shin Lai Zhirong Semiconductor Technology Shanghai Co ltd
Current assignee: Shin Lai Zhirong Semiconductor Technology Shanghai Co ltd
Priority date: 2025-01-07
Filing date: 2025-01-07
Publication date: 2025-02-14

Abstract

The present application provides a method, device, computer equipment and storage medium for operating a custom instruction code, which is applied to the field of computer technology, and specifically includes: detecting whether to execute a preset operation, wherein the preset operation includes a data read/write traversal operation, a data comparison operation and a bit operation; when the preset operation needs to be executed, in the custom instruction code set, the custom instruction code corresponding to the preset operation is obtained, and the operation corresponding to the custom instruction code is a combination operation corresponding to a series of conventional instruction codes; and the operation corresponding to the custom instruction code is executed. This method can reduce the burden of the processor caused by multiple read operations and pre-decoding operations, and improve the operating efficiency of the processor. At the same time, since a custom instruction code can usually realize the functions of multiple conventional instruction codes, using a custom instruction code set can save code space.

Description

Operation method, device, computer equipment and storage medium of custom instruction code

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and apparatus for operating a custom instruction code, a computer device, and a storage medium.

Background

RISC-V is an open source instruction set architecture, when a processor based on RISC-V instruction set architecture needs to execute a certain operation, an instruction code corresponding to the operation is read in RISC-V instruction set in advance, then the instruction code is decoded to obtain execution information corresponding to the instruction code, and then the operation is executed based on the execution information.

In the prior art, each conventional instruction code in the RISC-V instruction set often corresponds to an operation. When multiple operations need to be performed, the processor often needs to read the corresponding instruction codes separately.

However, in some applications requiring multiple operations, the processor often reads multiple instruction codes sequentially and decodes each instruction code separately, and the multiple reading and decoding operations increase the burden of the processor, so that the operation efficiency of the processor is reduced.

Disclosure of Invention

The embodiment of the application provides a method, a device, a computer device and a storage medium for operating a custom instruction code, which can reduce the burden of a processor caused by multiple reading operations and decoding operations in the implementation of specific application requirements, and improve the operation efficiency of the processor.

In a first aspect of the embodiment of the present application, there is provided a method for operating a custom instruction code, including:

Detecting whether to execute preset operations, wherein the preset operations comprise data read/write traversal operation, data comparison operation and bit operation;

When the preset operation is required to be executed, acquiring a custom instruction code corresponding to the preset operation in a custom instruction code set, wherein the operation corresponding to the custom instruction code is a combination operation corresponding to a series of conventional instruction codes;

Executing the operation corresponding to the custom instruction code;

when the preset operation is a data reading traversing operation, the type of the first operand is a base address register, the type of the first operand is a base address indicated by the base address register, the type of the second operand is an immediate, and the execution of the operation corresponding to the self-defined instruction code comprises the steps of determining a target register according to a data bit corresponding to the target register in the self-defined instruction code, acquiring data to be loaded from the base address, loading the data to be loaded into the target register, obtaining a base address updating value according to the base address and the second operand, and updating the base address indicated by the base register based on the base address updating value;

When the preset operation is a data writing traversing operation, the type of the first operand is a base address register, the type of the first operand is a base address indicated by the base address register, the type of the second operand is a source register, the second operand is a value stored by the source register, and the executing the operation corresponding to the custom instruction code comprises the steps of obtaining a third operand in the custom instruction code, the type of the third operand is an immediate number, storing the second operand into the base address indicated by the base address register, obtaining a base address updating value according to the base address indicated by the base address register and the third operand, and updating the base address indicated by the base address register based on the base address updating value.

Optionally, the preset operation further includes a data read operation, when the preset operation is a data read operation, the index value of the base address register is GP, the first operand is an immediate, and the executing the operation corresponding to the custom instruction code includes:

determining a left shift number according to the number of bytes of the loaded data;

Based on the left shift number, performing left shift operation on the first operand to obtain a first operand after left shift;

Adding the first operand after the left shift and the base address indicated by the GP register to obtain a target address, wherein the GP register is determined based on an index value GP;

and acquiring data to be loaded from the target address, and loading the data to be loaded into the target register.

Optionally, when the preset operation is a data writing operation, when the index value of the base address register is GP, the first operand is a source register, the first operand is a value stored in the source register, the second operand is an immediate, and the executing the operation corresponding to the custom instruction code includes:

determining a left shift number according to the number of bytes of the stored data;

Performing left shift operation on the second operand based on the left shift number to obtain a second operand after left shift;

Adding the second operand after the left shift and the base address indicated by the GP register to obtain a target address, wherein the GP register is determined based on an index value GP;

The first operand is stored into the target address.

Optionally, when the preset operation is a data comparison operation, the first operand is of a type of a source register, the first operand is a value in the source register, the second operand is of a type of an immediate,

The executing the operation corresponding to the custom instruction code comprises the following steps:

acquiring a third operand in the custom instruction code, wherein the type of the third operand is an offset;

Comparing the first operand with the second operand to obtain a comparison result;

adding the current address of the custom instruction code and the third operand to obtain a preset target address;

when the comparison results are equal, skipping to a preset target address to acquire an instruction code;

And when the comparison result is unequal, acquiring the next instruction code of the custom instruction code.

Optionally, when the preset operation is a data comparison operation, the type of the first operand is an immediate, and the type of the second operand is an immediate;

determining a target register according to a data bit corresponding to the target register in the custom instruction code;

when the comparison result is smaller than or equal to the comparison result, writing 1 into the target register;

and when the comparison result is larger than the target register, writing 0 into the target register.

Optionally, when the preset operation is a data comparison operation, the first operand is a source register, the first operand is a value stored in the source register, the second operand is a source register, and the second operand is a value stored in the source register;

Acquiring a third operand in the custom instruction code, wherein the type of the third operand is an immediate;

adding the second operand and the preset value to obtain a sum of the second operand and the preset value;

Comparing the sum with the first operand;

When the two are not equal, jumping to a preset operation, and storing the sum into a source register;

And when the two codes are not equal, acquiring the next instruction code of the custom instruction code.

Optionally, when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate;

Determining a target register according to a data bit corresponding to the target register in the custom instruction code, and acquiring a third operand in the custom instruction code, wherein the type of the third operand is an immediate;

determining a start intercepting bit and an end intercepting bit according to the second operand and the third operand;

Intercepting the first operand according to the start intercepting bit and the end intercepting bit to obtain intercepted data;

performing unsigned bit expansion or sign bit expansion on the intercepted data to obtain expanded data;

And storing the extension data into the target register.

Acquiring data to be modified from the first operand according to a start bit and an end bit of the data to be modified;

Modifying the data to be modified to obtain modified data;

and storing the modified data into the target register.

Optionally, when the preset operation is a bit operation, the executing the operation corresponding to the custom instruction code includes:

Determining a target register according to a data bit corresponding to the target register in the custom instruction code, and acquiring a first operand in the custom instruction code, wherein the type of the first operand is a source register, and the first operand is a value in the source register;

counting the number of times that sign bits of the first operand continuously appear from the most significant bit of the first operand until the least significant bit of the first operand is ended, and obtaining statistical data;

and when the first operand is a preset value, writing the preset value into the target register, otherwise writing statistical data into the target register.

determining a preset data bit from the most significant bit of the source register;

And when the data of the preset data bit is a preset value, writing the preset value into the target register.

grouping the first operands according to the second operands to obtain grouped data;

According to the third operand, performing left shift and overturn operation on the grouped data to obtain operated data;

and storing the operated data into the target register.

Alternatively, when the preset operation is a bit operation,

The type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate;

Sign bit expansion is carried out on the second operand to obtain an expanded immediate;

multiplying the first operand by the extended immediate data to obtain a product result, and storing the product result into the target register.

In a second aspect of the embodiment of the present application, an operating device for customizing instruction codes is provided, including:

A detection unit configured to detect whether a preset operation is performed, the preset operation including a data read/write traversal operation, a data comparison operation, and a bit operation;

The acquisition unit is used for acquiring a custom instruction code corresponding to the preset operation in a custom instruction code set when the preset operation needs to be executed, wherein the operation corresponding to the custom instruction code is a series of combined operations corresponding to conventional instruction codes;

the execution unit is used for executing the operation corresponding to the custom instruction code;

When the preset operation is a data reading traversing operation, the type of the first operand is a base address register, the first operand is a base address indicated by the base address register, the type of the second operand is an immediate, and the execution unit is used for determining a target register according to data bits corresponding to the target register in the self-defined instruction code, acquiring data to be loaded from the base address, loading the data to be loaded into the target register, obtaining a base address updating value according to the base address and the second operand, and updating the base address indicated by the base register based on the base address updating value;

When the preset operation is a data writing traversing operation, the type of the first operand is a base address register, the first operand is a base address indicated by the base address register, the type of the second operand is a source register, the second operand is a value stored in the source register, the execution unit is used for acquiring a third operand in the self-defined instruction code, the type of the third operand is an immediate, storing the second operand into the base address indicated by the base address register, obtaining a base address updating value according to the base address indicated by the base address register and the third operand, and updating the base address indicated by the base address register based on the base address updating value.

Optionally, the preset operation further includes a data read operation, when the preset operation is the data read operation, the index value of the base address register is GP, the first operand is an immediate, and the execution unit is configured to:

Optionally, when the preset operation is a data writing operation, when the index value of the base register is GP, the first operand is a source register, the first operand is a value stored in the source register, the second operand is an immediate, and the execution unit is configured to:

The first operand is stored into the target address.

The execution unit is used for:

the execution unit is used for:

Comparing the sum with the first operand;

the execution unit is used for:

And storing the extension data into the target register.

the execution unit is used for:

Modifying the data to be modified to obtain modified data;

and storing the modified data into the target register.

Optionally, when the preset operation is a bit operation, the execution unit is configured to:

the execution unit is used for:

and storing the operated data into the target register.

Alternatively, when the preset operation is a bit operation,

the execution unit is used for:

In a third aspect of the embodiments of the present application there is provided a computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the steps of any of the methods described above when executing the computer program.

In a fourth aspect of embodiments of the present application, there is provided a computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor implements the steps of the method of any of the above.

In the application, some operations which can be combined and executed are found out in all a series of normal instruction code corresponding operations, and the custom instruction code is obtained by editing according to the combined operations. And detecting whether a preset operation is executed or not, and when the preset operation is required to be executed, acquiring a custom instruction code corresponding to the preset operation in a custom instruction code set, and executing the operation corresponding to the custom instruction code, wherein the preset operation comprises a data read/write traversal operation, a data comparison operation and a bit operation. Because the operation corresponding to the custom instruction code is a series of combined operations corresponding to the conventional instruction code, the processor can read the custom instruction code once without respectively reading the conventional instruction code corresponding to each operation, thereby reducing the times of reading instructions by the processor. In addition, the application pre-decodes the self-defined instruction codes once, so that the operation corresponding to the self-defined instruction codes can be executed, each conventional instruction code does not need to be pre-decoded in sequence like the prior art, and the pre-decoding operation of a processor is reduced. Therefore, for a self-defined instruction code, the application only needs to perform one-time reading and pre-decoding operation, so that the burden of the processor caused by multiple reading operations and pre-decoding operations can be reduced, and the running efficiency of the processor can be improved. Meanwhile, since one custom instruction code can generally realize the functions of a plurality of conventional instruction codes, the code space can be saved by using the custom instruction code set.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a flow chart of a method of operation of custom instruction codes according to one embodiment of the present application;

FIG. 2 is a schematic diagram of an instruction format according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an operating device with custom instruction codes according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a computer device according to an embodiment of the present application.

Detailed Description

For some small area, low power consumption, and low cost scene use oriented chips, their memory space is often limited. When it is desired to implement some more complex operations, it is often necessary to use more conventional instruction code combinations in the program code. This takes up more memory space and may result in the processor not being able to support more complex operations at the same time.

In the process of implementing the present application, the inventor finds that each conventional instruction code in the RISC-V instruction set corresponds to one operation, and in implementing some application requirements that need to perform multiple operations, the processor needs to sequentially read multiple instruction codes and perform decoding operation on each instruction code, where multiple reading operations and decoding operations increase the burden of the processor, so that the operation efficiency of the processor is reduced.

In view of the above problems, an embodiment of the present application provides a method for operating a custom instruction code, where a feasible operation combination of the custom instruction code is designed according to different requirements of multiple operations on a specific application scenario, and the operation combination of the custom instruction code is defined as different custom instruction codes. And detecting whether a preset operation is executed or not, and when the preset operation is required to be executed, acquiring a custom instruction code corresponding to the preset operation in a custom instruction code set, and executing the operation corresponding to the custom instruction code, wherein the preset operation comprises a data read/write traversal operation, a data comparison operation and a bit operation. Because the operation corresponding to each custom instruction code is a series of combined operations corresponding to the conventional instruction codes, the processor can read the custom instruction codes once without respectively reading the conventional instruction codes corresponding to each operation, and the frequency of reading instructions by the processor is reduced. In addition, the application pre-decodes the self-defined instruction codes once, and the processor can acquire the operation information corresponding to the self-defined instruction codes, so that each conventional instruction code does not need to be pre-decoded in sequence like the prior art, and the pre-decoding operation of the processor is reduced. Therefore, for a self-defined instruction code, the application only needs to perform one-time reading and pre-decoding operation, can reduce the burden of the processor caused by multiple reading operations and pre-decoding operations, and improves the running efficiency of the processor. Meanwhile, as one custom instruction code can usually complete the combination operation corresponding to a series of conventional instruction codes, compared with the storage of a series of conventional instruction codes, the code space can be further saved by only storing the custom instruction codes.

The embodiment of the application provides an operation method of a custom instruction code, an execution body of the method is a processor in any equipment, the burden of the processor caused by multiple reading operations and decoding operations can be reduced, the operation efficiency of the processor is improved, and meanwhile, the custom instruction code can generally realize the functions of multiple conventional instruction codes, so that the code space can be saved by using a custom instruction code set. Referring specifically to fig. 1, comprising:

step 101, detecting whether to execute a preset operation.

The preset operation comprises a data read/write traversal operation, a data comparison operation and a bit operation.

Before executing this step, the embodiment of the present application finds some operations that can be executed in combination among all the series of normal instruction code corresponding operations, edits and obtains custom instruction codes according to these combination operations, and composes these custom instruction codes into a custom set.

As the instruction format described later, the instruction format I-type which supports the destination register (rd), the source register (rs 1) and the immediate (imm) at the same time is defined by the RISC-V authority, and the specific format is shown in fig. 2, wherein the total bit width of the instruction format I-type is 32 bits, the rs1 field in the I-type instruction format is used to store the index value of the source register, the index value is used to find the source register, and the rd field is used to store the index value of the destination register, and the index value is used to find the destination register. These two index fields each need to occupy 5 bit. The imm field is used to store an immediate, the opcode field is used to store an opcode, and the funct field is used to store a function field.

As in fig. 2, for some data traversal operations, single-byte signed data is loaded from an address specified in source register rs1 into destination register rd, and the data in source register rs1 is updated to the sum of the data in source register rs1 and the data in imm, named custom instruction code xl. The single-byte unsigned data is loaded from the address appointed in the source register rs1 into the target register rd, the data in the source register rs1 is updated to be the sum of the data in the source register rs1 and the data in the imm, and the custom instruction code is named as xl. Loading the double-byte signed data from the address appointed in the source register rs1 into the target register rd, updating the data in the source register rs1 into the sum of the data in the source register rs1 and the data in the imm, and naming the custom instruction code as xl.lhrd, imm (rs 1). The double-byte unsigned data is loaded from the address appointed in the source register rs1 into the target register rd, the data in the source register rs1 is updated to be the sum of the data in the source register rs1 and the data in the imm, and the custom instruction code is named as xl.lhu rd, imm (rs 1). Four bytes of signed data are loaded from an address specified in the source register rs1 into the target register rd, the data in the source register rs1 is updated to be the sum of the data in the source register rs1 and the data in imm, and the custom instruction code is named xl.lw rd, imm (rs 1). Four bytes of unsigned data are loaded from the address specified in the source register rs1 into the target register rd, the data in the source register rs1 is updated to be the sum of the data in the source register rs1 and the data in imm, and the custom instruction code is named as xl.

In addition, in the above operation instruction format, the bit width of the immediate is 12 bit, and in the case of word alignment (the lowest 2bit of imm is fixed to 0), the addressing range is-8192 to 8192, so that in order to meet the requirement of a larger addressing range in some cases, the index value of the source register rs1 of the custom instruction code xl.lgp.wu instruction can be fixed to GP in hardware, so that the rs1 domain is not specified in the instruction code, and thus 5 bit widths can be saved to expand the bit width occupied by the immediate domain. Thus, the immediate (imm) bit width of such instructions may be as high as 17 bit, enabling a larger memory addressing range with word alignment (the lowest 2 bits of imm fixed to 0).

Further, when the index value of the source register rs1 is fixed as GP, a target address can be obtained according to the base address indicated in the GP register and the immediate value, which comprises the specific steps of determining a left shift number according to the byte number of the loaded data, performing left shift operation on the immediate value based on the left shift number to obtain an immediate value after left shift, and adding the immediate value after left shift and the base address indicated by the GP register to obtain the target address. And according to the base address indicated in the GP register and the immediate, obtaining a target address, loading single-byte unsigned data from the target address into a target register rd, and naming the custom instruction code as xl. And obtaining a target address according to the base address indicated in the GP register and the immediate. And loading single-byte signed data from the target address into the target register rd, and naming the custom instruction code as xl.lgp.b rd, imm. And obtaining a target address according to the base address indicated in the GP register and the immediate. And loading the double-byte signed data from the target address into the target register rd, and naming the custom instruction code as xl.lgp.h rd, imm. And obtaining a target address according to the base address indicated in the GP register and the immediate. And loading the double-byte unsigned data from the target address into the target register rd, and naming the custom instruction code as xl. And obtaining a target address according to the base address indicated in the GP register and the immediate. And four bytes of signed data are loaded from the target address into the target register rd, and the custom instruction code is named as xl.lgp.w rd, imm. And obtaining a target address according to the base address indicated in the GP register and the immediate. And four bytes of unsigned data are loaded from the target address into the target register rd, and the custom instruction code is named as xl. And obtaining a target address according to the base address indicated in the GP register and the immediate. And the eight bytes signed data are loaded from the target address to the target register rd, and the custom instruction code is named as xl.

In the above instruction format, an rs2 field may be further included, where the rs2 field may be used to store an index of a source register, may be used to store an immediate, and may be set according to actual needs. When the rs2 field is used to store the index of the source register, the single byte data in the source register rs2 is stored to the base address in the source register rs1, the data in rs1 is updated to be the sum of the data in rs1 and the data in imm, and the custom instruction code is named as xl.sb rs2, imm (rs 1). The double-byte data in the source register rs2 is stored on a base address in the source register rs1, the data in the rs1 is updated to be the sum of the data in the rs1 and the data in the imm, and the custom instruction code is named as xl.sh rs2, imm (rs 1). Four bytes of data in the source register rs2 are stored to a base address in the source register rs1, the data in the rs1 is updated to be the sum of the data in the rs1 and the data in imm, and the custom instruction code is named as xl. Eight bytes of data in a source register rs2 are stored to a base address in a source register rs1, the data in rs1 is updated to be the sum of the data in rs1 and the data in imm, and a custom instruction code is named as xl.sd rs2, imm (rs 1).

And storing the single byte data in the source register rs2 to a base address in the source register rs1, updating the data in the rs1 to be the sum of the data in the rs1 and the data in imm, storing, and naming the custom instruction code as xl.sb rs2 and imm (rs 1). And storing the double-byte data in the source register rs2 to a base address in the source register rs1, updating the data in the rs1 to be the sum of the data in the rs1 and the data in imm, storing, and naming the custom instruction code as xl.fshRs 2, imm (rs 1). Four bytes of data in a source register rs2 are stored on a base address in a source register rs1, the data in the rs1 is updated to be the sum of the data in the rs1 and the data in imm, the sum is stored, and a custom instruction code is named as xl.sw rs2, imm (rs 1). Eight bytes of data in a source register rs2 are stored on a base address in a source register rs1, the data in the rs1 is updated to be the sum of the data in the rs1 and the data in imm, the sum is stored, and a custom instruction code is named as xl.

Step 102, when a preset operation needs to be executed, acquiring a custom instruction code corresponding to the preset operation from a custom instruction code set.

The operation corresponding to the custom instruction code is a series of combined operations corresponding to the conventional instruction code. The combination operation corresponding to the series of normal instruction codes may be an operation sequentially executed by the processor, for example, a data judging operation and a subsequent data processing operation in the data comparison process, and a data loading operation and a subsequent address updating operation in the data read traversal process.

Because the corresponding relation between the self-defined instruction codes and the micro-instruction combinations is predefined in the processor, when the processor performs the pre-decoding operation on the self-defined instruction codes, the corresponding micro-instruction combinations can be obtained based on the corresponding relation and the self-defined instruction codes to be decoded. After that, when a plurality of micro instructions are obtained, the processor can output to the execution unit according to the micro instructions. In this step, the obtaining unit implements the similar operations described above, and further implements the pre-decoding splitting operation on the custom instruction code.

Step 103, executing the operation corresponding to the custom instruction code.

After the execution unit receives the plurality of micro instructions sent from the acquisition unit. The execution unit decodes the micro instructions to obtain information such as instruction type, instruction operand, destination register, etc. The operands are then input into corresponding execution subunits for execution, depending on the instruction type. After the instruction execution is completed, the processor writes the operation result back to the destination register for the instruction to be written back. In this step, the execution unit performs the similar operations, and further performs decoding, execution, and write-back operations on the microinstructions split by the custom instruction code.

Further, when the preset operation is a data reading traversing operation, the type of the first operand is a base address register, the type of the first operand is a base address indicated by the base address register, the type of the second operand is an immediate, and the specific steps of executing the operation corresponding to the custom instruction code are that the target register is determined according to the data bit corresponding to the target register in the custom instruction code, the data to be loaded is obtained from the base address, the data to be loaded is loaded into the target register, the base address updating value is obtained according to the base address and the second operand, and the base address indicated by the base register is updated based on the base address updating value.

The first operand is based on a value stored in a register corresponding to the rs1 domain, and the second operand is data in the imm domain.

In this step, when the preset operation is a data read traversal operation, the custom instruction code at least includes a target register, a first operand, and a second operand. When the custom instruction code is executed, a corresponding target register is found according to data bits corresponding to the target register in the custom instruction code, data to be loaded is obtained from a base address, the data to be loaded is loaded into the target register to realize data reading, a base address updating value is obtained according to the base address and a second operand, and the base address is updated based on the base address updating value to read next data based on the updated base address.

For example, a single byte of signed data is loaded from the base address, with the base address updated to the sum of the base address and the second operand. One byte of unsigned data is loaded from the base address while the base address is updated to the sum of the base address and the second operand. Double bytes of signed data are loaded from the base address, with the base address updated to the sum of the base address and the second operand. Double bytes of unsigned data are loaded from the base address while the base address is updated to the sum of the base address and the second operand. Four bytes of signed data are loaded from the base address, with the base address updated to the sum of the base address and the second operand. Four bytes of unsigned data are loaded from the base address while the base address is updated to the sum of the base address and the second operand. 8 bytes of signed data are loaded from the base address, with the base address updated to the sum of the base address and the second operand. 8 bytes of unsigned data are loaded from the base address while the base address is updated to the sum of the base address and the second operand.

Further, when the preset operation is a data writing traversing operation, the first operand is a base address register, the first operand is a base address indicated by the base address register, the second operand is a source register, and the second operand is a value stored in the source register. Based on the operation, the specific steps of executing the operation corresponding to the custom instruction code comprise the steps of obtaining a third operand in the custom instruction code, wherein the type of the third operand is an immediate number, storing the second operand into a base address indicated by the base address register, obtaining a base address updating value according to the base address indicated by the base address register and the third operand, and updating the base address indicated by the base address register based on the base address updating value.

The first operand is a value stored in a register corresponding to the rs1 domain, the second operand is a value stored in a register corresponding to the rs2 domain, and the third operand is data in the imm domain.

The address updating step in this step is similar to the address updating step described above, and is not limited thereto.

For example, 2 bytes of signed data are read from the second operand, saved to the base address, and the base address is updated to the base address and the second operand and saved to the base address register. The 2 bytes of unsigned data are read from the second operand, saved to the base address, and the base address is updated to the base address and the second operand and saved to the base address register. 4 bytes of signed data are read from the second operand, saved to the base address, updated to the sum of the base address and the second operand, and saved to the base address register. 4 bytes of unsigned data are read from the second operand, saved to the base address, and the base address is updated to the sum of the base address and the second operand and saved to the base address register. 8 bytes of signed data are read from the second operand, saved to the base address, updated to the sum of the base address and the second operand, and saved to the base address register. The 8 bytes of unsigned data are read from the second operand, saved to the base address, and the base address is updated to the sum of the base address and the second operand and saved to the base address register.

Wherein the base address register may be a floating point register.

Further, when the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value in the source register, the type of the second operand is an immediate value, the specific step of executing the operation corresponding to the custom instruction code is to obtain a third operand in the custom instruction code, the type of the third operand is an offset, compare the first operand with the second operand to obtain a comparison result, add the current address of the custom instruction code and the third operand to obtain a preset target address, jump to the preset target address to obtain the instruction code when the comparison result is equal, and obtain the next instruction code of the custom instruction code when the comparison result is unequal.

Wherein the first operand is a value stored based on a register corresponding to the rs1 field. Wherein the imm field is divided into cimm fields and an offset field in the instruction code for storing the immediate. The second operand is data in the cimm field in the instruction code. The third operand is data in the offset domain.

For example, rs1 is compared with cimm immediate, if equal, jump to the current PC+offset for execution, and if unequal, get the next instruction code to be executed.

Further, when the preset operation is a data comparison operation, the type of the first operand is an immediate and the type of the second operand is an immediate, the execution step of executing the operation corresponding to the custom instruction code is to determine a target register according to the data bit corresponding to the target register in the custom instruction code, compare the first operand with the second operand to obtain a comparison result, write 1 into the target register when the comparison result is less than or equal to the comparison result, and write 0 into the target register when the comparison result is greater than the comparison result.

Wherein two imm fields are provided in the instruction code for storing the immediate. The second operand is data in the imm1 field in the instruction code. The third operand is data in the imm2 field.

For example, rs1 and rs2 are compared, if rs1 is less than or equal to rs2 (signed comparison), 1 is written into the target register, otherwise 0 is written. And comparing rs1 with rs2, if rs1 is less than or equal to rs2 (unsigned comparison), writing 1 into a target register, and otherwise writing 0.

Further, when the preset operation is a data comparison operation, the first operand is a source register, the first operand is a value stored in the source register, the second operand is a value stored in the source register, the execution step of executing the operation corresponding to the custom instruction code is that a third operand is obtained in the custom instruction code, the type of the third operand is an immediate number, the second operand and the preset value are added to obtain a sum of the second operand and the preset value, the sum is compared with the first operand, when the second operand and the preset value are not equal, the sum is skipped to the preset operation and stored in the first source register, and when the second operand and the first operand are not equal, the next instruction of the custom instruction code is obtained.

The first operand is a value stored in a register corresponding to the rs1 domain, the first operand is a value stored in a register corresponding to the rs2 domain, and the third operand is data in an imm domain in the instruction code.

Further, when the preset operation is bit operation, the type of the first operand is a source register, the first operand is a value in the source register, the type of the second operand is an immediate value, the specific step of executing the operation corresponding to the custom instruction code is that the target register is determined according to the data bit corresponding to the target register in the custom instruction code, a third operand is obtained in the custom instruction code, the type of the third operand is an immediate value, the start intercepting bit and the end intercepting bit are determined according to the second operand and the third operand, the first operand is intercepted according to the start intercepting bit and the end intercepting bit to obtain intercepting data, the unsigned bit extension or the signed bit extension is carried out on the intercepting data to obtain extension data, and the extension data is stored in the target register.

Wherein the first operand is a value stored based on a register corresponding to the rs1 field. Wherein the imm field is divided into uimm field and uimm field in instruction code for storing immediate data. The second operand is data in the uimm field in the instruction code. The third operand is data in the uimm field.

For example, data between [ uimm < 3+ > uimm < 2 > -1:uimm2] is intercepted from rs1, and then sign bit expansion is performed, and the sign bit expansion is saved to rd. And intercepting data between [ rs2[9:5] +rs2[4:0] -1:rs 2[4:0] ] from rs1, then performing sign bit expansion, and storing the sign bit expansion to rd. And intercepting data between [ uimm < 3+ > uimm < 2 > -1:uimm2] from rs1, performing unsigned bit expansion, and storing the data to rd. And intercepting data between [ rs2[9:5] +rs2[4:0] -1:rs 2[4:0] from rs1, then performing unsigned bit expansion, and storing the data to rd.

Further, when the preset operation is a bit operation, the type of a first operand is a source register, the type of the first operand is a value in the source register, the type of the second operand is an immediate value, the specific execution step of executing the operation corresponding to the custom instruction code is that the target register is determined according to a data bit corresponding to the target register in the custom instruction code, the data to be modified is obtained from the first operand according to a start bit and an end bit of the data to be modified, the data to be modified is modified, the modified data is obtained, and the modified data is stored in the target register.

For example, when the custom instruction codes xl.insert rd, rs1, uimm, uimm2 are executed, the data of the [ td: bd ] bit in rd is modified to rs1[ ts:0], and the data of other bits in rd are unchanged. When the custom instruction codes xl.bset rd, rs1, uimm3 and uimm2 are executed, the [ uimm3+ uimm2: uimm2] bit data in rs is changed into all 1, and the rest parts are unchanged and stored in rd. When the custom instruction codes xl, bsetr rd, rs1 and rs2 are executed, data of [ rs2[9:5] +rs2[4:0 ]: rs2[4:0] bits in rs1 are modified into all 1, the rest parts are kept unchanged, and the rest parts are stored in rd. When the custom instruction codes xl.bclr rd, rs1, uimm, uimm2 are executed, the bit data of [ uimm3+ uimm2: uimm2] in rs is changed to be all 0, and the rest parts are kept unchanged and stored in rd. When the custom instruction code xl.bclrr rd, rs1, rs2 is executed, the data of [ rs2[9:5] +rs2[4:0 ]: rs2[4:0] bit in rs1 is modified to be all 0, the rest part is kept unchanged, and the rest part is stored in the rd.

Further, when the preset operation is a bit operation, the executing step of executing the operation corresponding to the custom instruction code includes determining a target register according to a data bit corresponding to the target register in the custom instruction code, acquiring a first operand in the custom instruction code, wherein the first operand is a source register, the first operand is a value in the source register, counting the number of times of continuous occurrence of sign bits from the most significant bit of the first operand to the end of the least significant bit of the first operand to obtain statistical data, and writing the preset value into the target register when the first operand is a preset value, otherwise writing the statistical data into the target register.

Wherein the first operand is a value stored based on a register corresponding to the rs1 field.

For example, when the custom instruction code xl.clb rd, rs1 is executed, the number of consecutive bits of rs1 from the MSB is counted. If rs1 is 0, then 0 is returned to rd, otherwise the number is returned to rd.

Further, when the preset operation is a bit operation, the executing the operation corresponding to the custom instruction code includes determining the target register according to a data bit corresponding to the target register in the custom instruction code, acquiring a first operand in the custom instruction code, wherein the first operand is of a source register type, the first operand is a value in the source register, determining a preset data bit from the most significant bit of the source register, and writing a preset value into the target register when the data of the preset data bit is a preset value.

For example, when the custom instruction codes xl.fl1 rd, rs1 are executed, the position of the last bit1 in rs1 is found from the MSB. If rs1 is 0, rd is equal to 32 or 64. When the custom instruction code xl.ff1rd, rs1 is executed, the position of the first bit1 in rs1 is found out from MSB. If rs1 is 0, rd is equal to 32 or 64. For example, when the custom instruction codes xl.fl0 rd, rs1 are executed, the position of the last bit0 in rs1 is found from the MSB. If rs1 is 0, rd is equal to 32 or 64. For example, when the custom instruction codes xl.ff0 rd, rs1 are executed, the position of the first bit0 in rs1 is found from the MSB. If rs1 is 0, rd is equal to 32 or 64. Where MSB is the most significant bit.

Further, when the preset operation is a bit operation, the type of a first operand is a source register, the first operand is a value in the source register, the type of a second operand is an immediate value, the executing step of executing the operation corresponding to the custom instruction code according to the first operand and the second operand is to determine the target register according to a data bit corresponding to a target register in the custom instruction code, acquire a third operand in the custom instruction code, the type of the third operand is an immediate value, perform grouping operation on the first operand according to the second operand to obtain grouped data, and perform left shift and overturn operation on the grouped data according to the third operand to obtain the operated data. And storing the operated data into the target register.

For example, when the custom instruction codes xl.bitrev rd, rs1, uimm, uimm2 are executed, the bit flipping operation is performed on rs1 according to the specified mode and packet. Wherein uimm designates packet information, uimm2 designates the left shift number before flip.

Optionally, when the preset operation is a bit operation, the type of a first operand is a source register, the first operand is a value in the source register, the type of a second operand is an immediate value, and the executing step of executing the operation corresponding to the custom instruction code according to the first operand and the second operand is to determine a target register according to a data bit corresponding to the target register in the custom instruction code, sign bit expansion is performed on the second operand to obtain an expanded immediate value, multiplication is performed on the first operand and the expanded immediate value to obtain a product result, and the product result is stored in the target register.

The first operand is a value stored on a register corresponding to the rs1 domain, and the second operand is data in the imm domain.

For example, when the custom instruction codes xl.muli rd, rs1, imm are executed, rs1 is multiplied by imm after sign bit expansion and saved to rd.

Optionally, the preset operation further includes a data reading operation, when the preset operation is the data reading operation, the index value of the base address register is GP, the first operand is an immediate number, and the operation corresponding to the custom instruction code is executed, including determining a left shift number according to the byte number of the loaded data, performing the left shift operation on the first operand based on the left shift number to obtain a first operand after the left shift, adding the first operand after the left shift and the base address indicated by the GP register to obtain a target address, wherein the GP register is determined based on the index value GP, acquiring the data to be loaded from the target address, and loading the data to be loaded into the target register.

Wherein the first operand is data in the imm field.

When the number of bytes of the loaded data is 1 byte of unsigned data, the left shift number is determined to be 0. When the number of bytes of the loaded data is 2 bytes of unsigned data, the left shift number is determined to be 1. When the number of bytes of the loaded data is 2 bytes of signed data, the left shift number is determined to be 1. When the number of bytes of the loaded data is 4 bytes of unsigned data, the left shift number is determined to be 2. When the number of bytes of the loaded data is 4 bytes of signed data, the left shift number is determined to be 2. When the number of bytes of the loaded data is 8 bytes of unsigned data, the left shift number is determined to be 3. When the number of bytes of the loaded data is 8 bytes of signed data, the left shift number is determined to be 3.

It should be noted that, in the process of performing a left shift operation on the first operand based on the left shift number to obtain a first operand after the left shift, a data bit to be operated may also be selected from the first operand, and then, based on the left shift number, the left shift operation is performed on the data bit to be operated to obtain the first operand after the left shift. For example, the data bits corresponding to the 0 th bit to the 15 th bit in the first operand are used as the data bits to be operated. And taking the data bits corresponding to the 3 rd bit to the 16 th bit in the first operand as the data bits to be operated.

After the first operand after the left shift is determined, adding the first operand after the left shift and the base address indicated by the GP register to obtain a target address, acquiring data to be loaded from the target address, and loading the data to be loaded into the target register.

Optionally, the preset operation further includes a data writing operation, when the preset operation is the data writing operation, the index value of the base address register is GP, the first operand is the source register, the first operand is the value stored in the source register, the second operand is the immediate, the specific steps of executing the operation corresponding to the custom instruction code are that the left shift bit number is determined according to the byte number of the stored data, the left shift operation is performed on the second operand based on the left shift bit number to obtain the second operand after the left shift, the base address indicated by the GP register and the second operand after the left shift are added to obtain the target address, the GP register is determined based on the index value GP, and the first operand is stored in the target address.

The first operand is a value stored on a register corresponding to the rs2 domain, and the second operand is data in the imm domain.

The moving operation involved in this step is similar to the moving operation described above, and is not described in detail herein.

It should be understood that, although the steps in the flowchart are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of other steps or other steps.

Referring to fig. 3, an embodiment of the present application provides an operation device for customizing instruction codes, which includes:

A detection unit 301 for detecting whether to perform a preset operation including a data read/write traversal operation, a data comparison operation, and a bit operation;

The obtaining unit 302 is configured to obtain, in a custom instruction code set, a custom instruction code corresponding to the preset operation when the preset operation needs to be performed, where an operation corresponding to the custom instruction code is a combination operation corresponding to a series of conventional instruction codes;

an execution unit 303, configured to execute an operation corresponding to the custom instruction code;

When the preset operation is a data read traversing operation, the type of the first operand is a base address register, the first operand is a base address indicated by the base address register, the type of the second operand is an immediate, and the execution unit 303 is configured to determine a target register according to a data bit corresponding to the target register in the custom instruction code, obtain data to be loaded from the base address, load the data to be loaded into the target register, obtain a base address update value according to the base address and the second operand, and update the base address indicated by the base register based on the base address update value;

When the preset operation is a data writing traversing operation, the type of the first operand is a base address register, the first operand is a base address indicated by the base address register, the type of the second operand is a source register, the second operand is a value stored in the source register, the execution unit 303 is configured to obtain a third operand in the custom instruction code, the type of the third operand is an immediate, store the second operand into the base address indicated by the base address register, obtain a base address update value according to the base address indicated by the base address register and the third operand, and update the base address indicated by the base address register based on the base address update value.

Optionally, the preset operation further includes a data read operation, when the preset operation is a data read operation, the index value of the base address register is GP, the type of the first operand is an immediate, and the execution unit 303 is configured to:

Optionally, when the preset operation is a data writing operation, when the index value of the base register is GP, the first operand is a source register, the first operand is a value stored in the source register, the second operand is an immediate, and the execution unit 303 is configured to:

The first operand is stored into the target address.

The execution unit 303 is configured to:

the execution unit 303 is configured to:

Comparing the sum with the first operand;

the execution unit 303 is configured to:

And storing the extension data into the target register.

the execution unit 303 is configured to:

Modifying the data to be modified to obtain modified data;

and storing the modified data into the target register.

Optionally, when the preset operation is a bit operation, the execution unit 303 is configured to:

the execution unit 303 is configured to:

and storing the operated data into the target register.

Alternatively, when the preset operation is a bit operation,

the execution unit 303 is configured to:

For specific limitation of the operation device of the custom instruction code, reference may be made to the limitation of the operation method of the custom instruction code hereinabove, and the description thereof will not be repeated here. The above-mentioned individual modules in the operating device of the custom instruction code may be implemented in whole or in part by software, hardware, or a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 4. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is for storing data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of operating custom instruction code as described above. Comprising a memory storing a computer program and a processor implementing any of the steps of the method of operation of the custom instruction code described above when the processor executes the computer program.

In one embodiment, a computer readable storage medium is provided having a computer program stored thereon which, when executed by a processor, performs any of the steps in the method of operation of the instruction custom instruction code described above.

It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product of operation of the custom instruction code. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products for operating custom instruction codes according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A method for operating a custom instruction code, comprising:

Detecting whether to execute a preset operation, wherein the preset operation includes a data read/write traversal operation, a data comparison operation, and a bit operation;

When the preset operation needs to be executed, the custom instruction code corresponding to the preset operation is obtained from the custom instruction code set, and the operation corresponding to the custom instruction code is a combination of operations corresponding to a series of conventional instruction codes;

Execute the operation corresponding to the custom instruction code;

Wherein, when the preset operation is a data read traversal operation, the type of the first operand is a base register, the first operand is a base address indicated by the base register, and the type of the second operand is an immediate number, and the operation corresponding to the execution of the custom instruction code includes: determining the target register according to the data bit corresponding to the target register in the custom instruction code; obtaining the data to be loaded from the base address, and loading the data to be loaded into the target register; obtaining a base address update value according to the base address and the second operand; and updating the base address indicated by the base register based on the base address update value;

When the preset operation is a data write traversal operation, the type of the first operand is a base register, the first operand is the base address indicated by the base register, the type of the second operand is a source register, the second operand is the value stored in the source register, and the execution of the operation corresponding to the custom instruction code includes: obtaining the third operand in the custom instruction code, the type of the third operand is an immediate number; storing the second operand in the base address indicated by the base register; obtaining a base address update value according to the base address indicated by the base register and the third operand; and updating the base address indicated by the base register based on the base address update value.

2. The method according to claim 1, wherein the preset operation further comprises a data read operation, when the preset operation is a data read operation, the index value of the base register is GP, the type of the first operand is an immediate number, and the operation corresponding to the execution of the custom instruction code comprises:

Determine the number of left shifts according to the number of bytes of the loaded data;

Based on the number of left shifts, perform a left shift operation on the first operand to obtain a first operand after left shift;

Adding the first operand after the left shift and a base address indicated by a GP register to obtain a target address, wherein the GP register is determined based on an index value GP;

The data to be loaded is obtained from the target address, and the data to be loaded is loaded into the target register.

3. The method according to claim 1, characterized in that the preset operation also includes a data write operation. When the preset operation is a data write operation, when the index value of the base register is GP, the type of the first operand is a source register, the first operand is a value stored in the source register, and the type of the second operand is an immediate number, the operation corresponding to the execution of the custom instruction code includes:

Determine the number of left shifts according to the number of bytes of the stored data;

Based on the number of left shifts, performing a left shift operation on the second operand to obtain a left-shifted second operand;

Adding the second operand after the left shift and the base address indicated by the GP register to obtain a target address, the GP register being determined based on the index value GP;

The first operand is stored in the target address.

4. The method according to claim 1, characterized in that when the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value,

The operation corresponding to executing the custom instruction code includes:

Obtain a third operand in the custom instruction code, where the type of the third operand is an offset;

When the comparison result is equal, jump to the preset target address to obtain the instruction code;

When the comparison result is unequal, the next instruction code of the custom instruction code is obtained.

5. The method according to claim 1, characterized in that when the preset operation is a data comparison operation, the type of the first operand is an immediate number, and the type of the second operand is an immediate number;

The operation corresponding to executing the custom instruction code includes:

Determine the target register according to the data bit corresponding to the target register in the custom instruction code;

When the comparison result is less than or equal to, writing 1 into the target register;

When the comparison result is greater than, 0 is written into the target register.

6. The method according to claim 1, characterized in that when the preset operation is a data comparison operation, the type of the first operand is a source register, the first operand is a value stored in the source register, the type of the second operand is a source register, and the second operand is a value stored in the source register;

The operation corresponding to executing the custom instruction code includes:

In the custom instruction code, a third operand is obtained, wherein the type of the third operand is an immediate number;

Adding the second operand and the preset value to obtain a sum of the two;

comparing the sum to the first operand;

When the two are not equal, jump to the preset operation and save the sum in the source register;

When the two are not equal, the next instruction code of the custom instruction code is obtained.

7. The method according to claim 1, characterized in that when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value;

The operation corresponding to executing the custom instruction code includes:

Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a third operand in the custom instruction code, and the type of the third operand is an immediate number;

Determine a start interception position and an end interception position according to the second operand and the third operand;

According to the start interception bit and the end interception bit, intercepting the first operand to obtain intercepted data;

Performing unsigned bit extension or signed bit extension on the intercepted data to obtain extended data;

The extended data is stored in the target register.

8. The method according to claim 1, characterized in that when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value;

The operation corresponding to executing the custom instruction code includes:

Obtain the data to be modified from the first operand according to the start bit and the end bit of the data to be modified;

Modifying the data to be modified to obtain modified data;

The modified data is stored in the target register.

9. The method according to claim 1, wherein when the preset operation is a bit operation, executing the operation corresponding to the custom instruction code comprises:

Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a first operand in the custom instruction code, the type of the first operand is a source register, and the first operand is a value in the source register;

Starting from the most significant bit of the first operand and ending with the least significant bit of the first operand, counting the number of times the sign bit appears consecutively to obtain statistical data;

When the first operand is a preset value, the preset value is written into the target register; otherwise, statistical data is written into the target register.

10. The method according to claim 1, wherein when the preset operation is a bit operation, executing the operation corresponding to the custom instruction code comprises:

Determine the target register according to the data bit corresponding to the target register in the custom instruction code, obtain a first operand in the custom instruction code, wherein the type of the first operand is a source register, and the first operand is a value in the source register;

Starting from the most significant bit of the source register, determining a preset data bit;

When the data of the preset data bit is a preset value, the preset value is written into the target register.

11. The method according to claim 1, characterized in that when the preset operation is a bit operation, the type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value;

The operation corresponding to executing the custom instruction code includes:

Determine the target register according to the data bit corresponding to the target register in the custom instruction code, and obtain a third operand in the custom instruction code, where the type of the third operand is an immediate number;

According to the second operand, performing a grouping operation on the first operand to obtain grouped data;

According to the third operand, performing left shift and flip operations on the grouped data to obtain operated data;

The post-operation data is stored in the target register.

12. The method according to claim 1, characterized in that when the preset operation is a bit operation,

The type of the first operand is a source register, the first operand is a value in the source register, and the type of the second operand is an immediate value;

The operation corresponding to executing the custom instruction code includes:

Performing sign bit extension on the second operand to obtain an extended immediate value;

The first operand and the extended immediate number are multiplied to obtain a product result, and the product result is saved in the target register.

13. An operating device for a user-defined instruction code, comprising:

A detection unit, used to detect whether to perform a preset operation, wherein the preset operation includes a data read/write traversal operation, a data comparison operation, and a bit operation;

An acquisition unit, used for acquiring, when the preset operation needs to be executed, a custom instruction code corresponding to the preset operation in a custom instruction code set, wherein the operation corresponding to the custom instruction code is a combination of operations corresponding to a series of conventional instruction codes;

An execution unit is used to execute the operation corresponding to the custom instruction code, wherein, when the preset operation is a data read traversal operation, the type of the first operand is a base register, the first operand is a base address indicated by the base register, and the type of the second operand is an immediate number, and the execution of the operation corresponding to the custom instruction code includes: determining the target register according to the data bit corresponding to the target register in the custom instruction code; obtaining the data to be loaded from the base address, and loading the data to be loaded into the target register; obtaining a base address update value according to the base address and the second operand; and performing an operation on the base address indicated by the base register based on the base address update value. Update; when the preset operation is a data write traversal operation, the type of the first operand is a base register, the first operand is the base address indicated by the base register, the type of the second operand is a source register, the second operand is the value stored in the source register, and the operation corresponding to the execution of the custom instruction code includes: obtaining the third operand in the custom instruction code, the type of the third operand is an immediate number; storing the second operand in the base address indicated by the base register; obtaining a base address update value according to the base address indicated by the base register and the third operand; and updating the base address indicated by the base register based on the base address update value.

14. A computer device, comprising: a memory and a processor, wherein the memory stores a computer program, wherein the processor implements the steps of the method according to any one of claims 1 to 12 when executing the computer program.

15. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 12 are implemented.