CN119440226A - Low power consumption interrupt processing method and electronic device thereof - Google Patents

Abstract

The invention provides a low-power consumption interrupt processing method and electronic equipment thereof. The low-power-consumption interrupt processing method comprises the steps of running an ultra-low-power-consumption framework through a coprocessor, wherein the ultra-low-power-consumption framework comprises an interrupt alignment and active set, a memory prediction monitor and a task dynamic migration monitor, enabling the coprocessor to be awakened based on the aligned interrupt to execute all expired low-power-consumption functions, enabling an application processor to be awakened based on the awakening of the coprocessor, running the memory prediction monitor to predict the next time point of accessing global memory by a memory access monitor and a memory protection unit, determining whether to shut down the global memory through the memory access monitor, and enabling the task dynamic migration monitor to select one of the global memory or the local memory to access according to task load and running frequency.

Description

Low-power consumption interrupt processing method and electronic equipment thereof

Technical Field

The present invention relates generally to an electronic device. And more particularly, to an electronic device with an ultra-low power frame and an interrupt and task processing method.

Background

A normally open domain coprocessor may take over low-power functions of the system such as voice wake-up monitoring, position tracking, motion detection, cameras, etc. As a first wake-up source, a normally-on coprocessor can respond to various user behaviors with very low power consumption. By coprocessor processing, it is decided whether to wake the application processor to inform the application to continue with subsequent processing. In most cases, the coprocessor can handle many wake operations without notifying the application processor, thereby reducing power consumption.

External interrupt or timer interrupt methods are typically used to wake up the coprocessor from an idle state to an active state. After the coprocessor wakes up, it wakes up the corresponding task to perform subsequent sampling and low power functions in the interrupt service routine. However, waking up the coprocessor discretely causes the coprocessor to wake up frequently, thereby increasing power consumption.

If the coprocessor determines that the application processor needs to be awakened, the application processor will also be discretely activated for subsequent operations, thereby increasing the power consumption of the application processor.

Disclosure of Invention

The following disclosure is illustrative only and is not meant to be limiting in any way. In addition to the illustrative aspects, embodiments, and features, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. That is, the following disclosure is provided to introduce concepts, advantages, and benefits that are novel and non-obvious technical advantages described herein. Alternatively, but not all, embodiments are described in further detail below. Thus, the following disclosure is not intended to be exhaustive or to limit the scope of the claimed subject matter to the precise form disclosed.

One embodiment of the present invention provides an electronic device having an ultra-low power frame. The electronic device with an ultra-low power frame further includes a coprocessor, an application processor, a memory protection unit, a memory access monitor, a local memory, and a plurality of global memories. The coprocessor runs an ultra low power frame. The ultra-low power frame includes interrupt alignment and active set, memory prediction monitor, task live migration monitor. Interrupt alignment and active set execution by the coprocessor. The interrupt alignment and active set aligns the plurality of interrupts such that the coprocessor performs all expired low power functions based on the aligned interrupts being awakened and the application processor is aligned to wake based on the co-processor's wake. The memory prediction monitor is executed by the memory protection unit and the memory access monitor. The memory prediction monitor predicts the next point in time to access the global memory and determines whether to shutdown the global memory via the memory access monitor. The task live migration monitor is executed by the coprocessor. The task dynamic migration monitor selects a global memory or a local memory to access according to the task load and the operation frequency.

According to the electronic device, when the coprocessor first accesses the global memory, the memory protection unit sends an interrupt to the coprocessor to open the global memory. When the coprocessor does not access the global memory for a predetermined time, the memory access monitor is electrically connected to the memory protection unit and sends an interrupt to the coprocessor to shut down the global memory.

The electronic device further comprises an interrupt controller. An interrupt controller is electrically connected between the memory access monitor and the coprocessor and bypasses interrupts from the memory protection unit or the memory access monitor to the coprocessor.

According to the above electronic device, the global memory includes a Dynamic Random Access Memory (DRAM) and a global static random access memory (global static random access memory SRAM).

According to the electronic device, the local memory comprises a local static random access memory (local static random-access memory, SRAM for short).

According to the above electronic device, the interrupt includes an external interrupt and a timer interrupt.

According to the electronic device described above, the coprocessor generates the timer wheel by classifying the timer interrupts into a plurality of timer vectors according to the trigger frequency, thereby aligning the timer interrupts from the heartbeat timer. The timer wheel includes timer vectors that sequentially correspond to different trigger frequencies. The coprocessor further aligns the plurality of interrupts by selecting a recently expired timer vector, triggering an interrupt in the timer vector to perform a corresponding task, and triggering an interrupt in a subsequent timer vector in the timer wheel.

According to the electronic device described above, the coprocessor generates the timer wheel by aligning external interrupts from the inertial processing unit into the timer vector according to the trigger frequency of the timer interrupts and the external interrupts.

According to the electronic device described above, the coprocessor aligns the plurality of interrupts by reducing noise to calibrate the trigger frequency of external interrupts in the timer vector.

According to the above electronic device, the noise includes white noise, temperature drift, other interrupts with different trigger frequencies, and interrupt handling errors from the inertial processing unit.

According to the electronic device described above, the co-processor uses a Local statistical filter (Local STATISTIC FILTER) or a kalman filter (KALMAN FILTER) to reduce noise.

According to the above electronic device, the memory access monitor includes a timeout counter. When the memory access monitor determines that there is access to the global memory through the memory protection unit, the memory access monitor resets the count value of the timeout counter.

According to the above electronic device, when the memory access monitor determines that there is no access to the global memory through the memory protection unit, the memory access monitor decrements the count value of the timeout counter by one.

According to the electronic device, when the count value of the timeout counter is equal to zero, the memory access monitor sends an interrupt to the coprocessor to shut down the global memory.

According to the electronic device, when the memory protection unit determines that the coprocessor accesses the global memory for the first time, the coprocessor starts the memory access monitor.

According to the electronic device, after the memory access monitor sends an interrupt to the coprocessor to shut down the global memory, the coprocessor shuts down the memory access monitor.

According to the electronic device described above, the memory access monitor comprises a state machine. When the memory protection unit determines that the coprocessor is first accessing global memory, the coprocessor sets the state machine to an enabled state so that the memory access monitor is turned on.

According to the above electronic device, after the memory access monitor sends an interrupt to the coprocessor to shut down the global memory, the coprocessor sets the state machine to a disabled state so that the memory access monitor shuts down.

According to the electronic device, when the coprocessor first accesses the global memory, the memory protection unit sends an interrupt to the coprocessor to open the global memory. When the coprocessor does not access the global memory for a predetermined time, the memory access monitor sends an interrupt to the coprocessor to shut down the global memory.

The embodiment of the invention also provides a low-power consumption interrupt processing method. The method is applied to an electronic device having a local memory, a global memory, a coprocessor, a memory access monitor, and a memory protection monitor. The method comprises the following steps. The ultra low power frame is run by the coprocessor. The ultra low power frame includes interrupt alignment and active set, memory prediction monitor and task live migration monitor. The interrupt alignment and active set aligns the plurality of interrupts such that the coprocessor performs all expired low power functions based on the aligned interrupts being awakened and the application processor is aligned to wake based on the co-processor's wake. The memory prediction monitor operates to predict a next point in time when the memory access monitor and the memory protection unit access the global memory and determine whether to shutdown the global memory via the memory access monitor. The task dynamic migration monitor selects a global memory or a local memory to access according to the task load and the operation frequency.

Drawings

The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. It should be understood that the figures are not necessarily drawn to scale. Because some components may be shown disproportionately to the size in an actual implementation for clarity of illustration of the concepts of the present disclosure.

Fig. 1 shows a schematic diagram of an electronic device 110 according to some embodiments of the invention.

FIG. 2 shows a schematic diagram of a normally open domain 130, a global Static Random Access Memory (SRAM) 146, and a Dynamic Random Access Memory (DRAM) 148 in an electronic device 110, according to some embodiments of the invention.

Fig. 3 shows a schematic diagram of a low power timer 300 and an inertial processing unit 302 in the co-processor 100 of fig. 1 according to an embodiment of the invention.

Fig. 4 shows a schematic diagram of interrupts from a low power timer 300 and an inertial processing unit 302 according to an embodiment of the invention.

Fig. 5A-5D show schematic diagrams of noise in an interrupt according to an embodiment of the invention.

FIG. 6A is a schematic diagram of the memory access monitor 102 of FIG. 1 according to an embodiment of the invention.

Fig. 6B shows a schematic diagram of the state machine 602 in fig. 6A, according to an embodiment of the invention.

FIG. 7 illustrates a flow chart of operations by the coprocessor 100 of FIG. 1 to determine whether to shut down the global SRAM 146 or DRAM 148 based on interrupts, according to an embodiment of the present invention.

FIG. 8 illustrates a schematic diagram of the operation of the coprocessor 100 of FIG. 1 at a next point in time to turn on the global SRAM 146 or DRAM 148 according to interrupt prediction, in accordance with an embodiment of the present invention.

FIG. 9 illustrates a schematic diagram of the operation of selectively accessing either the local SRAM 108 or the global SRAM 146 or the DRAM 148 according to the task load and the operating frequency according to an embodiment of the present invention.

FIG. 10 shows a schematic diagram of the normally open domain 130, SRAM 146, and DRAM 148 in the electronic device 110 of FIG. 1, in accordance with an embodiment of the present invention.

FIG. 11 shows a flow chart of a low power interrupt handling method according to an embodiment of the invention.

Detailed Description

Certain terms are used throughout the description and claims to refer to particular components. Those of skill in the art will appreciate that a hardware manufacturer may refer to the same element by different names. The specification and claims do not identify differences in names as a way of distinguishing between elements, but rather differences in functions of the elements are used as a criterion for distinguishing. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" as used herein includes any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

Fig. 1 shows a schematic diagram of an electronic device 110 according to an embodiment of the invention. As shown in fig. 1, the electronic device 110 includes a system-on-chip (SoC) 150, a DRAM 148, an audio device 152, a location information device 154, a camera 156, and a sensor 158. In some embodiments, the electronic device 110 may be a tablet, a notebook, a smart phone, or a wearable device, but the invention is not limited thereto. The SoC 150 includes an application processor 140 having a plurality of central processing units, e.g., CPU0, CPU1, CPU2.SoC 150 also includes global bus 142, DRAM controller 144, global SRAM 146, and always on domain 130. In some embodiments, application processor 140 is electrically connected to global bus 142. Global bus 142 is electrically connected to DRAM controller 144, global SRAM 146, audio device 152, location information device 154, camera 156, and sensor 158.DRAM controller 144 is electrically connected to DRAM 148.

In the always-on domain 130 of the SoC 150, the electronic device 110 includes a coprocessor 100, a memory access monitor 102, a memory protection unit 104, a local SRAM 108, and a local bus 112. Coprocessor 100 is electrically connected to local bus 112. The local bus 112 is electrically connected to the global bus 142, the memory access monitor 102, the memory protection unit 104, and the local SRAM 108. In some embodiments, the co-processor 100 executes the audio software 114 to process interrupts of the audio device 152. Coprocessor 100 executes location information software 116 to process interrupts for location information device 154. Coprocessor 100 executes camera software 118 to process interrupts for camera 156. Coprocessor 100 executes sensor software 122 to handle interrupts for sensor 158. Coprocessor 100 also executes other software 124 to handle interrupts for other devices.

In some embodiments, coprocessor 100 runs an ultra low power frame 120. The ultra low power framework 120 includes interrupt alignment and active set, memory prediction monitor, and task live migration monitor. The interrupt alignment and active set aligns multiple interrupts such that the coprocessor 100 wakes up based on the aligned interrupts to perform all expired low power functions and the application processor 140 wakes up based on the wake-up of the coprocessor 100. The memory protection unit 104 and the memory access monitor 102 run a memory prediction monitor to predict when to access the next point in time of the global SRAM 146 or DRAM 148 and determine whether to shut down the global SRAM 146 or DRAM 148 by the memory access monitor 102. The task live migration monitor selects to access one of the global SRAM 146, DRAM 148, or local SRAM 108 depending on the load and operating frequency of the task performed by the coprocessor 100. The memory access monitor 102 is electrically connected to the global SRAM 146, DRAM 148, and coprocessor 100. When global SRAM 146 or DRAM 148 is first accessed, memory protection unit 104 sends an interrupt to coprocessor 100. The memory access monitor 102 also sends an interrupt to the coprocessor 100 when the global SRAM 146 or DRAM 148 is not accessed for a predetermined period of time.

In some embodiments, the coprocessor 100 aligns external interrupts with timer interrupts to avoid frequent waking up of the coprocessor 100. The coprocessor 100 is capable of performing all expired low power functions at one time, so the present invention can reserve more idle time or sleep time for the coprocessor 100 to save power consumption, and at the same time, the present invention can wake up the application processor 140 in an aligned manner. In some embodiments, the coprocessor 100 predicts the next time of use of the global SRAM 146 and DRAM 148 and determines whether to turn off the global SRAM 146 or DRAM 148 by the memory access monitor 102 according to an ultra low power frame to save power consumption. In some embodiments, coprocessor 100 selects one of global SRAM 146, DRAM 148, or local SRAM 108 to access to optimize power consumption based on task load and operating frequency.

Fig. 2 shows a schematic diagram of a normally open domain 130, a global Static Random Access Memory (SRAM) 146, and a Dynamic Random Access Memory (DRAM) 148 in the electronic device 110 of fig. 1, in accordance with an embodiment of the present invention. As shown in FIG. 2, always on domain 130 includes coprocessor 100, memory access monitor 102, memory protection unit 104, local SRAM 108, global SRAM 146, DRAM 148, interrupt controller 200, L1 instruction cache 202, L1 data cache 204, and L2 cache 206. The L1 instruction cache 202 and the L1 data cache 204 are electrically connected between the coprocessor 100 and the L2 cache 206. The L2 cache is electrically connected to the local SRAM 108, global SRAM 146, and DRAM 148. In some embodiments, when the coprocessor 100 first accesses the global SRAM 146 or DRAM 148, the memory protection unit 104 sends an interrupt to the coprocessor 100 through the interrupt controller 200 to turn on the global SRAM 146 or DRAM 148. In some embodiments, when the coprocessor 100 does not access the global SRAM 146 or the DRAM 148 for a predetermined period of time, the memory access monitor 102 sends an interrupt to the coprocessor 100 through the interrupt controller 200 to shut down the global SRAM 146 or the DRAM 148. The interrupt controller 200 is electrically connected between the memory access monitor 102 and the co-processor 100. Interrupt controller 200 bypasses interrupts from memory protection unit 104 or memory access monitor 102 to coprocessor 100.

Fig. 3 shows a schematic diagram of a low power timer 300 and an inertial processing unit 302 in the co-processor 100 of fig. 1 according to an embodiment of the invention. Interrupts include external interrupts and timer interrupts. In some embodiments, the audio software 114, the location information software 116, the camera software 118, and the sensor software 122 generate timer interrupts, and the timer interrupts are received by the co-processor 100. The inertial processing unit 302 generates an external interrupt and the external interrupt is received by the coprocessor 100. In some embodiments, coprocessor 100 classifies interrupts (including external interrupts and timer interrupts) into a plurality of timer vectors according to the trigger frequency of the interrupts to generate timer wheel 304. The timer wheel 304 sequentially includes timer vectors corresponding to different trigger frequencies. For example, as shown in FIG. 3, the timer vector 310 may correspond to a trigger frequency of 200 Hz. The timer vector 312 may correspond to a trigger frequency of 100 Hz. The timer vector 314 may correspond to a trigger frequency of 50 Hz. The timer vector 316 may correspond to a trigger frequency of 40 Hz. The timer vector 318 may correspond to a trigger frequency of 20 Hz. The timer vector 320 may correspond to a trigger frequency of 10 Hz. Timer vector 322 may correspond to a trigger frequency of 5Hz

As shown in fig. 3, timer vector 310 may include an interrupt from low power timer 332 and an interrupt from low power timer 334. The timer vector 314 may include interrupts from the low power timer 336 and interrupts from the low power timer 338. The timer vector 318 may include an interrupt from the low power timer 340 and an interrupt from the low power timer 342. In some embodiments, the low power timers 332, 334, 336, 338, 340, and 342 may be configured by the audio software 114, the location information software 116, the camera software 118, and the sensor software 122. Fig. 3 also shows an index array 306 to represent timer vectors 310, 312, 314, 316, 318, 320, and 322. FIG. 3 also shows a list array 308 to represent low power timers 332, 334, 336, 338, 340, and 342.

The coprocessor 100 then selects the latest expired one of the timer vectors 310, 312, 314, 316, 318, 320 or 322. Coprocessor 100 triggers an interrupt in the timer vector 310, 312, 314, 316, 318, 320, or 322 to perform the corresponding task. The co-processor 100 triggers an interrupt in a subsequent timer vector in the timer wheel 304. For example, assume that there are users in timer vector 310 and timer vector 314. For example, at 10 milliseconds, timer vectors 310 and 314 are triggered. At 15 milliseconds, the timer vector 310 is triggered. At 20 milliseconds, the timer vector 310 is triggered. At 25 milliseconds, the timer vector 310 is triggered. At 30 milliseconds, timer vectors 310 and 314 are triggered. The trigger source that triggers the timer wheel 304 may be a heartbeat timer or an inertial processing unit 302. Assuming that the operating frequency of the inertial processing unit is 200Hz, there is a user of the low power timer 332 in the timer vector 310. There is a user of the low power timer 336 in the timer vector 314. Since 200Hz is an integer multiple of the trigger frequency of timer vectors 310 and 314, the heartbeat timer or inertial processing unit 302 is switched to inertial processing unit 302 as the trigger source. For example, at 10 milliseconds, the inertia processing unit 302, the timer vector 310, and the timer vector 314 are triggered. At 15 milliseconds, the inertial processing unit and timer vector 310 are triggered. At 20 milliseconds, the inertia processing unit 302 and the timer vector 310 are triggered. At 25 milliseconds, the inertia processing unit 302 and the timer vector 310 are triggered. At 30 milliseconds, the inertia processing unit 302, the timer vector 310, and the timer vector 314 are triggered. Accordingly, the coprocessor 100 wakes up to perform the expired low-power function. That is, interrupts of the audio software 114, the positional information software 116, the camera software 118, the sensor software 122, and the inertial processing unit 302 are aligned.

Fig. 4 shows a schematic diagram of an interrupt of a low power timer 300 and an inertial processing unit 302 according to an embodiment of the invention. As shown in fig. 4, the frequency y (n) is the trigger frequency of the interruption of the inertia processing unit 302 at the current point of time. The frequency y (n-1) is the trigger frequency of the interruption of the inertia processing unit 302 at the last point of time. The frequency x (n) is the trigger frequency of the interrupt of the low power consumption timer 300 at the current point of time. The frequency x (n-1) is the trigger frequency of the interrupt of the low power consumption timer 300 at the last point of time. The frequency z (n) is the error frequency between the frequency y (n) and the frequency x (n-1). As shown in FIG. 4, frequency x (n), frequency x (n-1), frequency y (n), and frequency y (n-1) may be near 50Hz.

Specifically, the co-processor 100 executes the ultra-low power frame 120 to generate observer, state, and error analysis equations and uses the observer, state, and error analysis equations to calibrate the frequency of the inertial processing unit 302.

The observer equation is shown below.

X(n)=[x(n)y(n)z(n)]^T

E(n)=X(n)-X(n-1)

E(0)=[ΔTΔT0]^T

X (n) is a matrix, wherein the matrix elements consist of a frequency X (n), a frequency y (n) and a frequency z (n). E (n) is an error matrix derived from the difference between matrix X (n) and matrix X (n-1). Δt is a predetermined period defined by the user, for example, 0.02 seconds (50 Hz in fig. 4).

The equation of state is shown below.

x(n)=x(n-1)+y(n)-y(n-1)

y(n)=y(n-1)+T(t)

z(n)=y(n)-x(n-1)

T (T) is the actual trigger period of the interrupt of the inertia processing unit 302.

The error analysis equation is shown below.

T(t)=AT+α(t)+B(t)+y(t)+δ(t)

Alpha (t) is white noise. Beta (t) is the temperature drift. Gamma (t) is other interrupts from the inertial processing unit 302 with different trigger frequencies. Delta (t) is the interrupt handling error of coprocessor 100.

Fig. 5A-5D show schematic diagrams of interrupt noise according to embodiments of the invention. Fig. 5A shows white noise α (t) and temperature drift β (t). In some embodiments, the white noise α (t) is determined by the hardware structure of the inertial processing unit 302. The white noise α (t) and the temperature drift β (t) can be reduced by an algorithm. Fig. 5B shows other interrupts γ (t) from the inertial processing unit 302 with different trigger frequencies. In some embodiments, other interrupts γ (t) may include a data ready interrupt (DATA READY interrupt, DRI for short), but the invention is not limited thereto. Fig. 5C shows an example of the interrupt handling error δ (t). After the coprocessor receives a Data Ready Interrupt (DRI), the coprocessor 100 may delay processing for a period of time. The delay time may be equal to ISR-DRI. One example of an interrupt handling error delta (t) may be eliminated by a hardware latch. Fig. 5D shows another example of the interrupt handling error δ (t). The coprocessor 100 shuts down long interrupts, resulting in the loss of some interrupt from the inertial processing unit 302. This error can be eliminated by an algorithm.

In some embodiments, the co-processor 100 reduces noise using a local statistical filter or a kalman filter. For example, when the coprocessor 100 removes noise through the local statistical filter, the coprocessor 100 executes the ultra-low power frame 120 to generate state equations, boundaries of absolute error equations, local statistical filters, and prediction equations.

The equation of state is shown below.

y(n)=y(n-1)+AT(n-1)

AT(n)=y(n)-y(n-1)

The frequency y (n) is the trigger frequency of the interruption from the inertial processing unit 302 at the current point in time. The frequency y (n-1) is the trigger frequency of the interrupt from the inertial processing unit 302 at the last point in time. The frequency error DeltaT (n) is the frequency difference between frequency y (n) and frequency y (n-1).

The boundaries of the absolute error equation are shown below.

The local statistical filter is shown below.

The prediction equation is shown below.

In some embodiments, the co-processor 100 calculates the average trigger frequency by the bounds of the absolute error equation and the local statistical filterAnd average trigger frequencyAverage frequency error betweenThe co-processor 100 removes other interrupts γ (t) and interrupt handling errors δ (t) by the limits of the absolute error equation and white noise a (t) and temperature drift β (t) by the local statistical filter. In obtaining the average frequency errorThe coprocessor 100 then predicts the trigger frequency x (n) of the interrupt from the low power timer 300 at the next point in time to start the local SRAM 146 or DRAM 148 depending on the interrupt.

When the coprocessor 100 reduces noise through the kalman filter, the coprocessor 100 executes an ultra low power frame 120 to generate state equations, kalman filters, and prediction equations.

The equation of state is shown below.

y(n)=y(n-1)+ΔT(n-1)+Q_γ

ΔT(n)=ΔT(n-1)+Q_ΔT

z(n)=y(n)+R

Z_n＝HX_n+R,(Z_n＝[z]_n,H=[1 0])

The kalman filter is shown below.

The prediction equation is shown below.

x(n)=x(n-1)+ΔT(n)

Coprocessor 100 modifies matrix Q and matrix R to calculate average frequency error Δt (n). After the average frequency error Δt (n) is obtained, the coprocessor 100 predicts the interrupt trigger frequency x (n) of the low power timer 300 at the next time point according to the interrupt to turn on the local SRAM 146 or the DRAM 148.

FIG. 6A is a schematic diagram of the memory access monitor 102 of FIG. 1 according to an embodiment of the invention. Fig. 6B shows a schematic diagram of the state machine 602 of fig. 6A, according to an embodiment of the invention. As shown in fig. 6A and 6B, the memory access monitor 102 includes a timeout counter 600 and a state machine 602. When the memory protection unit 104 determines that the coprocessor 100 first accesses the global SRAM 146 or DRAM 148, the coprocessor 100 sets the state machine 602 to an enabled state (step S1) to turn on the memory access monitor 102. When the memory access monitor 102 determines through the memory protection unit 104 that the global SRAM 146 or DRAM 148 is not accessed, the memory access monitor 102 decrements the count value of the timeout counter 600 by one. When the count value of the timeout counter 600 is equal to zero (step S3), the state machine 602 receives a timeout message from the timeout counter so that the memory access monitor 102 sends an interrupt to the coprocessor 100 to turn off the global SRAM 146 or the DRAM 148. In some embodiments, after the memory access monitor 102 sends an interrupt to the coprocessor 100 to turn off the global SRAM 146 or DRAM 148, the coprocessor 100 sets the state machine 602 to a disabled state (step S2) in order to turn off the memory access monitor 102.

FIG. 7 illustrates a flowchart of the operation of the coprocessor 100 of FIG. 1 in determining whether to shut down the global SRAM 146 or DRAM 148 based on interrupts, in accordance with an embodiment of the present invention. As shown in fig. 7, the coprocessor starts operation (step S700). In step S702, the coprocessor 100 determines that the global SRAM 146 or DRAM 148 is first accessed by the memory protection unit 104, and the coprocessor 100 turns on the memory access monitor 102 in step S704. In step S706, the coprocessor 100 determines whether the global SRAM 146 or the DRAM 148 is accessed through the memory protection unit 104. If the answer in step S708 is affirmative, the memory access monitor 102 resets the timeout counter 600, and the coprocessor 100 executes step S706 again. If the answer in step S708 is negative, the memory access monitor 102 decrements the count value of the timeout counter 600 by one in step S710. In step S712, the memory access monitor 102 determines whether the count value of the timeout counter 600 is equal to zero.

If the answer in step S712 is negative, the coprocessor 100 executes step S706 again. If the answer in step S712 is affirmative, the memory access monitor 102 sends an interrupt to the coprocessor 100 in step S714. After receiving the interrupt from the memory access monitor 102, the coprocessor 100 turns off the global SRAM 146 or DRAM 148 in step S716. After the memory access monitor 102 sends an interrupt to the coprocessor 100to turn off the global SRAM 146 or DRAM 148, the coprocessor 100 sets the state machine 602 to a disabled state to turn off the memory access monitor 102 in step S718.

FIG. 8 illustrates a schematic diagram of the operation of the coprocessor 100 of FIG. 1 to turn on the global SRAM 146 or DRAM 148 at a next point in time based on interrupt prediction, in accordance with an embodiment of the present invention. As shown in fig. 8, coprocessor 100 performs memory access monitor timeout control 800 to predict the next point in time. In some embodiments, the coprocessor 100 predicts the next point in time to turn on the global SRAM 146 or DRAM 148. Because turning on the DRAM 148 and global SRAM 146 requires some time, to achieve better performance, the coprocessor 100 executes an idle frame 812 and scheduler run queue 804 to predict when the next task starts. A timer is used to wake up the coprocessor 100 to turn on the DRAM 148 or global SRAM 146.

In some embodiments, the coprocessor 100 predicts the next point in time to turn off the global SRAM 146 or DRAM 148. To achieve better power consumption, the count value of timeout counter 600 should be dynamically changed to accurately control the turning off of DRAM 148 and global SRAM in different scenarios. The coprocessor 100 integrates power consumption related modules in the system (e.g., idle framework 812, software monitor 802, scheduler run queue 804, wake lock 806, etc.) and uses Artificial Intelligence (AI) prediction 808 to predict what the next timeout should be. In some embodiments, because some Application Program Interfaces (APIs) provided by the system are frequently used, they are arranged to be placed in either the local SRAM 108 or the global SRAM 146. For example, if the DRAM task loops to call these APIs, the timeout counter 600 in the memory access monitor 102 does not timeout to shut down the DRAM 148 or the global SRAM 146.

In some embodiments, the count value of timeout counter 600 in memory access monitor 102 is corrected by combining the load of the DRAM or global SRAM task and the load of the entire coprocessor 100. If the load of the DRAM or global SRAM task is very high, the count value of the timeout counter 600 may be set to a large value or the memory access monitor 102 may be turned off directly. In some embodiments, to achieve better performance, some high frequency SRAM tasks will hold wake locks 806 to prevent coprocessor 100 from executing idle frame 812, which also affects the count value of timeout counter 600.

FIG. 9 illustrates a schematic diagram of the operation of local Static Random Access Memory (SRAM) 108, global SRAM 146, or Dynamic Random Access Memory (DRAM) 148 selected for access according to the task load and the operating frequency, according to an embodiment of the present invention. As shown in fig. 9, coprocessor 100 includes a task live migration monitor 900. Task dynamic migration monitor 900 first receives a plurality of tasks 902. The task dynamic migration monitor 900 selects the local SRAM 108, global SRAM 146, or DRAM 148 to be accessed based on the task load 904 and the operating frequency 906. In some embodiments, if the task's operating frequency is high (e.g., above 200 Hz), the task's live migration monitor 900 chooses to access the local SRAM 108 for better power consumption. If the task's operating frequency is low (e.g., below 5 Hz), the task-dynamic migration monitor 900 chooses to access the DRAM 148 because the DRAM 148 takes a short time and the average power consumption is not high because the operating frequency is low. If the task is running at a frequency between 5Hz and 200Hz, the task dynamic migration monitor 900 selects to access the global SRAM 146. In some embodiments, if a low frequency task is selected to be performed in DRAM 148, it is not suitable to continue to be performed in DRAM 148 because the load of the task is very high. For better power consumption, the task dynamic migration monitor 900 chooses to perform the task in the local SRAM 108.

FIG. 10 shows a schematic diagram of the normally open domain 130, SRAM 146 and DRAM 148 of FIG. 1 in an electronic device 110, in accordance with an embodiment of the invention. Please refer to fig. 2 and fig. 10 simultaneously. The main difference between fig. 2 and 10 is that in fig. 10 there is no memory protection unit 104, so the memory access monitor 102 is directly electrically connected to the DRAM 148 and the global SRAM 146.

FIG. 11 shows a flow chart of a low power interrupt handling method according to an embodiment of the invention. The low power interrupt handling method of the present invention is applied to the electronic device 110 of fig. 1 having the local SRAM 108, global SRAM 146, DRAM 148, co-processor 100, memory access monitor 102, and memory protection unit 104. The method comprises the following steps. An ultra-low power frame is executed (step S1100). The ultra low power frame includes interrupt alignment and active set, memory prediction monitor and task live migration monitor. The interrupt alignment and active set alignment are multiple interrupts (step S1104). The memory prediction monitor predicts the next point of time of accessing the global SRAM 146 and the DRAM 148, and determines whether to power off the global SRAM 146 and the DRAM 148 by the memory access monitor 102 (step S1106). The task dynamic migration monitor selects a global memory (e.g., global SRAM 146 or DRAM 148) or a local memory (e.g., local SRAM 108) to be accessed according to the task load and the running frequency of the task executed by the coprocessor 100 (step S1108).

The step of aligning the interrupt includes the following steps. Interrupts are classified into a plurality of timer vectors according to the trigger frequency of the interrupts to generate a timer wheel. The timer wheel sequentially includes timer vectors corresponding to different trigger frequencies. A last expired timer vector is selected. An interrupt in the timer vector is triggered to perform the corresponding task. An interrupt in a subsequent timer vector in the timer wheel is triggered. In some embodiments, the interrupt trigger frequency in the timer vector is calibrated by eliminating noise.

Any particular order or hierarchy of steps in the processes disclosed herein is by way of example only. Based on design preferences, it is understood that any specific order or hierarchy of steps in the processes may be rearranged within the scope of the disclosure presented in this document. The accompanying method claims present various steps in a sample order, and are, therefore, not limited to the specific order or hierarchy presented.

The use of ordinal terms such as "first," "second," "third," etc., in the claims to modify a component does not by itself connote any priority, precedence, order or order of steps performed by a method, but are used merely as identifiers to distinguish between different components having a same name (having different ordinal terms).

Although the present disclosure has been described with reference to exemplary embodiments, it should be understood that the invention is not limited thereto, but may be modified or altered by persons skilled in the art without departing from the spirit and scope of the disclosure.

Claims (20)

1. An electronic device for low power interrupt handling, comprising:

A local memory;

A global memory;

An application processor;

A coprocessor electrically connected to the local memory, the global memory, and the application processor and configured to run the ultra-low power frame, wherein the ultra-low power frame comprises an interrupt alignment and activity set, a memory prediction monitor, and a task live migration monitor, wherein the interrupt alignment and activity set aligns a plurality of interrupts such that the coprocessor wakes up based on the aligned interrupts to perform all expired low power functions and the application processor wakes up based on the wake-up of the coprocessor, and

The memory protection unit and the memory access monitor are electrically connected with the global memory and the coprocessor, and are used for running the memory prediction monitor to predict the next time point of accessing the global memory and determining whether to close the global memory through the memory access monitor;

wherein the task dynamic migration monitor selects one of the global memory or the local memory to access according to task load and operating frequency.

2. The electronic device of claim 1, wherein the memory protection unit sends an interrupt to the coprocessor to turn on the global memory when the coprocessor first accesses the global memory, and wherein the memory access monitor is electrically connected to the memory protection unit and sends the interrupt to the coprocessor to turn off the global memory when the coprocessor does not access the global memory for a predetermined time.

3. The electronic device of claim 1, further comprising:

And the interrupt controller is electrically connected between the memory access monitor and the coprocessor and is used for bypassing the interrupt of the memory protection unit or the memory access monitor to the coprocessor.

4. The electronic device of claim 1, wherein the global memory comprises dynamic random access memory, DRAM, and global static random access memory, SRAM.

5. The electronic device of claim 1, wherein the local memory comprises a local static random access memory SRAM.

6. The electronic device of claim 1, wherein the interrupt comprises an external interrupt and a timer interrupt.

7. The electronic device of claim 6, wherein the coprocessor aligns the plurality of interrupts by:

Classifying the timer interrupt from the heartbeat timer into a plurality of timer vectors according to the trigger frequency to generate a timer wheel, wherein the timer wheel comprises timer vectors corresponding in sequence to different trigger frequencies;

selecting a most recently expired timer vector;

Triggering an interrupt in the timer vector to perform a corresponding task, and

Triggering the interrupt in a subsequent timer vector in the timer wheel.

8. The electronic device of claim 7, wherein the coprocessor aligns the plurality of interrupts by classifying the external interrupt from the inertial processing unit into the timer vector according to the trigger frequency of the timer interrupt and the external interrupt to generate the timer wheel.

9. The electronic device of claim 8, wherein the coprocessor aligns interrupts by calibrating the trigger frequency of the external interrupt in the timer vector by reducing noise.

10. The electronic device of claim 9, wherein the noise comprises white noise, temperature drift, other interrupts with different trigger frequencies, or interrupt handling errors from the inertial processing unit.

11. The electronic device of claim 10, wherein the coprocessor reduces noise using a local statistical filter or a kalman filter.

12. The electronic device of claim 2, wherein the memory access monitor includes a timeout counter, and wherein the memory access monitor resets a count value of the timeout counter when the memory access monitor determines that the global memory is accessed by the memory protection unit.

13. The electronic device of claim 12, wherein the memory access monitor decrements the count value of the timeout counter by one when the memory access monitor determines that the global memory is not accessed by the memory protection unit.

14. The electronic device of claim 13, wherein the memory access monitor sends an interrupt to the coprocessor to shut down the global memory when the count value of the timeout counter is equal to zero.

15. The electronic device of claim 2, wherein the coprocessor turns on the memory access monitor when the memory protection unit determines that the coprocessor first accesses the global memory.

16. The electronic device of claim 15, wherein the coprocessor turns off the memory access monitor after the memory access monitor sends the interrupt to the coprocessor to turn off the global memory.

17. The electronic device of claim 16, wherein the memory access monitor includes a state machine, and wherein when the memory protection unit determines that the coprocessor is first accessing the global memory, the coprocessor sets the state machine to an enabled state to turn on the memory access monitor.

18. The electronic device of claim 17, wherein after the memory access monitor sends the interrupt to the coprocessor to shut down the global memory, the coprocessor sets the state machine to a disabled state to shut down the memory access monitor.

19. The electronic device of claim 1, wherein the memory protection unit sends the interrupt to the coprocessor to turn on the global memory when the coprocessor first accesses the global memory, and the memory access monitor sends the interrupt to the coprocessor to turn off the global memory when the coprocessor does not access the global memory for the predetermined time.

20. A low power consumption interrupt processing method is applied to an electronic device with a local memory, a global memory, a coprocessor, a memory access monitor and a memory protection monitor, and comprises the following steps:

Running an ultra-low power frame by the coprocessor, wherein the ultra-low power frame comprises an interrupt alignment and active set, a memory prediction monitor and a task dynamic migration monitor;

Aligning a plurality of interrupts by the interrupt alignment and active set such that the coprocessor wakes up based on the aligned interrupts to perform all expired low power functions and the application processor wakes up based on the co-processor wake up;

Running the memory prediction monitor to predict a next point in time at which the memory access monitor and the memory protection unit access the global memory and determining whether to shut down the global memory by the memory access monitor, and

Depending on the task load and the operating frequency, one of the global memory or the local memory is selected for access by the task migration monitor.