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CN1194376C - Microprobe Fabrication Method - Google Patents

Microprobe Fabrication Method Download PDF

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Publication number
CN1194376C
CN1194376C CNB021034982A CN02103498A CN1194376C CN 1194376 C CN1194376 C CN 1194376C CN B021034982 A CNB021034982 A CN B021034982A CN 02103498 A CN02103498 A CN 02103498A CN 1194376 C CN1194376 C CN 1194376C
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conductive layer
etching
contact hole
oxide layer
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CN1437217A (en
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刘醇明
李正汉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

A method for manufacturing a microprobe includes forming an oxide layer on a first surface of a silicon substrate having a first surface and a second surface, forming a first contact hole and a second contact hole in the oxide layer, forming a conductive layer on the first contact hole, the second contact hole and the entire surface, clamping the substrate with a clamp, and etching the second surface of the silicon substrate with the clamp as an etching mask until the conductive layer is exposed to obtain a microprobe structure.

Description

微探针制造方法Microprobe Fabrication Method

技术领域technical field

本发明是有关于一种微探针的制造方法。The invention relates to a manufacturing method of a microprobe.

技术背景technical background

随着半导体电路的渐渐微小化,目前使用的探针过于粗大,在探测一个小接点(0.5um)时,会有很大的问题产生。如图1中所示为一传统微探针装置的架构,其中微探针的针头部分71是连接一个连接部72至一基座73,上述基座与一探测系统74耦接;上述探测系统74是透过可上下左右移动的上述基座,将上述微探针的针头部分门接触到晶圆上的线路,进行电性量测产生的结果,可得知该晶圆上的组件是否正常,但是由于随着半导体电路的渐渐微小化,上述微探针的针头部分71已经不大能符合需求,所以,很多人花费相当多的时间,去制造一个合适的微探针,但是到目前为止,尚没有有效的方法来制造微探针。With the gradual miniaturization of semiconductor circuits, the currently used probes are too thick, and there will be serious problems when probing a small contact (0.5um). As shown in Figure 1, it is the structure of a traditional microprobe device, wherein the needle part 71 of the microprobe is to connect a connection part 72 to a base 73, and the above-mentioned base is coupled with a detection system 74; the above-mentioned detection system 74 is the result of electrical measurement by touching the needle part of the above-mentioned microprobe to the circuit on the wafer through the above-mentioned base that can move up and down, left and right, and it can be known whether the components on the wafer are normal , but with the gradual miniaturization of semiconductor circuits, the needle portion 71 of the above-mentioned micro-probe can no longer meet the demand, so many people spend a lot of time to manufacture a suitable micro-probe, but so far , there is no efficient way to fabricate microprobes.

发明内容Contents of the invention

有鉴于此,本发明的一个目的,是提供一个微探针的制造方法,可以有效地制造一尺寸相当小的微探针,步骤包括:首先,形成一氧化层于具有一第一表面以及一第二表面的一矽基板的上述第一表面上,然后,形成一第一接触孔及一第二接触孔于上述氧化层中,其中上述第二接触孔小于第一接触孔,再形成一导电层于上述第一接触孔、第二接触孔及整个表面上,最后,使用一夹具夹住该基板,以上述夹具当作蚀刻掩膜,对上述矽基板的上述第二表面进行蚀刻,直到露出上述导电层,以得到一个微探针的结构。In view of this, an object of the present invention is to provide a method of manufacturing a microprobe, which can effectively manufacture a microprobe with a relatively small size. The steps include: first, forming an oxide layer on a surface having a first surface and a On the above-mentioned first surface of a silicon substrate on the second surface, then, form a first contact hole and a second contact hole in the above-mentioned oxide layer, wherein the above-mentioned second contact hole is smaller than the first contact hole, and then form a conductive Layer on the above-mentioned first contact hole, second contact hole and the entire surface. Finally, use a jig to clamp the substrate, and use the above-mentioned jig as an etching mask to etch the above-mentioned second surface of the above-mentioned silicon substrate until it is exposed. above the conductive layer to obtain a microprobe structure.

通过本发明的方法,可以制造出适用于0.5um以下撩接点的探针,而且可以将它与微机械成功地连接,以进行探测的功能。Through the method of the present invention, a probe suitable for a contact point below 0.5um can be manufactured, and it can be successfully connected with a micromachine to perform the detection function.

附图说明Description of drawings

图1是显示本发明第一实施例制程剖面图。FIG. 1 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

图2a-图2h是为本发明第一实施例制程剖面图,其中图2d为实施例中导电层的俯视图。2a-2h are sectional views of the manufacturing process of the first embodiment of the present invention, wherein FIG. 2d is a top view of the conductive layer in the embodiment.

图3a-图3i是为本发明第二实施例制程剖面图,其中图3d为实施例中导电层的俯视图。3a-3i are sectional views of the process of the second embodiment of the present invention, wherein FIG. 3d is a top view of the conductive layer in the embodiment.

符号说明Symbol Description

10、310:矽基板;10. 310: silicon substrate;

101、3101:第一表面;101, 3101: first surface;

102、3102:第二表面;102, 3102: second surface;

20、320:氧化层;20, 320: oxide layer;

30a、30b、30c、330a、330b、330c:光阻图案;30a, 30b, 30c, 330a, 330b, 330c: photoresist patterns;

201、3201:第一接触孔;201, 3201: the first contact hole;

202、3202:第二接触孔;202, 3202: second contact hole;

40、340:导电层;40, 340: conductive layer;

401、341:第二导电层;401, 341: the second conductive layer;

50、350:夹具;50, 350: fixture;

401:突出部;401: protrusion;

71:针头部分;71: needle part;

73:基座;73: base;

74:探测系统;74: detection system;

351、352:插塞。351, 352: Plugs.

具体实施方式Detailed ways

以下,结合附图说明本发明的制造微探针的实施例。Hereinafter, an embodiment of manufacturing a microprobe according to the present invention will be described with reference to the drawings.

第一实施例:First embodiment:

首先,参考图2a,形成一氧化层20于具有一第一表面101以及一第二表面102的一矽基板10的上述第一表面101上,举例而言,上述氧化层的厚度大约为1微米的氧化矽、氮化矽或氢氧化矽所构成。接看,参考图2b,利用微影技术进行涂布光阻材料、曝光、显影、烘烤等步骤,以形成接触孔蚀刻用的光阻图案30a、30b及30c,透过上述光阻图案30a、30b及30c当作蚀刻掩膜,蚀刻上述氧化层20形成一第一接触孔201及一第二接触孔202于上述氧化层20中,由于在后续步骤中填入上述第二接触孔202中的导体,将为微探针的针头部分,所以所形成的上述第二接触孔202必须小于上述第一接触孔201,最好为0.13um或更小的蚀刻技术所能达到最小的尺寸。然后,再去除上述光阻掩膜30a、30b及30c。First, referring to FIG. 2a, an oxide layer 20 is formed on the above-mentioned first surface 101 of a silicon substrate 10 having a first surface 101 and a second surface 102. For example, the thickness of the above-mentioned oxide layer is about 1 micron Silicon oxide, silicon nitride or silicon hydroxide. Next, with reference to FIG. 2b, steps such as coating photoresist material, exposure, development, and baking are performed using lithography technology to form photoresist patterns 30a, 30b, and 30c for contact hole etching. Through the above photoresist pattern 30a , 30b and 30c are used as etching masks to etch the above-mentioned oxide layer 20 to form a first contact hole 201 and a second contact hole 202 in the above-mentioned oxide layer 20, because they are filled in the above-mentioned second contact hole 202 in subsequent steps The conductor will be the needle part of the microprobe, so the above-mentioned second contact hole 202 formed must be smaller than the above-mentioned first contact hole 201, preferably 0.13um or the smallest size that can be achieved by etching technology. Then, the photoresist masks 30a, 30b and 30c are removed.

接下来,形成一导电层40于上述第一接触孔201、第二接触孔202及整个表面上,如图2c中所示。另外,如图2e中所示,上述导电层40最好更包括至少一第二导电层401,以逐层由窄变宽的结构形成于上述导电层40之上,其中图2d中为上述导电层410的上视图,以防止最后完成的微探针,由于重力产生下垂的现象,且上述导电层可为铝、钨或其它导电材料所构成。Next, a conductive layer 40 is formed on the first contact hole 201, the second contact hole 202 and the entire surface, as shown in FIG. 2c. In addition, as shown in Figure 2e, the above-mentioned conductive layer 40 preferably further includes at least one second conductive layer 401, which is formed on the above-mentioned conductive layer 40 in a structure that changes from narrow to wide layer by layer, wherein in Figure 2d is the above-mentioned conductive layer 401. The top view of the layer 410 is used to prevent the final microprobe from sagging due to gravity, and the above-mentioned conductive layer can be made of aluminum, tungsten or other conductive materials.

然后,如图2f中所示,使用一夹具50夹住该基板10。接着,如图2g、2h中所示,以上述夹具50当作蚀刻掩膜,对上述矽基板10的上述第二表面102进行蚀刻,直到露出上述导电层40。举例而言,使用电浆蚀刻以去除未被夹具50覆盖而露出的砂基板10,如图2g所示。再蚀刻上述氧化层20,直到露出上述导电层40,造成一个凹槽;如图2h中所示,所以上述导电层41就具有一突出部403,以当作微探针的针头部分,如图1中的针头部分71。当然,上述蚀刻步骤更可包括形成一光阻于上述矽基板10的第二表面102之上,用以于后上述蚀刻步骤中当作一蚀刻掩膜。另外,上述夹具50就如同图1中的基座73,可用耦接一探测系统,以便对晶圆上的组件进行电性量测,经由产生的结果便可得知该晶圆上的组件是否正常。Then, the substrate 10 is clamped using a clamp 50 as shown in FIG. 2f. Next, as shown in FIGS. 2g and 2h , the second surface 102 of the silicon substrate 10 is etched using the jig 50 as an etching mask until the conductive layer 40 is exposed. For example, plasma etching is used to remove the exposed sand substrate 10 not covered by the jig 50, as shown in FIG. 2g. Etch above-mentioned oxide layer 20 again, until exposing above-mentioned conductive layer 40, cause a groove; As shown in Fig. The needle part 71 in 1. Of course, the etching step may further include forming a photoresist on the second surface 102 of the silicon substrate 10 to serve as an etching mask in the subsequent etching step. In addition, the above-mentioned fixture 50 is just like the base 73 in FIG. 1, and can be coupled with a detection system to conduct electrical measurements on the components on the wafer. Through the generated results, it can be known whether the components on the wafer are normal.

其中,上述蚀刻矽基板与上述氧化层的步骤,两者都使用干式蚀刻,或矽基板使用干式蚀刻而上述氧化层使用湿式或干式蚀刻皆可。Wherein, in the step of etching the silicon substrate and the above-mentioned oxide layer, both dry etching is used, or the silicon substrate is dry-etched and the above-mentioned oxide layer is wet-etched or dry-etched.

第二实施例:Second embodiment:

首先,参考图3a,形成一氧化层320于具有一第一表面3101以及一第二表面3102的一矽基板310的上述第一表面3101上,其中上述氧化层为氧化矽、氮化矽或氢氧化矽所构成。接着,参考图3b,利用微影技术进行涂布光阻材料、曝光、显影、烘烤等步骤,以形成接触孔蚀刻用的光阻图案330a、330b及330c,透过上述光阻图案330a、330b及330c当作蚀刻掩膜,蚀刻上述氧化层320形成一第一接触孔3201及一第二接触孔3202于上述氧化层320中,由于在后续步骤中填入上述第二接触孔3202中的导体,将为微探针的针头部分,所以所形成的上述第二接触孔3202必须小于上述第一接触孔3201,最好为0.13um或更小的蚀刻技术所能达到最小的尺寸。然后,再去除上述光阻掩膜330a、330b及330c。First, referring to FIG. 3 a, an oxide layer 320 is formed on the first surface 3101 of a silicon substrate 310 having a first surface 3101 and a second surface 3102, wherein the oxide layer is silicon oxide, silicon nitride or hydrogen Made of silicon oxide. Next, with reference to FIG. 3b, steps such as coating photoresist material, exposure, development, and baking are performed using lithography technology to form photoresist patterns 330a, 330b, and 330c for contact hole etching. Through the above photoresist patterns 330a, 330b and 330c are used as etching masks to etch the above-mentioned oxide layer 320 to form a first contact hole 3201 and a second contact hole 3202 in the above-mentioned oxide layer 320. The conductor will be the needle part of the microprobe, so the formed second contact hole 3202 must be smaller than the first contact hole 3201, preferably 0.13um or the smallest size that can be achieved by etching technology. Then, the photoresist masks 330a, 330b and 330c are removed.

接下来,如图3c中所示,填入一第一导电材料于上述第一接触孔3201、第二接触孔3202中成形两个插塞351、352,其中上述第一导电材料可为铝、钨…等金属或复晶矽的导电材料,举例而言,于本实施例中的上述第一导电材料为铝。接着,如图3d中所示,再形成一导电层340于上述插基351、352及上述氧化层320的表面上,其中上述第一导电材料可由铝、钨等金属或复晶矽导电材料所构成,与导电层是为不同导电材料,举例而言,于本实施例的上述导电层为一复晶矽的导电材料。另外,如第3f图中所示,上述第一导电层340最好更包括至少一第二导电层341,以逐层由窄变宽的结构形成于上述第一导电层340之上,以防止最后完成的微探针,由于重力产生下垂的现象,其中图3e中为上述第一导电层340的上视图。Next, as shown in FIG. 3c, a first conductive material is filled to form two plugs 351, 352 in the first contact hole 3201 and the second contact hole 3202, wherein the first conductive material can be aluminum, The conductive material of metal such as tungsten or polycrystalline silicon, for example, the above-mentioned first conductive material in this embodiment is aluminum. Next, as shown in FIG. 3d, a conductive layer 340 is formed on the surface of the above-mentioned insertion bases 351, 352 and the above-mentioned oxide layer 320, wherein the above-mentioned first conductive material can be made of metals such as aluminum and tungsten or polysilicon conductive materials. The composition and the conductive layer are made of different conductive materials. For example, the above-mentioned conductive layer in this embodiment is a polysilicon conductive material. In addition, as shown in Figure 3f, the above-mentioned first conductive layer 340 preferably further includes at least one second conductive layer 341, which is formed on the above-mentioned first conductive layer 340 in a structure that changes from narrow to wide layer by layer, so as to prevent The final microprobe sags due to gravity, and FIG. 3 e is a top view of the above-mentioned first conductive layer 340 .

然后,如图3g中所示,使用一夹具350夹住该基板310。接着,如图3h、3i所示,以上述夹具350当作蚀刻掩膜,对上述矽基板310的上述第二表面3102进行蚀刻,直到露出上述导电层340。举例而言,使用电浆蚀刻以去除未被夹具50覆盖而露出的矽基板310;如图3g所示,再蚀刻上述氧化层320,直到露出上述第一导电层340,造成一个凹槽,如图3h中所示。所以上述插塞352就整个暴露在上述导电层340上,以当作微探针的针头部分,如图1中的针头部分71。当然,上述蚀刻步骤更可包括形成一光阻于上述矽基极310的第二表面3102之上,用以于后上述蚀刻步骤中当作一蚀刻掩膜。另外,上述夹具就如同图1中的基座73,可用耦接一探测系统,以便对晶圆上的组件进行电性量测,经由产生的结果便可得知该晶圆上的组件是否正常。Then, the substrate 310 is clamped using a clamp 350 as shown in FIG. 3g. Next, as shown in FIGS. 3h and 3i , the second surface 3102 of the silicon substrate 310 is etched using the jig 350 as an etching mask until the conductive layer 340 is exposed. For example, plasma etching is used to remove the exposed silicon substrate 310 not covered by the fixture 50; as shown in FIG. 3g, the oxide layer 320 is etched until the first conductive layer 340 is exposed, forming a groove, as shown in Figure 3h. Therefore, the above-mentioned plug 352 is entirely exposed on the above-mentioned conductive layer 340 to serve as the needle portion of the microprobe, such as the needle portion 71 in FIG. 1 . Of course, the etching step may further include forming a photoresist on the second surface 3102 of the silicon base 310 to serve as an etching mask in the subsequent etching step. In addition, the above-mentioned fixture is like the base 73 in FIG. 1, and can be coupled with a detection system to conduct electrical measurements on the components on the wafer. Through the generated results, it can be known whether the components on the wafer are normal. .

其中,上述蚀刻矽基板与上述氧化层的步骤,两者都使用干式蚀刻,或矽基极使用干式蚀刻而上述氧化层使用湿式或干式蚀刻皆可。Wherein, in the step of etching the silicon substrate and the above-mentioned oxide layer, both dry etching is used, or the silicon base is dry-etched and the above-mentioned oxide layer is wet-etched or dry-etched.

虽然本发明已以一较佳实施例揭露如上,然其并非用以限定本发明,任何熟习此技艺者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视权利要求所界定者为准。Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be defined by the claims.

Claims (16)

1. the manufacture method of a microprobe, step comprises
Form an oxide layer on the above-mentioned first surface of a silicon substrate with a first surface and a second surface;
Form one first contact hole and one second contact hole in above-mentioned oxide layer, wherein above-mentioned second contact hole is less than above-mentioned first contact hole;
Form a conductive layer on above-mentioned first contact hole, second contact hole and whole surface; And
Use this substrate of a clamp clamps, be used as etching mask, the above-mentioned second surface of above-mentioned silicon substrate is carried out etching, up to exposing above-mentioned conductive layer with above-mentioned anchor clamps.
2. the method for claim 1 wherein forms the step of above-mentioned conductive layer, more comprises forming at least one second conductive layer on above-mentioned conductive layer partly.
3. method as claimed in claim 2, wherein above-mentioned second conductive layer are for successively broadening, and along with width successively increases and the structure of thickening.
4. the method for claim 1, wherein the second surface to above-mentioned silicon substrate carries out etching, up to the step of exposing above-mentioned conductive layer, more comprises the step of the above-mentioned oxide layer of an etching.
5. method as claimed in claim 2, wherein above-mentioned conductive layer and at least one second conductive layer are a same material.
6. method as claimed in claim 2, wherein above-mentioned conductive layer and at least one second conductive layer are made of aluminium.
7. method as claimed in claim 2, wherein above-mentioned conductive layer and at least one second conductive layer are constituted by tungsten.
8. method as claimed in claim 4, the step of the above-mentioned oxide layer of etching is wherein used the above-mentioned oxide layer of mode etching of Wet-type etching.
9. method as claimed in claim 4 is wherein carried out etching to above-mentioned silicon substrate, up to the step of exposing above-mentioned conductive layer, is to use the above-mentioned conductive layer of mode etching of dry-etching.
10. the manufacture method of a microprobe, step comprises
Form an oxide layer on the above-mentioned first surface of a silicon substrate with a first surface and a second surface;
Form one first contact hole and one second contact hole in above-mentioned oxide layer, wherein above-mentioned second contact hole is less than above-mentioned first contact hole;
Formation plugs in above-mentioned first contact hole, second contact hole;
Form conductive layer on above-mentioned whole base plate surface; And
Use this substrate of a clamp clamps, be used as etching mask, the above-mentioned second surface of above-mentioned silicon substrate is carried out etching, up to exposing an above-mentioned conductive layer with above-mentioned anchor clamps.
11. manufacture method as claimed in claim 10 wherein forms the step of above-mentioned conductive layer, more comprises
Form at least one second conductive layer on the above-mentioned conductive layer of part.
12. manufacture method as claimed in claim 10, wherein above-mentioned second conductive layer are for successively broadening, and along with width successively increases and the structure of thickening.
13. manufacture method as claimed in claim 11, wherein to above-mentioned silicon substrate second towards carrying out etching, up to the step of exposing above-mentioned conductive layer, more comprise the step of the above-mentioned oxide layer of an etching.
14. manufacture method as claimed in claim 10 is wherein carried out etching to above-mentioned silicon substrate, the step up to exposing above-mentioned conductive layer is to use dry-etching.
15. manufacture method as claimed in claim 13, wherein the step of the above-mentioned oxide layer of etching is to use Wet-type etching.
16. method as claimed in claim 13, wherein the step of the above-mentioned oxide layer of etching is to use dry-etching.
CNB021034982A 2002-02-06 2002-02-06 Microprobe Fabrication Method Expired - Lifetime CN1194376C (en)

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CN100580886C (en) * 2005-05-27 2010-01-13 财团法人工业技术研究院 Gravity liquid etching method capable of controlling structure size
CN100492017C (en) * 2005-11-29 2009-05-27 旺矽科技股份有限公司 Method for batch manufacturing vertical probe card micropore guide plate
CN102121944A (en) * 2010-01-08 2011-07-13 技鼎股份有限公司 Microprobe structure and manufacturing method thereof

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