CN119420333A

CN119420333A - Signal calibration circuit, OOK modulation circuit and signal processing method

Info

Publication number: CN119420333A
Application number: CN202411495740.7A
Authority: CN
Inventors: 季佳文
Original assignee: 3Peak Inc
Current assignee: 3Peak Inc
Priority date: 2024-10-24
Filing date: 2024-10-24
Publication date: 2025-02-11

Abstract

The present invention discloses a signal calibration circuit, an OOK modulation circuit and a signal processing method. The signal calibration circuit includes: a phase detection module, a signal generating circuit, a time digital conversion module and a calibration module. The phase detection module generates a characterization signal that characterizes the phase difference between a data signal and a clock signal; the signal generating circuit is used to generate a pulse signal based on the data signal; the time digital conversion module is used to detect the characterization signal based on the pulse signal to generate a control signal; the calibration module is used to output a result clock signal based on the control signal. According to the signal calibration circuit, OOK modulation circuit and signal processing method of the present invention, the phase difference between the characterization data signal and the clock signal is detected to generate a control signal, thereby calibrating the clock signal to obtain a result clock signal, so that the result clock signals within the effective pulse width range of the data signal are all synchronized, which is conducive to solving the problem of large duty cycle differences of the finally demodulated signal.

Description

Signal calibration circuit, OOK modulation circuit and signal processing method

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a signal calibration circuit, an OOK modulation circuit and a signal processing method.

Background

The transmitting end of the digital isolator modulates the low-frequency data signal to high frequency by using a modulating circuit to transmit, and certain requirements are set for the modulating circuit.

A common OOK modulation circuit is an and gate, with two inputs being a clock signal CLK and a DATA signal DATA, respectively. Since the digital isolator needs to transmit the DATA signal DATA of 0Hz to several tens MHz, the frequency of the clock signal CLK cannot be designed to always be an integer multiple of the frequency of the DATA signal DATA. When the clock signal CLK is not an integer multiple of the DATA signal DATA, a jitter (jitter) problem is likely to occur during modulation, especially for high frequency DATA signals DATA. As shown in fig. 1, the DATA signal DATA is up-mixed, the effective signal width of the obtained signal CLKQ in different DATA periods is different, such signal is filtered by an isolation capacitor, the amplified signal CLKP after filtering is further passed through the receiving end of a digital isolator, and finally the demodulated signal CLKO has the problem of inconsistent duty ratios in different DATA periods.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a signal calibration circuit, an OOK modulation circuit and a signal processing method, which can enable the duty ratio of a calibrated clock signal to be consistent in different data periods when the frequency of the clock signal is not an integral multiple of the frequency of a data signal.

In order to achieve the above objective, a specific embodiment of the present invention provides a signal calibration circuit for calibrating a clock signal based on a data signal, where the signal calibration circuit includes a phase detection module, a signal generation circuit, a time-to-digital conversion module, and a calibration module.

The phase detection module is used for carrying out phase detection on the data signal and the clock signal so as to generate a characterization signal for characterizing the phase difference between the data signal and the clock signal;

the signal generating circuit is used for generating one or more pulse signals based on the data signals;

the time digital conversion module is used for detecting the pulse width of the characterization signal based on the pulse signal so as to generate a control signal;

the calibration module is used for outputting a result clock signal after calibrating the clock signal based on the control of the control signal.

In one or more embodiments of the present invention, the phase detection module includes a first flip-flop, an inverting unit, and a first logic unit, where an input terminal of the first flip-flop is configured to receive a data signal, a clock input terminal of the first flip-flop is configured to receive a clock signal, an input terminal of the inverting unit is configured to receive the data signal, a set terminal of the first flip-flop is connected to an output terminal of the inverting unit, a first input terminal of the second logic unit is connected to an output terminal of the first flip-flop, and a second input terminal of the second logic unit is connected to an output terminal of the inverting unit, and an output terminal of the second logic unit is configured to output a characterization signal.

In one or more embodiments of the invention, the signal generation circuit includes a pulse generation module for generating a pulse signal based on edges of a data signal, or

The signal generating circuit comprises a pulse generating module and a first delay module, wherein the pulse generating module is used for generating an initial pulse signal based on the edge of the data signal, and the first delay module is used for delaying the initial pulse signal one or more times to generate one or more subsequent pulse signals.

In one or more embodiments of the present invention, the time-to-digital conversion module includes one or more second flip-flops, an input of the second flip-flop is configured to receive the characterization signal, a clock input of the second flip-flop is configured to receive the corresponding pulse signal, and an output of the one or more second flip-flops is configured to output the control signal.

In one or more embodiments of the invention, the calibration module includes a buffer unit and an adjustment unit connected to each other, the adjustment unit adjusting a delay time of the buffer unit based on control of the control signal, the buffer unit outputting a resultant clock signal based on the clock signal and adjustment of the adjustment unit, or

The calibration module comprises a second delay module and a gating module which are connected, wherein the second delay module is used for delaying the clock signal once or for many times, and the gating module is used for selecting the original clock signal and the delayed clock signal based on the control of the control signal so as to output a result clock signal.

The invention also discloses an OOK modulation circuit, which comprises a first logic unit and the signal calibration circuit, wherein the first logic unit is used for carrying out logic operation on a result clock signal and a data signal output by the signal calibration circuit to generate a modulation signal.

The invention also discloses a signal processing method, which comprises the following steps of:

performing phase detection on the data signal and the clock signal to generate a characterization signal that characterizes a phase difference between the data signal and the clock signal;

generating one or more pulse signals based on the data signal;

Detecting a pulse width of the characterization signal based on the pulse signal to generate a control signal;

and outputting a result clock signal after calibrating the clock signal based on the control signal.

In one or more embodiments of the invention, the detecting the pulse width of the characterization signal based on the pulse signal to generate the control signal includes:

The number of significant bits of the control signal is obtained based on the number of edges of the pulse signal lying within the pulse width range of the characterization signal.

In one or more embodiments of the present invention, the outputting the calibrated resultant clock signal based on the control signal includes:

adjusting the delay time based on the control signal to output a resulting clock signal, or

The clock signal is delayed one or more times, and the original clock signal and the delayed clock signal are selected based on control of the control signal to output a resultant clock signal.

In one or more embodiments of the present invention, the signal processing method further includes logically operating the resultant clock signal with the data signal to generate a modulated signal.

Compared with the prior art, the signal calibration circuit, the OOK modulation circuit and the signal processing method have the advantages that the characterization signals for characterizing the phase difference between the data signals and the clock signals are detected through the pulse signals to generate corresponding control signals, so that the clock signals are calibrated to obtain result clock signals, the result clock signals in the effective pulse width range of the data signals are kept synchronous, the problem that the duty ratio difference of the finally demodulated signals is large due to the influence of PVT or the non-integral multiple of the clock frequency and the non-data signal frequency is solved, and the signal calibration circuit is suitable for digital isolators with any channel number.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a waveform diagram of signal modulation in the prior art.

Fig. 2 is a schematic circuit diagram of an OOK modulation circuit in a first embodiment.

Fig. 3 is a schematic circuit diagram of the phase detection module and the time-to-digital conversion module in the first embodiment.

Fig. 4 is a schematic circuit diagram of a portion of a calibration module in a first embodiment.

Fig. 5 is a schematic circuit diagram of a switch control unit in the first embodiment.

Fig. 6 is a schematic diagram of a portion of a circuit of a calibration module in another embodiment.

Fig. 7 is a schematic diagram of a portion of a circuit of a calibration module in another embodiment.

Fig. 8 is a signal modulation waveform diagram of the OOK modulation circuit in the first embodiment.

Fig. 9 is a circuit schematic of an OOK modulation circuit in the second embodiment.

Fig. 10 is a schematic circuit diagram of a second delay module in the second embodiment.

Fig. 11 is a schematic circuit diagram of a gating module in the second embodiment.

Fig. 12 is a schematic circuit diagram of a gating module in another embodiment.

Detailed Description

In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection via an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance, and may also include a connection via other active or passive devices, such as a circuit or component via a switch, follower, etc., that achieves the same or similar functional purpose. Furthermore, in the invention, words such as "first," "second," and the like are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number, or order between the technical features.

In the detailed description of the present specification, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments which may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

Various operations in the specification may be described as multiple discrete acts or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed in additional embodiments and/or the described operations may be omitted.

For the purposes of this disclosure, the phrase "a and/or B" refers to (a), (B) or (a and B). For the purposes of this disclosure, the phrase "a, B and/or C" refers to (a), (B), (C), (a and B), (a and C), (B and C) or (a, B and C).

Various components, devices may be referred to or shown herein in the singular (e.g., "transistor," "switch," etc.), but this is for convenience of discussion only and any element referred to in the singular may comprise a plurality of such elements in accordance with the teachings herein.

The description uses the phrases "in one embodiment" or "in other embodiments" or "in some embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

Example 1

As shown in fig. 2, a signal calibration circuit according to an embodiment of the present invention is configured to calibrate a clock signal CLK based on a DATA signal DATA, and the signal calibration circuit includes a phase detection module 10, a signal generation circuit, a time-to-digital conversion module 30, and a calibration module.

The phase detection module 10 is configured to perform phase detection on the DATA signal DATA and the clock signal CLK to generate a characterization signal TIME LENGTH that characterizes a phase difference between the DATA signal DATA and the clock signal CLK. In one embodiment, the phase difference between each falling edge of the DATA signal DATA and the adjacent rising edge of the corresponding clock signal CLK (the rising edge of the clock signal CLK is located after the falling edge of the DATA signal DATA, i.e., the rising edge of the clock signal CLK is located outside the high level of the DATA signal DATA) constitutes each pulse width of the characterization signal TIME LENGTH, the width of the pulse width characterizing the degree of deviation of the clock signal CLK with respect to each falling edge of the DATA signal DATA.

In other embodiments, each pulse width of the characterization signal TIME LENGTH may be formed according to a phase difference between a falling edge of the DATA signal DATA and an adjacent falling edge of the clock signal CLK, each pulse width of the characterization signal TIME LENGTH may be formed according to a phase difference between a rising edge of the DATA signal DATA and an adjacent falling edge of the clock signal CLK, and each pulse width of the characterization signal TIME LENGTH may be formed according to a phase difference between a rising edge of the DATA signal DATA and an adjacent rising edge of the clock signal CLK.

The signal generating circuit is used for generating one or more pulse signals based on the DATA signal DATA. In one embodiment, each falling edge of the DATA signal DATA is used as a reference to generate an initial pulse signal, the initial pulse signal is delayed to generate a next pulse signal, and so on, multiple times of delay generate multiple pulse signals, the pulse signals are different in phase, and the initial pulse signal has corresponding delay relative to the falling edge of the DATA signal DATA. The duration from the start of the initial pulse signal to the end of the continuous generation of the pulse signal by the signal generating circuit is one period of the clock signal CLK, i.e., from each falling edge of the DATA signal DATA until the end of one period of the clock signal CLK, within which period the respective pulse signals are generated. In other embodiments, the initial pulse signal may be generated with the rising edge of the DATA signal DATA as a reference.

The time-to-digital conversion module 30 is configured to detect a pulse width of the signal TIME LENGTH based on the pulse signal to generate the control signal. In one embodiment, the number of valid bits (1 is valid, the number of 1 is valid) and the number of invalid bits (0 is invalid, the number of 0 is invalid) of the control signal form the total number of bits of the control signal by obtaining the number of pulse signals within the pulse width range of the characterization signal TIME LENGTH to determine the number of valid bits of the control signal, and obtaining the number of pulse signals within one clock period t_clk of the clock signal CLK outside the pulse width range of the characterization signal TIME LENGTH to determine the number of invalid bits of the control signal, wherein the number of valid bits (1 is valid) and the number of invalid bits (0 is invalid, and the number of 0 is invalid) of the control signal. The total number of bits of the control signal may be predetermined according to one clock period t_clk of the clock signal CLK and the delay time of each pulse signal, for example, if one clock period t_clk of the clock signal CLK is 1.6ns and the delay time between two adjacent pulse signals is 0.2ns, the total number of bits of the control signal is 8 bits, for example, the number of pulse signals in the pulse width range of the characterization signal TIME LENGTH is 2, the number of pulse signals in the pulse width range of the characterization signal TIME LENGTH is 6, the control signal is 11000000, and for example, if the delay time between two adjacent pulse signals is 0.1ns, the total number of bits of the control signal is 16 bits, and the corresponding detection accuracy is higher. In other embodiments, the number of pulse signals may be determined by the number of falling edges of the pulse signals.

The calibration module is configured to output a result clock signal CLKnew after calibrating the clock signal CLK based on the control signal. In an embodiment, the delay time of the calibration module is adjusted by the control signal to output the resultant clock signal CLKnew, the fewer the number of pulse signals in the pulse width range of the characterization signal TIME LENGTH, i.e. the narrower the pulse width of the characterization signal TIME LENGTH, the fewer the number of valid bits of the control signal, the longer the delay time of the clock signal CLK is needed, and if the pulse width of the characterization signal TIME LENGTH is 0 or equal to one clock period t_clk of the clock signal CLK, the resultant clock signal CLKnew in each valid pulse width (high level) range of the DATA signal DATA is finally kept synchronous (phase is consistent) without delay calibration.

As shown in fig. 3, in a specific example, the phase detection module 10 includes a first flip-flop D1, an inverting unit X, and a first logic unit, where in an embodiment, the first flip-flop D1 is a D flip-flop, and the first logic unit is an exclusive or gate XNOR. The input end of the first trigger D1 is used for receiving the DATA signal DATA, the clock input end of the first trigger D1 is used for receiving the clock signal CLK, the input end of the inverting unit X is used for receiving the DATA signal DATA, the setting end SDN of the first trigger D1 is connected with the output end of the inverting unit X, the first input end of the second logic unit is connected with the output end of the first trigger D1, the second input end of the second logic unit is connected with the output end of the inverting unit X, and the output end of the second logic unit is used for outputting the characterization signal TIME LENGTH.

As shown in fig. 2, in a specific example, the signal generating circuit includes a pulse generating module for generating an initial pulse signal read1 based on an edge (in an embodiment, a falling edge) of the DATA signal DATA, and a first delay module for generating one or more subsequent pulse signals by delaying the initial pulse signal read1 one or more times, where the plurality of subsequent pulse signals are read2 and read3.

As shown in fig. 3, in a specific example, the time-to-digital conversion module 30 includes a plurality of second flip-flops D21, D22..d2n, the second flip-flops are D flip-flops, an input terminal of each of the second flip-flops is configured to receive the characterization signal TIME LENGTH, a clock input terminal of each of the second flip-flops D21, D22..d2n is configured to receive the corresponding pulse signal read1, ready 2.. readn, and an output terminal of each of the plurality of second flip-flops is configured to output the control signal. The number of the second triggers can be selected according to the number of the pulse signals, the number of the second triggers is equal to the number of the pulse signals, the number of the second triggers is corresponding to the number of the control signals, and the n second triggers correspond to the nbit (n-bit) control signals.

In one embodiment, the calibration module includes a buffer unit and an adjustment unit connected to each other, the adjustment unit adjusts a delay time of the buffer unit based on a control signal, and the buffer unit outputs a result clock signal CLKnew based on the clock signal CLK and an adjustment of the adjustment unit.

As shown in fig. 4, in a specific example, the buffer unit includes a first inverter 41 and a second inverter 42, the adjusting unit is connected to the first inverter 41, the power supply and the ground voltage, the adjusting unit is used for adjusting the current on the first inverter 41, the input end of the first inverter 41 is used for receiving the clock signal CLK, the input end of the second inverter 42 is connected to the output end of the first inverter 41, and the output end of the second inverter 42 is used for outputting the result clock signal CLKnew. By adjusting the current on the first inverter 41, the speed at which the first inverter 41 turns on in response to the clock signal CLK can be adjusted, thereby adjusting the delay time of the clock signal CLK.

The first inverter 41 includes a first transistor M1 and a second transistor M2, the second inverter 42 includes a third transistor M3 and a fourth transistor M4, the first transistor M1 and the third transistor M3 are P-channel MOS transistors, and the second transistor M2 and the fourth transistor M4 are N-channel MOS transistors. The source of the first transistor M1 is connected to the adjusting unit, the gate of the first transistor M1 is connected to the gate of the second transistor M2 for receiving the clock signal CLK, the source of the second transistor M2 is connected to the adjusting unit, the drain of the first transistor M1 and the drain of the second transistor M2 are connected to the gate of the third transistor M3 and the gate of the fourth transistor M4, and the drain of the third transistor M3 is connected to the drain of the fourth transistor M4 for outputting the resulting clock signal CLKnew.

In other embodiments, the adjusting unit may be connected to the second inverter 42, the power supply and the ground voltage, the adjusting unit is used for adjusting the current on the second inverter 42, the number of the series connection of the first inverter 41 and the second inverter 42 may be increased or decreased according to the need, and the adjusting unit may also be connected to the first inverter 41 and the second inverter 42, that is, simultaneously adjust the current on the first inverter 41 and the second inverter 42.

As shown in fig. 4, in a specific example, the adjusting unit includes a first adjusting module 43 and a second adjusting module 44, the first adjusting module 43 is connected to the first inverter 41 and the power supply, and the second adjusting module 44 is connected to the first inverter 41 and the ground voltage. The first regulation module 43 and the second regulation module 44 each include a plurality of regulation branches, a first end of the regulation branch of the first regulation module 43 is connected to the power supply voltage, a second end of the regulation branch of the first regulation module 43 is connected to the source of the first transistor M1 of the first inverter 41, and the regulation branch of the first regulation module 43 is used for generating the current flowing into the first inverter 41. The first end of the regulation branch of the second regulation module 44 is connected to the source of the second transistor M2 of the first inverter 41, the second end of the regulation branch of the second regulation module 44 is connected to ground, and the regulation branch of the second regulation module 44 is adapted to generate a current drawn from the first inverter 41.

Each regulating branch comprises a control switch and a current source which are connected in series, wherein each control switch Kn, kn-1..K1 is controlled by a regulating signal N, N-1..1. The current source An, an-1..A 1 generates different magnitudes of current > > I, I..I/m (m is a positive integer greater than 1), and the currents generated by each current source An, an-1..A 1 in one embodiment are different and can be gradually reduced in proportion. When the control switches (Kn) of the two corresponding regulation branches in the first regulation module 43 and the second regulation module 44 are both closed, the current (> I) generated by the corresponding current source (An) is injected into the first inverter 41 and extracted from the first inverter 41. The delay time is adjusted by adjusting the magnitude of the operating current on the first inverter 41, i.e. the opening speed of the first inverter 41, by controlling which adjusting branch is selected to be opened by the adjusting signals N, N-1.

As shown in fig. 5, the first and second adjustment modules 43, 44 also each include a switch control unit that generates an adjustment signal N, N-1..1 based on the control signal to turn on one or more adjustment legs in each adjustment module. The switch control unit comprises a first logic module and a second logic module, and the number of the second logic modules can be adjusted according to the bit number of the control signal. The first logic module is used for generating an adjusting signal N based on a data signal of a first bit of the control signal and a data signal of a last bit of the control signal, and each second logic module is used for generating an adjusting signal N-1.

Specifically, the first logic module includes a first not gate NO1 and an OR gate OR, the input end of the first not gate NO1 is used for receiving the last bit data signal bitn of the control signal, the first input end of the OR gate OR is connected to the output end of the first not gate NO1, the second input end of the OR gate OR is used for receiving the first bit data signal bit1 of the control signal, and the output end of the OR gate OR is used for outputting the adjustment signal N.

Each second logic module comprises a second NOT gate AND an AND gate, the input ends of the second NOT gates NO2 AND NO3.. NOn are used for respectively AND correspondingly receiving data signals bit1 AND bit2.. bitn-1 from the first bit to the last second bit of the control signal, the first input ends of the AND gates AND1 AND AND2.. ANDn are correspondingly connected with the output ends of the second NOT gates NO2 AND NO3.. NOn, the second input ends of the AND gates AND1 AND AND2.. ANDn are used for respectively AND correspondingly receiving data signals bit2 AND bit3.. bitn from the second bit to the last bit of the control signal, AND the output ends of the AND gates AND1 AND AND2.. ANDn are used for outputting adjusting signals N-1..1.

As shown in fig. 6, in another specific example, the adjusting unit is connected between the output end of the first inverter 41 and the input end of the second inverter 42, the adjusting unit includes a resistor R0, a plurality of adjusting branches, and a switch control unit, the first end of the adjusting branch is connected to the input end of the second inverter 42 and the first end of the resistor R0, the second end of the resistor R0 is connected to the output end of the first inverter 41, the second end of the adjusting branch is connected to the ground voltage, and in other embodiments, the position of the resistor R0 may be exchanged. Each adjusting branch comprises a control switch and a capacitor unit which are connected in series, wherein each control switch Kn-1 and Kn-2.1 is controlled by adjusting signals N-1 and N-2.1, and capacitance values of each capacitor unit C and 2.m.C are different and can be increased proportionally and gradually. The switch control unit includes a second logic module, and the structure of the second logic module may refer to the foregoing, which is not described herein, and the first logic module is not set in this embodiment, so that the adjustment signal N is less, because when the control signals of the bits are l or 0, the adjustment signals N are all 0, and one or more adjustment branches are controlled to be turned on by the adjustment signals N-1 and N-2..1, so as to select which capacitor unit is connected to the circuit, or adjust the number of capacitor units in the connection circuit, thereby adjusting the speed from the first inverter 41 to the second inverter 42, and thus adjusting the delay time.

As shown in fig. 7, in another specific example, the adjusting unit is connected between the output end of the first inverter 41 and the input end of the second inverter 42, the adjusting unit includes a capacitor C0, a plurality of adjusting branches, and a switch control unit, the first end of the adjusting branch is connected to the output end of the first inverter 41, the second end of the adjusting branch is connected to the input end of the second inverter 42 and the first end of the capacitor C0, the second end of the capacitor C0 is connected to the ground voltage, and in other embodiments, the positions of the adjusting branches may be exchanged. Each regulating branch comprises a control switch and a resistance unit which are connected in series, each control switch is controlled by regulating signals N-1 and N-2..1, the resistance values of the respective resistance units R, 2*R..m.r may be different, may be progressively proportionally larger. The switch control unit includes a first logic module and a second logic module, and the structures of the first logic module and the second logic module may be referred to the foregoing, and are not described herein again, and one or more adjusting branches are controlled to be turned on by adjusting signals N, N-1, N-2..1 to select which resistor unit is connected to the circuit or adjust the number of resistor units connected to the circuit, so as to adjust the speed from the first inverter 41 to the second inverter 42, thereby adjusting the delay time.

Taking an 8bit control signal as an example, the following is the corresponding truth table.

Bit8	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	8	7	6	5	4	3	2	1
																1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0
1	1	1	1	1	1	1	0	0	1	0	0	0	0	0	0
																1	1	1	1	1	1	0	0	0	0	1	0	0	0	0	0
1	1	1	1	1	0	0	0	0	0	0	1	0	0	0	0
																1	1	1	1	0	0	0	0	0	0	0	0	1	0	0	0
1	1	1	0	0	0	0	0	0	0	0	0	0	1	0	0
																1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
																0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0

Wherein Bit1, bit2, bit3, bit4, bit5, bit6, bit7, bit8 correspond to the 8-Bit data signal of the control signal, and the 8-Bit control signal also corresponds to the 8-Bit adjustment signal 8, 7, 6, 5, 4, 3, 2, 1.

As shown in the truth table, if the pulse width of the characterization signal TIME LENGTH is wider, leading to that the rising edges of the 8 pulse signals are all within the pulse width range, the control signal is 11111111, which is equivalent to delaying the DATA signal DATA by the clock signal CLK by one clock cycle, calibration is not needed, at this time, the adjustment signal n=8 is 1, the adjustment signal N-1=7 is 0, the adjustment signal N-2=6 is 0, the adjustment signal N-3=5 is 0.

If the rising edges of the 7 pulse signals are all within the pulse width range, the control signal is 11111110, at this time, the switch control unit can obtain an adjustment signal n=8 as 0, an adjustment signal N-1=7 as 1, an adjustment signal N-2=6 as 0, and an adjustment signal N-3=5 as 0. As can be seen from fig. 4, the control switch K7 controlled by the adjustment signal N-1=7 is closed, and the reference current I is generated corresponding to the current source A7 connected in series, and at this time, the current on the first inverter 41 can be considered to be reduced compared with the current of > I, the delay of the calibration module is increased, and the calibration module outputs the resultant clock signal CLKnew delayed by the first delay time.

If the rising edges of the 6 pulse signals are all within the pulse width range, the control signal is 11111100, at this time, the switch control unit can obtain an adjustment signal n=8 as 0, an adjustment signal N-1=7 as 0, an adjustment signal N-2=6 as 1, and an adjustment signal N-3=5 as 0. The control switch K6 controlled by the adjustment signal N-2=6 is closed, and the corresponding series current source A6 generates the reference current I/2, at this time, the current on the first inverter 41 can be considered to be reduced compared with the reference current I, the delay of the calibration module is further increased, and the calibration module outputs the resultant clock signal CLKnew delayed by the second delay time.

Similarly, if no rising edge of the pulse signal is within the pulse width range, the control signal is 00000000, i.e. no pulse width of the characterization signal TIME LENGTH is generated, no calibration of the clock signal CLK is needed, at this time, the adjustment signal n=8 is 1, the adjustment signal N-1=7 is 0, the adjustment signal N-2=6 is 0, the adjustment signal N-3=5 is 0, as can be seen from fig. 4, the control switch K8 controlled by the adjustment signal n=8 is closed, and the corresponding current source A8 connected in series generates > I current (I is a reference current), at this time, the first inverter 41 can be considered to be completely opened, the delay of the calibration module is negligible, and the calibration module outputs the resultant clock signal CLKnew synchronized with the clock signal CLK.

As shown in fig. 8, first, the clock signal CLK and the DATA signal DATA are subjected to phase detection, and the duration between the falling edge of the DATA signal DATA and the next rising edge of the clock signal CLK is detected to obtain the characterization signal TIME LENGTH, where the characterization signal TIME LENGTH has pulse widths with different widths based on the magnitude of the phase difference between the clock signal CLK and the DATA signal DATA, and it is seen that the width of the pulse width of the characterization signal TIME LENGTH is within one clock period t_clk of the clock signal CLK.

The periodic initial pulse signal read1 is obtained according to the DATA signal DATA, the period of the pulse signal read1 is the same as the period of the DATA signal DATA, and the pulse width of the pulse signal read1 cannot exceed the pulse width of the DATA signal DATA after the falling edge of the DATA signal DATA.

The pulse signal read1 is delayed n times, and the delay time of each time is Δt, so that the pulse signals read2, read3.. readn are obtained, and rising edges of the nbit pulse signals read1, read2, and read3.. readn in a single period are uniformly distributed in one clock period t_clk after the falling edge of the DATA signal DATA. The nbit pulse signals read1, read2, and read3.. readn are used for reading the characterization signal TIME LENGTH in the clock period t_clk after the falling edge of the DATA signal DATA, the nbit pulse signals read1, read2, read3.. readn and the characterization signal TIME LENGTH are input into the time-to-digital conversion module 30 to obtain an nbit control signal, the nbit control signal controls the length of the delay required by the clock signal CLK after the corresponding clock period t_clk after the falling edge of the DATA signal DATA (see the length of the thick line in the result clock signal CLKnew in fig. 8), the calibrated result clock signal CLKnew is obtained, and the result clock signal CLKnew and the DATA signal DATA are subjected to AND operation to obtain the modulation signal MIXERout. As can be seen from the timing diagram of fig. 8, the effective DATA frequency of the resulting modulated signal MIXERout is more converged after the first falling edge of the DATA signal DATA.

Further, the length relationship between the nbit control signal and the clock signal CLK in the corresponding period is as follows, the clock signal CLK is controlled by 625MHz (1.6 ns) in which the clock signal CLK is delayed, the 8-bit pulse signals read1, read2, and read3 are used, each bit control signal corresponds to the delay time of 0.2ns, if the time between the falling edge of the DATA signal DATA and the rising edge of the next clock signal CLK is 0.3ns, the pulse width of the characterization signal TIME LENGTH is 0.3ns, the 8-bit control signal is 11000000 (0.2ns+0.2ns), the clock signal CLK is controlled by 1.2ns (1.6 ns-0.2 ns) in the period, the pulse width of the characterization signal TIME LENGTH is 0.7ns if the falling edge of the DATA signal CLK is 0.7ns, the 8-bit control signal is 11110000 ns in the period, and if the falling edge of the DATA signal DATA is 0.8ns is not delayed from the falling edge of the next clock signal CLK, the clock signal is not controlled by 20.20.2 ns, and if the clock signal CLK is delayed by 1.20.20 ns in the period, the clock signal is not delayed by 1.20 ns, and the pulse width of the clock signal is not controlled by 1.1118 ns. From this analysis, the more the number of pulse signal bits, the more accurately the clock signal CLK is synchronized with the DATA signal DATA.

One clock period t_clk after the falling edge of the DATA signal DATA belongs to the time of pulse width detection of the sign signal TIME LENGTH by using the pulse signal, and each period of the DATA signal DATA corresponds to a delay time of a different clock signal CLK, which is unstable. After the falling edge of the DATA signal DATA is added by one clock period t_clk, the detection is completed, a control signal is generated, a stable result clock signal CLKnew is generated, the falling edge of the next DATA signal DATA is maintained, the detection is carried out again after the falling edge of the next DATA signal DATA, and the control signal and the new delay time are regenerated.

As shown in fig. 2, the present invention further discloses an OOK modulation circuit, which includes a first logic unit and the signal calibration circuit described above, wherein the first logic unit is configured to perform a logic operation on a result clock signal CLKnew output by the signal calibration circuit and a DATA signal DATA to generate a modulation signal MIXERout. In one embodiment, the first logic unit is a logic and gate (AND gate) that performs an AND operation on the result clock signal CLKnew and the DATA signal DATA to generate the modulation signal MIXERout.

The embodiment also discloses a signal processing method, based on the signal calibration circuit, the signal processing method comprises the following steps:

the DATA signal DATA and the clock signal CLK are phase detected to generate a characterization signal TIME LENGTH that characterizes the phase difference between the DATA signal DATA and the clock signal CLK.

One or more pulse signals are generated based on the DATA signal DATA.

The pulse width of the characterization signal TIME LENGTH is detected based on the pulse signal to generate a control signal. Specifically, the number of valid bits of the control signal is obtained based on the number of edges of the pulse signal that lie within the pulse width range of the characterization signal TIME LENGTH.

The clock signal CLKnew after the clock signal CLK is calibrated is outputted based on the control of the control signal. Specifically, the delay time is adjusted based on the control signal to output a resulting clock signal CLKnew.

The resulting clock signal CLKnew is logically operated with the DATA signal DATA to generate the modulated signal MIXERout.

Specific signal processing methods and signal processing principles may be referred to in the above description of circuit principles.

Example 2

As shown in fig. 9, the difference between the present embodiment and embodiment 1 is that the calibration module includes a second delay module for delaying the clock signal CLK a plurality of times and a gating module for selecting the original clock signal and the delayed clock signal based on the control of the control signal to output the resultant clock signal CLKnew.

As shown In fig. 10, the second delay module includes a plurality of buffer units a1, a 2..a3 and current sources I1, I2..in connected to the buffer units a1, a 2..a3, where the number of the buffer units can be adjusted according to the need, each buffer unit includes two sets of transistors (e.g., a P-channel MOS transistor M11 and an N-channel MOS transistor M12, a P-channel MOS transistor M13 and an N-channel MOS transistor M14, a P-channel MOS transistor M21 and an N-channel MOS transistor M22, a P-channel MOS transistor M23 and an N-channel MOS transistor M24, and..p-channel MOS transistor Mn1 and an N-channel MOS transistor Mn2, a P-channel MOS transistor Mn3 and an N-channel MOS transistor Mn4, and four or more sets of transistors can be also be disposed In the buffer units. In other embodiments, the second delay module may be other circuit structures.

In one embodiment, each of the current sources I1, I2..in is connected to a set of transistors of the buffer units, respectively, and the delay time of each buffer unit is changed by changing the current generated by the current sources I1, I2..in, the larger the current is, the larger the opening speed of the buffer unit is, the shorter the delay time is, and each buffer unit delays the clock signal CLK by different delay times to generate the clock signals CLK1, clk2..clkn-1.

As shown in fig. 11, in a specific example, the gating module includes a plurality of switching units controlled by the adjustment signals N, N-1..1. The adjustment signals N, N-1..1 are generated by the switching control units as shown in fig. 5, each switching unit includes a control switch, a first terminal of each control switch Kn, kn-1..k1 is used for receiving the clock signals CLK0, CLK1, clk2..clkn-1, the clock signal CLK0 is the original clock signal, and the adjustment signals N, N-1..1 select which control switch is controlled to be turned on to output the corresponding clock signal CLKnew at a second terminal of the control switch.

As shown in fig. 12, in another specific example, the gating module includes a plurality of switching units controlled by the adjustment signals N, N-1..1, a part of the switching units including a first control switch, and another part of the switching units including a second control switch and an inverter. Wherein a first terminal of the first control switch Kn, kn-1..kn/2+1 receives the clock signals CLK0, CLK1, clk2..clkn/2-1 and is selectively controlled by the adjustment signals N, N-1..n/2+1 which first control switch is turned on to output a corresponding resulting clock signal CLKnew at a second terminal of the first control switch, and a second control switch Kn-N/2, kn- (N/2+1)..k1 is connected in series with the inverters X1, X2...xn, the clock signals CLK0, CLK1, clk2..clkn/2-1 are inverted by the inverters X1, X2...clkn/2-1 and which second control switch is selectively controlled by the adjustment signals N-N/2, N- (N/2+1)..1 to output a corresponding resulting clock signal CLKnew. The number of the first control switches is equal to the number of the second control switches, and in other embodiments, the number of the first control switches and the number of the second control switches may be respectively selected according to needs.

One or more pulse signals are generated based on the DATA signal DATA.

The clock signal CLK is delayed one or more times.

The original clock signal and the delayed clock signal are selected based on control of the control signal to output a resulting clock signal CLKnew.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.

Claims

1. A signal calibration circuit for calibrating a clock signal based on a data signal, the signal calibration circuit comprising:

A signal generating circuit for generating one or more pulse signals based on the data signal;

A time-to-digital conversion module for detecting the pulse width of the characterization signal based on the pulse signal to generate a control signal, and

And the calibration module is used for outputting a result clock signal after calibrating the clock signal based on the control of the control signal.

2. The signal calibration circuit of claim 1, wherein the phase discrimination module comprises a first flip-flop, an inverting unit, and a first logic unit, wherein an input of the first flip-flop is configured to receive the data signal, a clock input of the first flip-flop is configured to receive the clock signal, an input of the inverting unit is configured to receive the data signal, a set of the first flip-flop is coupled to an output of the inverting unit, a first input of the second logic unit is coupled to an output of the first flip-flop, a second input of the second logic unit is coupled to an output of the inverting unit, and an output of the second logic unit is configured to output the characterization signal.

3. The signal calibration circuit of claim 1, wherein the signal generation circuit comprises a pulse generation module for generating a pulse signal based on edges of a data signal, or

4. The signal calibration circuit of claim 1, wherein the time-to-digital conversion module comprises one or more second flip-flops having inputs for receiving the characterization signal, clock inputs for receiving the corresponding pulse signals, and outputs for outputting the control signal.

5. The signal calibration circuit of claim 1, wherein the calibration module comprises a buffer unit and an adjustment unit connected to each other, the adjustment unit adjusting a delay time of the buffer unit based on control of the control signal, the buffer unit outputting a resultant clock signal based on the clock signal and adjustment of the adjustment unit, or

6. An OOK modulation circuit comprising a first logic unit and a signal calibration circuit according to any one of claims 1 to 5, wherein the first logic unit is configured to perform a logic operation on a result clock signal and a data signal output by the signal calibration circuit to generate a modulation signal.

7. A signal processing method, characterized in that it is based on a signal calibration circuit according to any one of claims 1 to 6, the signal processing method comprising:

generating one or more pulse signals based on the data signal;

8. The signal processing method of claim 7, wherein detecting the pulse width of the characterization signal based on the pulse signal to generate the control signal comprises:

9. The signal processing method of claim 7, wherein the outputting the calibrated resultant clock signal based on the control signal comprises:

10. The signal processing method of claim 7, further comprising performing a logic operation on the resulting clock signal and the data signal to generate the modulated signal.