CN119418645B - Display panel and display device - Google Patents
Display panel and display deviceInfo
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- CN119418645B CN119418645B CN202411721749.5A CN202411721749A CN119418645B CN 119418645 B CN119418645 B CN 119418645B CN 202411721749 A CN202411721749 A CN 202411721749A CN 119418645 B CN119418645 B CN 119418645B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
本公开提供一种显示面板及显示装置，涉及显示技术领域，像素驱动电路包括驱动晶体管、第一复位模块和数据写入模块，驱动晶体管的栅极连接第一节点，第一极连接第二节点、第二极连接第三节点；第一复位模块的两端分别连接第一复位信号线和第一节点，控制端连接第一扫描线；数据写入模块的两端分别连接数据信号线和第二节点，控制端连接第二扫描线；显示区包括沿第一方向排列的第一显示区和第二显示区，第一显示区位于第二显示区和绑定区之间；在各像素驱动电路中，第一节点与第二扫描线之间形成第一电容；第一显示区对应的像素驱动电路中第一电容的容值，小于第二显示区对应的像素驱动电路中第一电容的容值，以提升显示均一性。
The present disclosure provides a display panel and a display device, relating to the field of display technology. A pixel driving circuit includes a driving transistor, a first reset module, and a data writing module. The gate of the driving transistor is connected to a first node, the first electrode is connected to a second node, and the second electrode is connected to a third node. Two ends of the first reset module are respectively connected to a first reset signal line and a first node, and a control end is connected to a first scan line. Two ends of the data writing module are respectively connected to a data signal line and a second node, and a control end is connected to a second scan line. The display area includes a first display area and a second display area arranged along a first direction, and the first display area is located between the second display area and a binding area. In each pixel driving circuit, a first capacitor is formed between the first node and the second scan line. The capacitance of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than the capacitance of the first capacitor in the pixel driving circuit corresponding to the second display area, so as to improve display uniformity.
Description
Technical Field
The disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the continuous development of science and technology, more and more display products, such as mobile phones, tablet computers, notebook computers, intelligent wearing equipment and the like, are widely applied to daily life and work of people, bring great convenience to daily life and work of people, and become an indispensable important tool for people at present.
At present, how to improve the uniformity of the display brightness of the display product so as to improve the display effect becomes one of the technical problems to be solved in the present stage.
Disclosure of Invention
In order to solve the technical problems, the present disclosure provides a display panel and a display device.
In a first aspect, the present disclosure provides a display panel including a display region and a binding region located at one side of the display region in a first direction, the display region including a plurality of light emitting elements and a pixel driving circuit connected to the light emitting elements;
The pixel driving circuit comprises a driving transistor, a first reset module and a data writing module, wherein a grid electrode of the driving transistor is connected with a first node, a first electrode of the driving transistor is connected with a second node, and a second electrode of the driving transistor is connected with a third node;
The display area comprises a first display area and a second display area which are arranged along the first direction, the first display area is positioned between the second display area and the binding area, a first capacitor is formed between the first node and the second scanning line in each pixel driving circuit, and the capacitance value of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than that of the first capacitor in the pixel driving circuit corresponding to the second display area.
The display panel comprises a display area and a binding area which is positioned at one side of the display area along a first direction, wherein the display area comprises a plurality of light emitting elements and a pixel driving circuit connected with the light emitting elements, the pixel driving circuit comprises a driving transistor, a first reset module and a data writing module, wherein a grid electrode of the driving transistor is connected with a first node, a first electrode of the driving transistor is connected with a second node and a second electrode of the driving transistor is connected with a third node;
The display area comprises a first display area and a second display area which are arranged along the first direction, the first display area is positioned between the second display area and the binding area, in the pixel driving circuit of the first display area, a shielding part is arranged at the first node along the direction parallel to the light emitting surface of the display panel, and the side direction of the first node towards the second scanning line receives a fixed potential signal.
In a third aspect, the present disclosure provides a display device including the display panel according to any one of the first and second aspects of the present disclosure.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
in the display panel and the display device provided by the disclosure, in each pixel driving circuit, a first capacitor is formed between the first node and the second scanning line, and the first capacitor can be regarded as a coupling capacitor between the first node and the second scanning line due to the fact that the first node and the second scanning line are adjacent. The first capacitors of the first display area and the second display area are designed in a differentiation mode, so that the capacitance value of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than that of the first capacitor in the pixel driving circuit corresponding to the second display area. Therefore, the coupling capacitance between the second scanning line and the first node in the first display area is reduced, the coupling influence of signal jump on the second scanning line in the first display area on the first node is reduced, the condition that the brightness of the first display area is dark is improved, and the potential of the first node in the first display area is consistent or nearly consistent after being influenced by the coupling capacitance, so that the problem that the display brightness difference between the first display area and the second display area is larger due to the potential inconsistency of the first node is reduced, the overall display brightness uniformity of the display panel is improved, and the display effect is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic plan view of a display panel according to an embodiment of the disclosure;
FIG. 2 is a schematic diagram showing a connection between a pixel driving circuit and a light emitting element in a display panel;
FIG. 3 is a driving timing diagram corresponding to the pixel driving circuit of FIG. 2;
FIG. 4 is a schematic diagram showing a connection between a scan line and a gate driving circuit;
FIG. 5 is a schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the disclosure;
fig. 6 is a diagram illustrating a structure of a film layer of a display panel according to an embodiment of the disclosure;
FIG. 7 is a schematic diagram showing another layout of a pixel driving circuit according to an embodiment of the disclosure;
FIG. 8 is a schematic diagram showing another layout of a pixel driving circuit according to an embodiment of the disclosure;
FIG. 9 is a schematic diagram showing another layout of a pixel driving circuit according to an embodiment of the disclosure;
FIG. 10 is a schematic diagram showing another layout of a pixel driving circuit according to an embodiment of the disclosure;
FIG. 11 is a schematic diagram showing another layout of a pixel driving circuit according to an embodiment of the disclosure;
FIG. 12 is a schematic diagram showing another connection between a pixel driving circuit and a light emitting element in a display panel;
fig. 13 is a schematic structural diagram of a display device according to an embodiment of the disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein, and it is apparent that the embodiments in the specification are only some, rather than all, of the embodiments of the present disclosure.
Fig. 1 is a schematic plan view of a display panel according to an embodiment of the disclosure, fig. 2 is a schematic connection diagram of a pixel driving circuit 10 and a light emitting element 30 in the display panel, fig. 3 is a driving timing diagram corresponding to the pixel driving circuit 10 in fig. 2, and fig. 4 is a schematic connection diagram of a scan line and a gate driving circuit. It should be noted that, in the embodiments of the present disclosure, only the transistors in the pixel driving circuit 10 are all P-type transistors, the active level signal of the on state of the P-row transistor is a low level signal, and the off state signal is a high level signal, but the present disclosure is not limited thereto, and in other embodiments of the present disclosure, the transistors in the pixel driving circuit 10 may be all N-type transistors, or may be a combination of P-type transistors and N-type transistors, which is not particularly limited thereto. The active level signal of the N-type transistor is a high level signal, and the off signal is a low level signal.
Referring to fig. 1 to 4, the embodiment of the disclosure provides a display panel, which includes a display area A1 and a binding area A2 located at one side of the display area along a first direction D1, wherein the display area A1 includes a plurality of light emitting elements 30 and a pixel driving circuit 10 connected to the light emitting elements 30, the pixel driving circuit 10 includes a driving transistor DT, a first reset module 71 (illustrated by including a transistor T1 as an example) and a data writing module 72 (illustrated by including a transistor T5 as an example), wherein a gate of the driving transistor DT is connected to a first node N1, a first pole is connected to a second node N2, and a second pole is connected to a third node N3, two ends of the first reset module 71 are respectively connected to a first reset signal line Vref1 and the first node N1, a control end is connected to a first scan line S1, two ends of the data writing module 72 are respectively connected to a data signal line DL and a second node N2, a control end is connected to the second scan line S2, and the third node N3 is used for electrically connecting to the light emitting elements 30. The display area A1 of the display panel includes a first display area a11 and a second display area a12 aligned in the first direction D1, the first display area a11 being located between the second display area a12 and the bonding area A2.
Optionally, the pixel driving circuit 10 further includes a first light emitting control module 73 (illustrated as including a transistor T3) and a second light emitting control module 74 (illustrated as including a transistor T4), the first light emitting control module 73 is connected between the first power signal terminal PVDD and the second node N2, the second light emitting control module 74 is connected between the third node N3 and the light emitting element 30, and control terminals of the first light emitting control module 73 and the second light emitting control module 74 are connected to the light emitting control signal line EM. Optionally, the pixel driving circuit 10 further includes a threshold compensation module 75 (illustrated by way of example as including a transistor T6), the threshold compensation module 75 is connected between the first node N1 and the third node N3, and a control terminal of the threshold compensation module 75 is connected to the second scan line S2.
The operation of the pixel driving circuit 10 includes:
In the first reset stage, the first scan line S1 supplies an active level signal to the first reset module 71, the first reset module 71 is turned on, and a reset signal on the first reset signal line Vref1 is transmitted to the first node N1 to reset the first node N1.
In the data writing and threshold compensation stage, the second scanning line S2 provides an effective level signal to the data writing module 72 and the threshold compensation module 75, the data writing module 72 and the threshold compensation module 75 are turned on, the data signal on the data signal line DL is transmitted to the second node N2, and the threshold compensation is performed on the gate of the driving transistor DT by the threshold compensation module 75.
In the light emitting stage, the light emitting control signal line EM sends an effective level signal to the first light emitting control module 73 and the second light emitting control module 74, controls the first light emitting control module 73 and the second light emitting control module 74 to be conducted, and the signal of the first power supply signal end PVDD is transmitted to the driving transistor DT to form current for driving the light emitting element 30 to emit light.
In the pixel driving circuit 10 described above, the stability of the potential of the gate electrode (corresponding to the first node N1 in the drawing) of the driving transistor DT directly affects the magnitude of the driving current formed in the light emission stage. In the driving sequence shown in fig. 3, after the data writing is completed, the potential on the second scan line S2 jumps from the low level to the high level, and if the distance between the second scan line S2 and the first node N1 is relatively short, the signal change on the second scan line S2 will be coupled to the first node N1, so that the potential of the first node N1 changes, and the magnitude of the driving current is affected. If the number of pixel driving circuits 10 connected to each second scan line S2 in the display panel is equal, the loads of the second scan lines S2 are equal or nearly equal, the coupling effect of the second scan lines S2 to the first node N1 will be equal, and the overall display brightness of the display panel will be equal.
But for the architecture shown in fig. 4, the loading of the second scan line S2 is not uniform. Referring to fig. 4, in an alternative embodiment of the disclosure, a display panel includes M pixel driving circuit rows H, the display panel includes N cascaded gate driving circuits (Scan 1 to Scan (N)) n=m+s, a first Scan line S1 corresponding to a pixel driving circuit 10 located in an mth row is electrically connected to a gate driving circuit of an mth stage, and a second Scan line S2 corresponding to a pixel driving circuit 10 located in an mth row is electrically connected to a gate driving circuit of an mth+s stage, where M is greater than or equal to 1 and less than or equal to M, S is greater than or equal to 2, and s=7 is taken as an example for illustration, but the embodiment is not limited thereto. The rows of the pixel driving circuits 10 connected to the gate driving circuits of the m+1st to m+s th stages (corresponding Scan (n-13) to Scan (n-7) in the drawing) are located in the first display area a11. Taking the architecture shown in fig. 4 as an example, the first Scan line S1 corresponding to the pixel driving circuit 10 of the first row is connected to the gate driving circuit Scan1 of the 1 st stage, the second Scan line S2 corresponding to the pixel driving circuit 10 of the first row is connected to the gate driving circuit Scan8 of the 8 th stage, that is, after the first node N1 is reset to the pixel driving circuit 10 of the first row, the data is written again at intervals of 8 Scan lines 8H, which is advantageous to increase the time for resetting the first node N1 and restore the potential of the first node N1 to the initial state. For the pixel driving circuit 10 of the second row, the first scanning line S1 is connected to the gate driving circuit Scan2 of the 2 nd stage, the second scanning line S2 is connected to the gate driving circuit Scan9 of the 9 th stage, and so on. Thus, when there are M rows of pixel driving circuits 10 in the display panel, it will be necessary to design m+7 stages of gate driving circuits in the display panel, the gate driving circuits (Scan 1 to Scan (n-12)) for the first M stages will be connected to two rows of pixel driving circuits 10, and the gate driving circuits (Scan (n-13) to Scan (n-7)) for the latter 7 stages will be connected to only 1 row of pixel driving circuits, and provide control signals to the second Scan lines S2 corresponding to 1 row of pixel driving circuits, and the 7 rows of pixel driving circuits connected to the gate driving circuits for the latter 7 stages are located in the first display area a11. in this way, the second scan lines S2 in the first display area a11 are electrically connected to only one row of the pixel driving circuits 10, the second scan lines S2 in the second display area a12 are electrically connected to both rows of the pixel driving circuits 10, that is, the loads of the second scan lines S2 in the first display area a11 and the second display area a12 are different, when the data writing is completed, the signal transitions on the second scan lines S2 are at a high level, because the loads are different, the loads of the second scan lines S2 in the first display area a11 are smaller, the coupling effect of the signal transitions of the second scan lines S2 in the first display area a11 and the second display area a12 on the first node N1 in the first display area a11 will be different, the pull-up amplitude of the first node N1 in the first display area a11 after being coupled by the signals on the second scan lines S2 will be larger, so that the electric potentials of the first node N1 in the first display area a11 and the second display area a12 after being coupled are different, and the first luminance problem occurs in the first display area a12 than the second luminance area a 12.
In order to solve the above technical problems, the embodiments of the present disclosure provide two improvements:
A first modification is that, in each pixel driving circuit 10, a first capacitor is formed between the first node N1 and the second scan line S2, and the first capacitor can be regarded as a coupling capacitor between the first node N1 and the second scan line S2 due to the adjacent first node N1 and the second scan line S2. The first improvement provided in this embodiment is to perform differential design on the first capacitors of the first display area a11 and the second display area a12, so that the capacitance value of the first capacitor in the pixel driving circuit 10 corresponding to the first display area a11 is smaller than the capacitance value of the first capacitor in the pixel driving circuit 10 corresponding to the second display area a 12. In this way, the coupling capacitance between the second scanning line S2 and the first node N1 in the first display area a11 is reduced, so that the coupling influence of the signal jump on the second scanning line S2 in the first display area a11 on the first node N1 is reduced, the condition that the brightness of the first display area a11 is dark is improved, and the potential of the first node N1 in the first display area a11 affected by the coupling capacitance is consistent or nearly consistent, so that the problem that the difference between the display brightness of the first display area a11 and the display brightness of the second display area a12 is larger due to the inconsistent potential of the first node N1 is reduced, and the overall display brightness uniformity of the display panel is improved, and the display effect is improved.
On the basis of the first scheme, in order to implement the differential design of the first capacitances corresponding to the first display area a11 and the second display area a12, please refer to fig. 5, which is a schematic layout diagram of the pixel driving circuit 10 provided in the embodiment of the disclosure shown in fig. 5, fig. 6 is a film layer structure diagram of the display panel provided in the embodiment of the disclosure, optionally, in the pixel driving circuit 10 of the first display area a11, along a direction parallel to the light emitting surface of the display panel, a shielding portion 90 is disposed at a side direction of the first node N1 facing the second scanning line S2, and the shielding portion 90 receives a fixed potential signal. In this embodiment, the shielding portion 90 for receiving the fixed potential signal is introduced into the area between the first node N1 and the second scan line S2, and when the signal on the second scan line S2 hops, the shielding portion 90 can reduce the influence of the hopped signal on the first node N1 due to the shielding portion 90, so as to reduce the coupling capacitance between the second scan line S2 in the first display area a11 and the first node N1, thereby realizing that the capacitance value of the first capacitance in the pixel driving circuit 10 corresponding to the first display area a11 is smaller than the capacitance value of the first capacitance in the pixel driving circuit 10 corresponding to the second display area a12, so as to reduce the display brightness difference between the first display area a11 and the second display area a 12.
In the second scheme, in the pixel driving circuit 10 of the first display area a11, a shielding portion 90 is disposed along a direction parallel to the light emitting surface of the display panel, and the first node N1 faces the second scanning line S2, and the shielding portion 90 receives a fixed potential signal. Referring to fig. 5 and fig. 6 specifically, in conjunction with fig. 1 to fig. 4, in this embodiment, a shielding portion 90 for receiving a fixed potential signal is introduced in a region between a first node N1 and a second scan line S2, when a signal on the second scan line S2 hops, due to the shielding portion 90, the shielding portion 90 is capable of reducing the influence of the hopped signal on the first node N1 in the first display area a11, thereby reducing the coupling capacitance between the second scan line S2 in the first display area a11 and the first node N1, facilitating improvement of the coupling influence of the second scan line S2 on the first node N1 after the completion of data writing due to a smaller load of the second scan line S2 in the first display area a11, thereby facilitating balancing the influence of the second scan line S2 on the first node N1 in the first display area a11 and the second display area a12, facilitating the improvement of the luminance element N1 when the luminance of the second scan line S2 is close to the first node N1 after the completion of data writing, and facilitating the improvement of the luminance element to the luminance of the first node a when the luminance element is close to the first node a.
The following description will be further directed to the first and second schemes, and it should be noted that the following embodiments are applicable to both the first and second schemes, and may be regarded as further expansion description of the first scheme, and may also be further expansion description of the second scheme, where the same points will not be expressed separately.
Referring to fig. 6, fig. 6 illustrates a film structure of a display panel, optionally, the display panel provided in the embodiments of the disclosure includes a substrate 00, a driving layer 40, and a display layer 10, where the display layer 10 includes a pixel defining layer 19, the pixel defining layer 19 defines a plurality of pixel openings, a luminescent material layer 302 is at least located in the pixel openings, an anode 301 and a cathode 303 are respectively located at two sides of the luminescent material layer 302 along a direction perpendicular to the substrate 00, and the anode 301 is located at a side of the cathode 303 facing the substrate 00. Optionally, an encapsulation layer 50 is further disposed on a side of the cathode 303 remote from the anode 301, and optionally, the encapsulation layer 50 includes a first inorganic layer 51, an organic layer 52, and a second organic layer 53 that are stacked. The pixel driving circuit mentioned in the foregoing embodiment is located in the driving layer 40, and the pixel driving circuit includes a plurality of transistors T. Alternatively, in the driving layer 40, the gate electrode of the transistor is disposed at the first metal layer M1, and the source and drain electrodes of the transistor are disposed at the second metal layer M2. The array substrate 10 further includes a semiconductor layer poly disposed on a side of the first metal layer M1 facing the substrate 00 and an auxiliary metal layer M0 disposed on a side of the semiconductor layer poly facing the substrate 00, and it should be noted that the display panel may include a transistor with a dual-gate structure, and at this time, one gate of the transistor may be located on the first metal layer M1 and the other gate may be located on the auxiliary metal layer M0. Along the direction perpendicular to the plane of the substrate 00, the first metal layer M1 and the auxiliary metal layer M0 overlap with the semiconductor layer poly, and the auxiliary metal layer M0 also has a light shielding effect to avoid light affecting the semiconductor layer poly. Optionally, a capacitor metal layer Mc is further included between the first metal layer M1 and the second metal layer M2, and the capacitor metal layer Mc may form a capacitor structure with the second metal layer M2. Optionally, the side of the second metal layer M2 facing away from the substrate 00 further includes a third metal layer M3, and an additional metal layer may be disposed on the side of the third metal layer M3 facing away from the substrate according to actual needs, which is not specifically limited in the present disclosure, and each metal layer may be configured with a signal line. Optionally, referring to fig. 5, the first scan line S1 and the second scan line S2 are located on the first metal layer M1, the first reset signal line Vref1 and the second reset signal line Vref2 are located on the capacitor metal layer Mc, and the data signal line DL and the first power signal line PVDD are located on the second metal layer M2, but the embodiment of the disclosure is not limited thereto.
Referring to fig. 5 and fig. 6, in an alternative embodiment of the disclosure, the gate of the driving transistor DT is electrically connected to the first node N1 through a first connection portion L1, the first connection portion L1 is disposed in a different layer from the second scan line S2, and the embodiment uses the first connection portion L1 located in the third metal layer M3 and the second scan line S2 located in the first metal layer M1 as an example, but not limited thereto. In the second direction D2, the first connection portion L1 overlaps the second scan line S2 to form a first overlapping region, the second direction D2 is perpendicular to the plane of the light emitting surface of the display panel, and in the first display region a11, the shielding portion 90 includes a first shielding portion 91, and in the second direction D2, the first shielding portion 91 overlaps the first overlapping region, and at least a portion of the first shielding portion 91 is located between the first connection portion L1 and the second scan line S2. Alternatively, the first shielding portion 91 is located on the capacitance metal layer Mc.
Since the first connection portion L1 is for connecting the gate of the driving transistor and the first node N1, the potential of the gate of the driving transistor DT, the potential of the first connection portion L1, and the potential of the first node N1 are equal. When the first connection portion L1 and the second scan line S2 are located in different film layers and overlap to form a first overlapping region, due to the coupling capacitance in the first overlapping region, the changed signal will be coupled to the first connection portion L1 when the second scan line S2 jumps, so as to affect the potential of the first connection portion L1 and thus the potential of the first node N1. Therefore, when the first shielding portion 91 is introduced into the first display area a11 of the display panel and the first shielding portion 91 overlaps the first overlapping area, the first shielding portion 91 can at least partially shield the transition signal of the second scan line S2, so as to avoid or reduce the influence of the transition signal on the electric potential on the first connection portion L1, and further avoid or reduce the influence of the transition signal on the electric potential on the first node N1, that is, reduce the influence of the second scan line S2 in the first display area a11 on the electric potential of the first node N1, and reduce the difference of the influence of the second scan line S2 in the first display area a11 and the second display area a12 on the first node N1, so that the difference of the electric potentials of the first node N1 in the first display area a11 and the second display area a12 in the light-emitting phase can be reduced, which is beneficial to reducing the difference of the display brightness of the first display area a11 and the second display area a12, and thus is beneficial to improving the uniformity of the display brightness of the first display area a11 and the second display area a 12.
Fig. 7 is a schematic diagram showing another layout of the pixel driving circuit 10 provided in the embodiment of the disclosure, please refer to fig. 7, in an alternative embodiment of the disclosure, the second scan line S2 includes a main body 81, the main body 81 extends along a third direction D3, the main body 81 and the first node N1 are arranged along the first direction D1, the third direction D3 intersects the first direction D1 and is parallel to a plane of the light emitting surface of the display panel, and in the first display area a11, the shielding portion 90 includes a second shielding portion 92, and along the first direction D1, the second shielding portion 92 is located between the first node N1 and the main body 81 of the second scan line S2.
In this embodiment, the shielding portion 90 is disposed in the first display area a11, when the main portion 81 of the second scan line S2 and the first node N1 are aligned along the first direction D1, which is equivalent to the first node N1 being located at one side of the main portion 81 of the second scan line S2 along the first direction D1, at this time, a lateral coupling capacitance exists between the main portion 81 of the second scan line S2 and the first node N1, and when the signal on the second scan line S2 jumps after the data writing stage, the potential of the first node N1 will change due to the influence of the lateral coupling capacitance. When the second shielding portion 92 is introduced into the main body portion 81 of the second scan line S2 toward one side of the first node N1 along the first direction D1, the second shielding portion 92 is located between the first node N1 and the main body portion 81, so that the second shielding portion 92 is utilized to isolate the jump signal on the main body portion 81 to a certain extent, thereby reducing the influence of the jump signal of the main body portion 81 of the second scan line S2 in the first display area a11 on the potential of the first node N1, and reducing the difference of the influence of the second scan line S2 in the first display area a11 and the second display area a12 on the first node N1, which is also beneficial to improving the uniformity of the display brightness of the first display area a11 and the second display area a 12.
Fig. 8 is another layout diagram of the pixel driving circuit 10 provided in the embodiment of the disclosure, which illustrates a scheme in which the shielding portion 90 in the first display area a11 includes the first shielding portion 91 and the second shielding portion 92 at the same time, referring to fig. 8, in an alternative implementation of the disclosure, when the shielding portion 90 includes the first shielding portion 91 and the second shielding portion 92, the first shielding portion 91 and the second shielding portion 92 are electrically connected and located at the same layer.
Specifically, when the first shielding portion 91 and the second shielding portion 92 are disposed on the same layer and electrically connected, the first shielding portion 91 and the second shielding portion 92 can be manufactured in the same manufacturing process, and different manufacturing processes are not required to be introduced into the first shielding portion 91 and the second shielding portion 92 respectively, so that the manufacturing process of the shielding portion 90 is simplified, the overall manufacturing process of the display panel is simplified, and the production efficiency is improved. In addition, when the first shielding portion 91 and the second shielding portion 92 are electrically connected in the same film layer, the shielding area of the shielding portion 90 can be increased, the shielding effect of the shielding portion 90 can be improved, and the potential influence of the second scanning line S2 on the first node N1 in the first display area a11 can be reduced.
The foregoing embodiment shows a scheme of introducing the shielding portion 90 between the first node N1 and the main portion 81 of the second scan line S2, and in some other embodiments of the present disclosure, the shielding portion 90 may also be introduced between the first node N1 and the extension portion 82 of the second scan line S2, for example, please refer to fig. 9 and 10, fig. 9 and 10 respectively show another layout schematic diagram of the pixel driving circuit 10 provided in the embodiment of the present disclosure, which describes a scheme of introducing the third shielding portion 93 in the first display area a 11. In an alternative embodiment of the disclosure, the second scan line S2 includes a main body 81 and an extension 82 connected to the main body 81, the main body 81 extends along a third direction D3, the third direction D3 intersects the first direction D1 and is parallel to a plane on which the light emitting surface of the display panel is located, the extension 82 extends along the first direction D1 and is located at a side of the main body 81 facing the first node N1, the main body 81 and the first node N1 are arranged along the first direction D1, and the extension 82 and the first node N1 are arranged along the third direction D3. The shielding portion 90 includes a third shielding portion 93, please refer to fig. 9, in which the third shielding portion 93 is located between the first node N1 and the extending portion 82 along the third direction D3, and at this time, the third shielding portion 93 may be embodied as an elongated structure disposed between the extending portion 82 and the first node N1 aligned along the third direction D3, and by introducing the third shielding portion 93 in this form, it is capable of shielding at least part of the influence of the signal hopped on the extending portion 82 on the first node N1, thereby reducing the difference of the influence of the second scan line S2 of the first display area a11 and the second display area a12 on the electric potential of the first node N1, and improving the uniformity of the display brightness of the first display area a11 and the second display area a 12.
Referring to fig. 10, the third shielding portion 93 includes a first sub-portion 931 and a second sub-portion 932 electrically connected, the first sub-portion 931 being located between the first node N1 and the extension portion 82 along the third direction D3, and the second sub-portion 932 being located between the first node N1 and the main portion 81 along the first direction D1. The present embodiment describes another possible structure of the third shielding portion 93, in which the extending portion 82 and the main body portion 81 form a vertical corner structure, the first node N1 is located at one side of the opening of the corner structure, the third shielding portion 93 may be regarded as an L-shaped structure disposed between the corner structure and the first node N1 along the shape of the corner structure, wherein the first sub-portion 931 may shield the influence of the extending portion 82 on the first node N1, the second sub-portion 932 may shield the influence of the main body portion 81 on the first node N1, and the shielding range of the shielding portion 90 is increased by the combined structure of the first sub-portion 931 and the second sub-portion 932, thereby being more advantageous to reduce the influence of the second scan line S2 in the first display area a11 on the potential of the first node N1, and thus being more advantageous to improve the display brightness difference of the first display area a11 and the second display area a 12. It should be noted that, while the embodiment of fig. 10 illustrates the arrangement of the first sub-portion 931 and the second sub-portion 932 on the auxiliary metal layer M0 of the display panel, this is not limited thereto, and in other embodiments of the present disclosure, the first sub-portion 931 and the second sub-portion 932 may be located on other metal layers.
It should be noted that, in the foregoing embodiments, several embodiments of the first shielding portion 91, the second shielding portion 92, and the third shielding portion 93 may be combined arbitrarily, for example, the first shielding portion 91 in the first display area a11 may be combined with the second shielding portion 92, may be combined with the third shielding portion 93, or may be separately present in an area corresponding to a certain pixel in the first display area a11, which is not specifically limited in the present disclosure.
Fig. 11 is a schematic diagram illustrating another layout of the pixel driving circuit 10 provided in the embodiment of the disclosure, in which the second scan line S2 includes a main body 81 and an extension 82 connected to the main body 81, the main body 81 extends along a third direction D3, the third direction D3 intersects the first direction D1 and is parallel to a plane of the light emitting surface of the display panel, the extension 82 extends along the first direction D1 and is located at a side of the main body 81 facing the first node N1, the main body 81 and the first node N1 are arranged along the first direction D1, the extension 82 and the first node N1 are arranged along the third direction D3, the shielding portion 90 includes a fourth shielding portion 94, and the fourth shielding portion 94 overlaps the extension 82 along a second direction perpendicular to the plane of the light emitting surface of the display panel.
The present embodiment describes another possible structure of the shielding portion 90, specifically, introducing the fourth shielding portion 94 into the upper film layer or the lower film layer of the extending portion 82 in the second scan line S2, so that the fourth shielding portion 94 overlaps the extending portion 82 of the second scan line S2, and since the fourth shielding portion 94 receives the fixed potential signal, when the fourth shielding portion 94 overlaps the extending portion 82, it is also beneficial to reduce the signal influence of the second scan line S2 on the first node N1, so as to reduce the influence difference of the second scan line S2 in the first display area a11 and the second display area a12 on the first node N1, thereby also beneficial to promote the uniformity of the display brightness of the first display area a11 and the second display area a 12.
In the above embodiment, the first shielding portion 91, the second shielding portion 92, the third shielding portion 93, and the fourth shielding portion 94 may be individually present in the pixel driving circuit 10 of the first display area a11, may be combined in any two or any three or four, may be simultaneously present in the same pixel driving circuit 10 of the first display area a11, and may be set according to actual needs, which is not particularly limited in the present disclosure.
With continued reference to fig. 2, in an alternative embodiment of the disclosure, the pixel driving circuit 10 includes a second reset module 76 (illustrated by including a transistor T2), two ends of the second reset module 76 are respectively connected to a second reset signal line Vref2 and a fourth node N4, the fourth node N4 is connected to an anode of the light emitting element 30, the second reset signal line Vref2 includes a main line 70 extending along a third direction D3 and a connection line 71 extending along a first direction D1, the main line 70 is electrically connected to the connection line 71, the third direction D3 intersects the first direction D1, the display panel includes a plurality of pixel driving circuits 10 arranged along the first direction D1, two main lines 70 are electrically connected to the connection line 71 in the second reset signal lines Vref2 corresponding to two adjacent pixel driving circuits 10 along the first direction D1, and the fourth shielding portion 94 is electrically connected to the connection line 71.
The present embodiment shows a scheme of multiplexing the film layer of the connection line 71 in the second reset signal line Vref2 as the fourth shielding portion 94, specifically, the second reset signal line Vref2 is a signal line that provides a reset signal to the second reset module 76 in the pixel driving circuit 10, and when the second reset module 76 is turned on, the reset signal can be transmitted to the anode of the light emitting element 30 to reset the anode of the light emitting element 30. Since the reset signal on the second reset signal line Vref2 is a global signal, that is, the signals for resetting the light emitting elements 30 in different areas are the same, in the embodiment of the disclosure, the second reset signal line Vref2 includes the main line 71 and the connecting line 71 which have different extending directions and are electrically connected, which is equivalent to setting the second reset signal line Vref2 to be a mesh structure, thus being beneficial to reducing the overall impedance of the second reset signal line Vref2, reducing the voltage drop of the reset signals in different areas, and being beneficial to improving the uniformity of resetting the light emitting elements 30 in different areas. When the fourth shielding portion 94 is introduced into the first display area a11, the embodiment of the disclosure connects the fourth shielding portion 94 with the connection line 71 in the second reset signal line Vref2, which is equivalent to extending from the connection line 71 along the third direction D3, and at this time, the fourth shielding portion 94 and the connection line 71 can be manufactured in the same manufacturing process, and no additional manufacturing process is required to be separately introduced into the fourth shielding portion 94, and the reset signal on the connection line 71 is multiplexed, so that the manufacturing process of the display panel is simplified and the production efficiency is improved.
Referring to fig. 2 and 5 to 11, in an alternative embodiment of the present disclosure, the display panel includes a fixed potential signal line (a possible fixed potential signal line will be described in the following examples), and the shielding portion 90 is electrically connected to the fixed potential signal line. When the shielding portion 90 is connected to an existing fixed potential signal line in the display panel, a new signal line is not required to be separately introduced into the shielding portion 90 to provide a fixed potential signal to the shielding portion 90, and the existing fixed potential signal line is utilized to provide a fixed potential to the shielding portion 90, so that the whole design of the display panel when the shielding portion 90 is introduced into the display panel is simplified, and the production efficiency of the display panel is improved.
A scheme of supplying the fixed potential signal to the shielding portion 90 using the fixed potential signal in the display panel will be described in detail as follows.
Fig. 12 is another connection schematic diagram of the pixel driving circuit 10 and the light emitting element 30 in the display panel, which is different from fig. 2 in that a bias module is introduced into the pixel driving circuit 10, referring to fig. 2 and 12, in an alternative embodiment of the disclosure, the pixel driving circuit 10 includes a second reset module 76 and a bias module 77, two ends of the second reset module 76 are respectively connected to a second reset signal line Vref2 and a fourth node N4, the fourth node N4 is connected to an anode of the light emitting element 30, two ends of the bias module 77 are respectively connected to a bias signal line DVH and a second node N2, or two ends of the bias module 77 are respectively connected to a bias signal line DVH and a third node N3, which is described by taking the bias module 77 connected to the third node N3 as an example. The display panel further includes a power signal line including one of a power signal line, a first reset signal line Vref1, a second reset signal line Vref2, and a bias signal line DVH, and the shielding portion 90 is provided in the same layer as the fixed potential signal line electrically connected thereto.
For the pixel driving circuit 10, the signal lines connected thereto capable of transmitting a fixed potential signal include a first reset signal line Vref1 transmitting a reset signal to the first reset block 71, a second reset signal line Vref2 transmitting a reset signal to the second reset block 76, power supply signal lines PVDD and PVEE necessary for light emission, and a bias signal line DVH supplying a bias potential signal to the bias block 77, wherein the power supply signal lines further include a positive power supply signal line PVDD and a negative power supply signal line PVEE. When the shielding portion 90 is introduced into the first display area a11, the shielding portion 90 may be electrically connected to any one of the fixed potential signal lines described above, and a corresponding fixed potential signal may be used as a shielding signal to be supplied to the shielding portion 90. The embodiment shown in fig. 10 and 11 illustrates a scheme of electrically connecting the shielding portion 90 with the second reset signal line Vref2, and the embodiment shown in fig. 7 and 8 illustrates a scheme of electrically connecting the shielding portion 90 with the power signal line PVDD, in some other embodiments of the present disclosure, the shielding portion 90 may be further electrically connected with the bias signal line DVH, and in the actual connection, the shielding portion 90 and the corresponding fixed potential signal line may be disposed in the same layer, which is equivalent to forming a part of the extension portion 82 as the shielding portion 90 on the basis of the original fixed potential signal line, and the shielding portion 90 and the fixed potential signal line need not be connected through a via hole, and may be formed in the same process with the corresponding fixed potential signal line, thereby being beneficial to simplifying the overall manufacturing process of the display panel.
Referring to fig. 1, in an alternative embodiment of the disclosure, a first display area a11 includes a first sub-area a01 and a second sub-area a02 arranged along a first direction D1, the first sub-area a01 is located between the second sub-area a02 and a binding area A2, and a projection area of a shielding portion 90 corresponding to a pixel driving circuit 10 in the first sub-area a01 on a plane of a light emitting surface of a display panel is larger than a projection area of a shielding portion 90 corresponding to the pixel driving circuit 10 in the second sub-area a02 on a plane of the light emitting surface of the display panel. The first sub-area a01 in the first display area a11 may be regarded as an area closer to the binding area A2, and the second sub-area a02 is further away from the binding area A2 than the first sub-area a01, so that the voltage drop on the second scanning line S2 in the first sub-area a01 is smaller than the voltage drop on the second scanning line S2 in the second sub-area a02, when signal jump occurs, the signal influence of the second scanning line S2 in the first sub-area a01 on the first node N1 is greater than the signal influence of the second scanning line S2 in the second sub-area a02 on the first node N1, so that the area of the shielding part 90 in the first sub-area a01 is greater than the area of the shielding part 90 in the second sub-area a02, in the embodiment of the present disclosure, the influence of the second scanning line S2 in the first sub-area a01 on the first node N1 is balanced, the luminance uniformity of the first sub-area a01 and the second sub-area a02 is beneficial to the improvement of the luminance display of the first sub-area a01 and the luminance display panel. When the shielding portions 90 in the second sub-area a02 and the first sub-area a01 are differently designed, the shielding portions 90 in the first sub-area a01 may employ, for example, a structure as shown in fig. 8 (the area of the shielding portion 90 is larger), and the shielding portions 90 in the second sub-area a02 may employ a structure as shown in fig. 7, which is not particularly limited by the present disclosure. The first sub-area a01 and the second sub-area a02 in the drawing are only schematic, and the number of pixel circuit rows actually included in the first sub-area a01 and the second sub-area a02 is not limited.
Based on the same inventive concept, the disclosure further provides a display device 200, fig. 13 is a schematic structural diagram of the display device 200 provided in the embodiment of the disclosure, and referring to fig. 13, the display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in the embodiments of the present disclosure may be any electronic device with a display function, such as a tablet computer with touch and display functions, a display product for a showcase, a television, or a vehicle-mounted display device. The display device 200 provided in the embodiments of the present disclosure has the beneficial effects of the display panel 100 provided in the embodiments of the present disclosure, and the specific description of the display panel 100 in the embodiments described above may be referred to specifically, and the description of the embodiment is omitted here.
It is to be understood that fig. 13 illustrates the display device in a rectangular configuration only, and that in some other embodiments of the present disclosure, the display device 200 may also be embodied as a circular, rounded rectangular, oval, or any other feasible shape, which is not specifically limited in this disclosure.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (19)
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