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CN119415450A - Base address register resource management method, electronic device and medium - Google Patents

Base address register resource management method, electronic device and medium Download PDF

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Publication number
CN119415450A
CN119415450A CN202510020725.5A CN202510020725A CN119415450A CN 119415450 A CN119415450 A CN 119415450A CN 202510020725 A CN202510020725 A CN 202510020725A CN 119415450 A CN119415450 A CN 119415450A
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address register
base address
peripheral device
interconnection
shortcut
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CN202510020725.5A
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CN119415450B (en
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胡培培
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Zhuhai Xingyun Zhilian Technology Co Ltd
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Zhuhai Xingyun Zhilian Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Small-Scale Networks (AREA)

Abstract

The application relates to the technical field of computers and provides a base address register resource management method, electronic equipment and a medium. The method is used for solving the problem of insufficient reservation of the base address register resource caused by hot plug, responding to detection of the in-place interconnection link of the shortcut peripheral devices, creating virtual equipment as occupying equipment to reserve the base address register resource, limiting the zero base address register space contained in the virtual equipment to be the first base address register space and the size thereof, and deleting the virtual equipment after the configuration of the last base address register space is determined, so that the integrity of the whole process of scanning and distributing the base address register resource of the basic input and output system is ensured, the processing flow of the basic input and output system of different manufacturers can be adapted, the requirements of various types of interconnection equipment of the shortcut peripheral devices of different manufacturers can be flexibly adapted, the hot plug function which is not perceived by the system is realized, and the system stability is ensured.

Description

Base address register resource management method, electronic equipment and medium
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method for managing a base address register resource, an electronic device, and a medium.
Background
In application scenarios such as high-performance computers, data centers, cloud computing, etc., heterogeneous computing related technologies are widely adopted, so that a large number of devices of different types are bus-connected through bus standards defined by peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) and Peripheral Component Interconnect Express (PCIE). Therefore, the PCI device and the PCIE device which are connected based on the PCI bus and the PCIE bus realize hot plug in a non-accidental (no surprise) mode, namely, the user is allowed to insert the device or remove the device under the condition that the user does not notify the system software in advance. For device expansion, a Base address register (Base ADDRESS REGISTER, BAR) resource of a PCIE end device mounted under a PCIE Bridge device (PCIE Bridge) is configured through the PCIE Bridge device, so that the PCIE end device can perform data uplink and downlink operations, interrupt operations and the like through a bus. In the prior art, a base address register resource management scheme is to scan PCIE end devices mounted under PCIE bridge devices and allocate BAR resources through a basic input output system (Basic Input Output System, BIOS) in a system starting and scanning PCIE topology stage. However, the hot plug is realized by an unintentional mode, which means that when the BIOS scans PCIE bridge devices in a system startup and scanning PCIE topology stage, PCIE bridge devices may not be mounted under PCIE bridge devices, but then new PCIE end devices may be added to PCIE bridge devices by a hot plug mode in an operating system stage, so that the BIOS does not reserve BAR resources for the newly added PCIE end devices, and therefore, startup items of the operating system need to be modified to reallocate BAR resources, which is not beneficial to improving overall system efficiency.
Therefore, the application provides a base address register resource management method, electronic equipment and medium, which are used for solving the technical problem of insufficient base address register resource reservation caused by hot plug.
Disclosure of Invention
In a first aspect, the present application provides a method for managing a base address register resource. The base address register resource management method comprises the steps of responding to detection that a shortcut peripheral device interconnection link associated with a shortcut peripheral device interconnection bridge device is in place, determining whether idle shortcut peripheral device interconnection end devices exist under each downlink port connected with an uplink port of the shortcut peripheral device interconnection bridge device, determining an idle shortcut peripheral device interconnection end device set associated with the shortcut peripheral device interconnection bridge device, establishing virtual devices only comprising a zero-th base address register space and mounting the virtual devices to the downlink port corresponding to the idle shortcut peripheral device interconnection end device, wherein the zero-th base address register space is a first base address register space in a plurality of base address register spaces defined by shortcut peripheral device interconnection standards associated with the shortcut peripheral device interconnection bridge device, aiming at each idle shortcut peripheral device interconnection end device in the idle shortcut peripheral device interconnection end device set, establishing that the virtual devices only comprise a zero-th base address register space are small in the idle peripheral device interconnection end device, configuring the virtual devices corresponding to the largest peripheral device interconnection end devices, and deleting the virtual devices corresponding to the largest base address register of the shortcut peripheral device interconnection end devices, completing configuration of the virtual devices and completing the configuration of the peripheral device interconnection end devices, and setting reply of the transaction layer data packet message destined for the virtual equipment as request unsupported.
According to the application, in response to detection of insufficient reservation of the base address register resource caused by hot plug, virtual equipment is created as a space occupying equipment to reserve the base address register resource, the zero base address register space contained in the virtual equipment is defined as the first base address register space and the size thereof, and the virtual equipment is deleted after the configuration of the last base address register space is determined, so that the integrity of the whole process of scanning and distributing the base address register resource of a basic input/output system is ensured, the processing flow of basic input/output systems of different manufacturers can be adapted, the requirements of various types of quick peripheral device interconnection end equipment of different manufacturers can be flexibly adapted, the hot plug function which is not perceived by the system is realized, and the system stability is ensured.
In a possible implementation manner of the first aspect of the present application, all types of shortcut peripheral device interconnection devices supported by the shortcut peripheral device interconnection bridge device include a shortcut peripheral device interconnection device of a network device type, a shortcut peripheral device interconnection device of a storage device type, and a shortcut peripheral device interconnection device of a remote direct memory access device type.
In a possible implementation manner of the first aspect of the present application, the size of the maximum base address register space in all types of shortcut peripheral device interconnect devices supported by the shortcut peripheral device interconnect bridge device is determined based on the maximum base address register resources required by all types of shortcut peripheral device interconnect devices supported by the shortcut peripheral device interconnect bridge device.
In a possible implementation manner of the first aspect of the present application, when a configuration transaction layer packet corresponding to a last base address register space in the plurality of base address register spaces associated with the virtual device is received, it is determined that the configuration of the last base address register space in the plurality of base address register spaces associated with the virtual device is completed.
In a possible implementation manner of the first aspect of the present application, the bios associated with the peripheral device interconnect bridge device scans a plurality of base address register spaces associated with devices mounted under each of the downstream ports connected to the upstream ports of the peripheral device interconnect bridge device in a stage of scanning a peripheral device interconnect topology, and allocates the base address register resources required for each of the plurality of base address register spaces one by one in an order from a first base address register space of the plurality of base address register spaces to a last base address register space of the plurality of base address register spaces.
In a possible implementation manner of the first aspect of the present application, the virtual device is created before the bios scans a downstream port corresponding to the idle peripheral device interconnect device, the bios allocates a base address register resource according to a size of the zeroth base address register space included in the virtual device, and the virtual device is deleted after the bios scans a last base address register space of a plurality of base address register spaces associated with the virtual device.
In a possible implementation manner of the first aspect of the present application, the method for managing a base address register resource further includes not creating the virtual device when there is no idle shortcut peripheral device interconnect end device under each downlink port connected to an uplink port of the shortcut peripheral device interconnect bridge device.
In a possible implementation manner of the first aspect of the present application, the plurality of base address register spaces defined by the peripheral device shortcut interconnection standard are, in order, the zeroth base address register space, a first base address register space, a second base address register space, a third base address register space, a fourth base address register space, and a fifth base address register space, where the fifth base address register space is a last base address register space of the plurality of base address register spaces defined by the peripheral device shortcut interconnection standard.
In a possible implementation manner of the first aspect of the present application, when the configuration of the last base address register space in the plurality of base address register spaces associated with the virtual device is completed, a base address register resource determined based on the size of the zeroth base address register space included in the virtual device is reserved for a downstream port corresponding to the idle peripheral device interconnection device, so as to be used for hot plug of a device under the downstream port corresponding to the idle peripheral device interconnection device.
In a possible implementation manner of the first aspect of the present application, the virtual device is created before the bios associated with the peripheral device express interconnection bridge device scans the peripheral device express interconnection topology stage, and the virtual device is deleted at least before the os stage, and during the os stage, the os does not perceive a device hot plug under the downstream port corresponding to the peripheral device express interconnection side device.
In a possible implementation manner of the first aspect of the present application, the base address register resource management method further includes deleting a virtual device under a downlink port corresponding to each idle peripheral device interconnect in the idle peripheral device interconnect device set in response to detecting that the peripheral device interconnect link is not in place.
In a possible implementation manner of the first aspect of the present application, the shortcut peripheral device interconnection bridge device and the shortcut peripheral device interconnection end device mounted under the shortcut peripheral device interconnection bridge device are generated by simulation by a simulator at an embedded central processor side of the data processor.
In a possible implementation manner of the first aspect of the present application, when any shortcut peripheral device interconnection end device is not mounted under any downlink port connected to an uplink port of the shortcut peripheral device interconnection bridge device, it is determined that an idle shortcut peripheral device interconnection end device exists under any downlink port.
In a second aspect, embodiments of the present application further provide a computer device, the computer device including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing a method according to any one of the implementations of any one of the above aspects when the computer program is executed.
In a third aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.
In a fourth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for managing a base address register resource according to an embodiment of the present application;
Fig. 2 is a schematic diagram of PCIE bridge device according to an embodiment of the present application, where the PCIE bridge device refers to the base address register resource management method shown in fig. 1;
fig. 3 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
It should be understood that in the description of the application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.
Fig. 1 is a flow chart of a method for managing a base address register resource according to an embodiment of the present application. As shown in fig. 1, the base address register resource management method includes the following steps.
Step S101, in response to detecting that a shortcut peripheral device interconnection link associated with a shortcut peripheral device interconnection bridge device is in place, determining whether an idle shortcut peripheral device interconnection end device exists under each downlink port connected with an uplink port of the shortcut peripheral device interconnection bridge device, thereby determining an idle shortcut peripheral device interconnection end device set associated with the shortcut peripheral device interconnection bridge device.
Step S103, for each free peripheral device interconnection end device in the free peripheral device interconnection end device set, creating a virtual device only comprising a zero-th base address register space and mounting the virtual device to a downlink port corresponding to the free peripheral device interconnection end device, wherein the zero-th base address register space is a first base address register space in a plurality of base address register spaces defined by a peripheral device interconnection standard associated with the peripheral device interconnection bridge device, the size of the zero-th base address register space contained in the virtual device is the size of the largest base address register space in all types of peripheral device interconnection end devices supported by the peripheral device interconnection bridge device, and then, after the configuration of the last base address register space in the plurality of base address register spaces associated with the virtual device is determined to be completed, deleting the virtual device and configuring the peripheral device interconnection bridge device to reply to the corresponding port of the peripheral device interconnection end device, and requesting the peripheral device interconnection end device is not carried by the peripheral device interconnection end, and the peripheral device interconnection end device is not requested to be the downlink port.
The base address register resource management method shown in fig. 1 can be applied to application scenes such as high-performance computers, data centers and cloud computing, can be applied to various technologies such as heterogeneous computing, virtualization and paravirtualization, can meet the requirements of user-customized input and output by performing bus connection on a large number of devices of different types through bus standards defined by peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) and Peripheral Component Interconnect Express (PCIE), and can support hot plug in a non-unexpected (no surprise) manner, namely, allows a user to insert devices or remove devices without informing system software in advance. The host computer system sequentially goes through a system starting stage and an operating system stage after being started. In a system starting stage, also called a scanning shortcut peripheral device interconnection topology stage, a shortcut peripheral device interconnection end device under shortcut peripheral device interconnection bridge equipment is scanned through a basic input output system (Basic Input Output System, BIOS) and a Base address register (Base ADDRESS REGISTER, BAR) resource is allocated, so that the shortcut peripheral device interconnection end device utilizes the allocated Base address register resource to carry out uplink and downlink data transmission, interrupt operation and the like through a bus. After the system starting stage, namely the stage of scanning the interconnection topology of the shortcut peripheral devices, the operating system starts, enters the operating system stage, and the operating system uses the basic input and output system to scan the result of the interconnection topology of the shortcut peripheral devices by default. Therefore, by implementing the hot plug in an unintentional manner, if enough base address register resources are not allocated in the stage of scanning the shortcut peripheral device interconnection topology, even no base address register resources are allocated at all, the shortcut peripheral device interconnection end equipment newly added through the hot plug may lack suitable base address register resources to run, and therefore, the startup item of the operating system is required to allocate the base address register resources again, which is not beneficial to improving the overall system efficiency. In view of the fact that devices are added, deleted, or replaced by means of inadvertent hot plug, this means that at the operating system stage, the operating system and system software have difficulty in predicting the need for new devices that may be added by hot plug, while various different types of devices may have different base address register resource needs, and the host may have limited overall base address register resources, which may be subject to the host, and may need to optimize overall resource utilization while also minimizing the problem of insufficient resource reservation. The following details with reference to fig. 1, how the method for managing the base address register resource shown in fig. 1 implements a hot plug function that is not perceived by the system, and can flexibly adapt to requirements of various types of shortcut peripheral device interconnection devices of different manufacturers, and flexibly adapt to system start flows of various basic input/output systems of different manufacturers and operation characteristics of a scanning shortcut peripheral device interconnection topology stage.
Referring to fig. 1, in step S101, in response to detecting that a shortcut peripheral device interconnection link associated with a shortcut peripheral device interconnection bridge apparatus is in place, it is determined whether an idle shortcut peripheral device interconnection end apparatus exists under each downlink port connected to an uplink port of the shortcut peripheral device interconnection bridge apparatus, thereby determining an idle shortcut peripheral device interconnection end apparatus set associated with the shortcut peripheral device interconnection bridge apparatus. Here, the shortcut peripheral device interconnect link associated with the shortcut peripheral device interconnect bridge apparatus means that a signal that the link of the host side is in place is detected. In the normal starting process of the server, the PCI express link, namely the PCIE link, is electrified, so that the PCI express link can be detected in place by detecting the electrified signal of the PCI express link. When the shortcut peripheral device interconnection link is in place, the basic input/output system starts to work, namely enters a system starting stage, namely a shortcut peripheral device interconnection topology scanning stage, and the shortcut peripheral device interconnection end equipment under the shortcut peripheral device interconnection bridge equipment is scanned through the basic input/output system and the basic address register resource is allocated. In step S101, in response to detecting that the shortcut peripheral device interconnection link associated with the shortcut peripheral device interconnection bridge apparatus is in place, it is determined whether an idle shortcut peripheral device interconnection end apparatus exists under each downlink port connected to the uplink port of the shortcut peripheral device interconnection bridge apparatus, so as to determine an idle shortcut peripheral device interconnection end apparatus set associated with the shortcut peripheral device interconnection bridge apparatus. This means that when no shortcut peripheral device interconnection end device is mounted under a certain downlink port, an idle shortcut peripheral device interconnection end device exists under the downlink port, so that an idle shortcut peripheral device interconnection end device set associated with the shortcut peripheral device interconnection bridge device can be determined. In other words, by traversing each downlink port connected to the uplink port of the peripheral shortcut interconnection bridge device, it can be determined whether a peripheral shortcut interconnection device is mounted under each downlink port, if no peripheral shortcut interconnection device is mounted, it means that there is an idle peripheral shortcut interconnection device, so that all idle peripheral shortcut interconnection devices can be recorded by the idle peripheral interconnection device set associated with the peripheral shortcut interconnection bridge device for subsequent flow of reserving the base address register resource. If any He Kongxian shortcut peripheral device interconnection end device is not detected after traversing each downlink port connected with the uplink port of the shortcut peripheral device interconnection bridge device, which means that shortcut peripheral device interconnection end devices are mounted under all downlink ports, then the subsequent process of reserving the base address register resource is not required to be continuously executed.
With continued reference to fig. 1, in step S103, for each idle shortcut peripheral device interconnection end device in the idle shortcut peripheral device interconnection end device set, a virtual device only including a zeroth base address register space is created and mounted under a downlink port corresponding to the idle shortcut peripheral device interconnection end device. The zeroth base address register space is the first base address register space in a plurality of base address register spaces defined by a shortcut peripheral device interconnection standard associated with the shortcut peripheral device interconnection bridge equipment, and the size of the zeroth base address register space contained in the virtual equipment is the size of the largest base address register space in all types of shortcut peripheral device interconnection end equipment supported by the shortcut peripheral device interconnection bridge equipment. Here, for each idle peripheral component interconnect device, i.e. for each downstream port under which no peripheral component interconnect device is mounted, a virtual device (dummy) is created, which is used for occupying, i.e. reserving, the base address register resource. It should be appreciated that creating the virtual device occurs prior to the scan shortcut interconnect topology stage, and therefore, the bios scans for the created virtual device and allocates base address register resources for the virtual device. Here, since the virtual device only includes the zeroth base address register space, the other base address register spaces of the virtual device are empty, which means that the base input output system scans the zeroth base address register space included in the virtual device to determine the size of the zeroth base address register space and allocate corresponding base address register resources, so that the base address register resources allocated to the virtual device are the size corresponding to the largest base address register space in all types of shortcut peripheral interconnection devices supported by the shortcut peripheral interconnection bridge device. Here, since the zeroth base address register space is the first base address register space among the base address register spaces defined by the shortcut peripheral device interconnection standard associated with the shortcut peripheral device interconnection bridge apparatus, the bios scans the first base address register space, that is, the zeroth base address register space, when scanning the plurality of base address register spaces, so that it is ensured that the bios allocates a base address register resource corresponding to the size of the zeroth base address register space to the created virtual apparatus in the stage of scanning the shortcut peripheral device interconnection topology.
With continued reference to fig. 1, after the virtual device is created and mounted under the downlink port corresponding to the idle peripheral device interconnect device in step S103, at least after it is determined that the configuration of the last base address register space in the plurality of base address register spaces associated with the virtual device is completed, the virtual device is deleted and the peripheral device interconnect bridge device is configured not to mount the peripheral device interconnect device under the downlink port corresponding to the idle peripheral device interconnect device any more, and a reply of a Transaction layer packet (Transaction LAYER PACKET, TLP) message destined for the virtual device is set to be unsupported. here, at least after determining that the configuration of the last base address register space of the plurality of base address register spaces associated with the virtual device is completed, this means that the basic input output system has scanned the plurality of base address register spaces associated with the virtual device and scanned the last base address register space and the configuration is completed. Therefore, the zeroth base address register space is the first base address register space in a plurality of base address register spaces defined by the shortcut peripheral device interconnection standard associated with the shortcut peripheral device interconnection bridge apparatus, and after the configuration of the last base address register space in the plurality of base address register spaces associated with the virtual apparatus is determined, the basic input/output system is ensured to scan all the plurality of base address register spaces, so that the requirements of various types of shortcut peripheral device interconnection end apparatuses of different manufacturers are flexibly adapted, and the system start-up flow of various basic input/output systems of different manufacturers and the operation characteristics of the scanning shortcut peripheral device interconnection topology stage are also adapted. for example, the PCIE protocol specifies that each PCIE device may have 6 BAR spaces numbered BAR0 through BAR5. Depending on the specific device requirements and the system boot flow of the BIOS, some PCIE devices may occupy BAR0 and BAR1, and some PCIE devices may occupy BAR0 through BAR3, so the number of these six BAR spaces each PCIE device occupies and the size of each BAR space may be set based on the PCIE device's own requirements and user-customized requirements. Moreover, the BIOS employed, i.e., the system start-up flow of the BIOS, may be different for servers, hosts, systems, etc. of different vendors. Therefore, in order to ensure that the created virtual device can successfully reserve the designed base address register resource, by defining that the zero-th base address register space is the first base address register space in the base address register spaces defined by the shortcut peripheral device interconnection standard associated with the shortcut peripheral device interconnection bridge device, it is ensured that the basic input/output system must read the information of the first base address register space, i.e. the zero-th base address register space (BAR 0), when scanning to the virtual device, so as to allocate the base address register resource corresponding to the size of the largest base address register space in all types of shortcut peripheral device interconnection devices supported by the shortcut peripheral device interconnection bridge device, and then, by defining that at least after the configuration of the last base address register space in the base address register spaces associated with the virtual device is completed, deleting the virtual device, it means that after all the base address register spaces (for example, from BAR0 to BAR 5) are completed, that is also the basic input/output system is not completely configured, i.e. the basic input/output system is ensured that the basic input/output system is not completely matched with the basic input system, and the basic input/output system is completely completed.
With continued reference to fig. 1, at least after determining that the configuration of the last base address register space of the plurality of base address register spaces associated with the virtual device is completed, deleting the virtual device and configuring the shortcut peripheral device interconnection bridge device to no longer mount the shortcut peripheral device interconnection end device under the downlink port corresponding to the idle shortcut peripheral device interconnection end device, and setting that the reply of the transaction layer packet message destined for the virtual device is not supported. By configuring the shortcut peripheral device interconnection bridge device to no longer mount the shortcut peripheral device interconnection end device under the downlink port corresponding to the idle shortcut peripheral device interconnection end device, the reserved base address register resource is ensured not to be occupied, and the design purpose is met, namely, the base address register resource with the size equivalent to the maximum base address register space in all types of shortcut peripheral device interconnection end devices supported by the shortcut peripheral device interconnection bridge device is reserved. Here, the maximum base address register space in all types of shortcut peripheral device interconnect-side apparatuses supported by the shortcut peripheral device interconnect bridge apparatus is the size of the maximum base address register space. For example, all types of shortcut peripheral interconnection devices supported by the shortcut peripheral interconnection bridge device include a network device type, a storage device type and a remote direct memory access device type, and it is assumed that a size of a base address register space required by the shortcut peripheral interconnection device of the network device type is 16 gigabytes (KB), a size of a base address register space required by the shortcut peripheral interconnection device of the storage device type is 16KB, and a size of a base address register space required by the shortcut peripheral interconnection device of the remote direct memory access device type is 32KB. The size of the maximum base address register space in all types of peripheral device interconnect devices supported by the peripheral device interconnect bridge device is the size of the base address register space required by the peripheral device interconnect device of the remote direct memory access device type, i.e., 32KB. By defining that the size of the zero-th base address register space contained in the virtual device is the size of the largest base address register space in all types of peripheral device interconnection end devices supported by the peripheral device interconnection bridge device, by creating the virtual device and distributing base address register resources for the created virtual device, the base address register resources corresponding to the size of the largest base address register space in all types of peripheral device interconnection end devices supported by the peripheral device interconnection bridge device are reserved under the downlink port corresponding to the idle peripheral device interconnection end device. the benefit of this design is that it allows, at a subsequent operating system stage, the user to select, from among all types of shortcut peripheral device interconnect-side devices supported by the shortcut peripheral device interconnect bridge device, selecting any type of peripheral device interconnect device, e.g. from the network device type, The storage device type and one of the remote direct memory access device types are arbitrarily selected, so that the selected device or device type can be added under a downlink port corresponding to the idle peripheral device interconnection end device in a hot plug mode, and the reserved base address register resource is ensured to be enough to support the operation of newly added devices, thereby realizing the hot plug under the condition that a system is not aware, flexibly adapting to the requirements of various types of peripheral device interconnection end devices of different manufacturers, and flexibly adapting to the system starting flow of various basic input/output systems of different manufacturers and the operation characteristics of the scanning peripheral device interconnection topology stage.
With continued reference to fig. 1, a reply to a transaction layer packet message destined for the virtual device is set to be unsupported by the request. This means that, on the basis that the shortcut peripheral device interconnection bridge device is configured to no longer mount the shortcut peripheral device interconnection end device under the downlink port corresponding to the idle shortcut peripheral device interconnection end device, for example, by configuring a status register of the shortcut peripheral device interconnection bridge device to indicate that any shortcut peripheral device interconnection end device is not mounted under the shortcut peripheral device interconnection bridge device, further, for all received transaction layer data packet messages destined for the virtual device, a reply to an unsupported request (Unsupported Request) message is required, that is, a reply is set to be uniformly unsupported. The advantage of this design is that, on the basis of reserving the base address register resource by using the virtual device as the occupying device, in order to avoid the occupying device from affecting the normal data service, the TLP destined for the virtual device is uniformly replied with the unsupported request, thereby ensuring the system stability.
In summary, the method for managing the base address register resources shown in fig. 1 is faced with the problem of insufficient reservation of the base address register resources caused by hot plug, in response to detecting that the interconnection link of the peripheral devices is in place, virtual devices are created as occupying devices to reserve the base address register resources, the zero-th base address register space contained in the virtual devices is defined to be the first base address register space and the size thereof, and the virtual devices are deleted after the configuration of the last base address register space is determined to be completed, so that the integrity of the whole process of scanning and distributing the base address register resources by the basic input/output system is ensured, the processing flow of the basic input/output system of different manufacturers can be adapted, the requirements of various types of interconnection devices of the peripheral devices of different manufacturers can be flexibly adapted, the hot plug function which is not perceived by the system is realized, and the system stability is ensured.
Fig. 2 is a schematic diagram of PCIE bridge equipment according to an embodiment of the present application, where the PCIE bridge equipment refers to a base address register resource management method shown in fig. 1. As shown in fig. 2, the root port 203 of the host 201 is connected to the upstream port 220 of the shortcut peripheral device interconnection bridge device 210, and a plurality of downstream ports, namely, a downstream port a230, a downstream port B232, a downstream port C234 and a downstream port D236, are further connected through the upstream port 220. Here, the shortcut peripheral device interconnection bridge device 210 is a PCIE bridge device referring to the base address register resource management method shown in fig. 1. The mounting conditions of the downstream ports are different. Wherein the downstream port a230 downloads the network device 240. No shortcut peripheral device interconnection end equipment is mounted under the downlink port B232, so that an idle shortcut peripheral device interconnection end equipment exists under the downlink port B232, and for this purpose, a virtual device a242 is created and a virtual device a242 is mounted under the downlink port B232. The downstream port C234 has a block device 244 (BLK) mounted thereon, where the block device 244 may be a storage device generated based on a virtualization technology, such as a virtio-BLK device generated based on virtio technology. The block device 244 may be generated by an Embedded CPU (ECPU) side simulator of a data processor (data processing unit, DPU), such as a Quick Emulators (QEMU). No shortcut peripheral device interconnect device is mounted under the downstream port D236, and therefore, there is an idle shortcut peripheral device interconnect device under the downstream port D236, for which purpose, the virtual device B246 is created and the virtual device B246 is mounted under the downstream port D236. It can be seen that, in combination with various virtualization technologies and paravirtualization technologies, the shortcut peripheral interconnection bridge device 210 may be a shortcut peripheral interconnection device with a physical entity, or a virtual device generated by simulation, or a virtual device a242 and a virtual device B246 created by referring to the base address register resource management method shown in fig. 1 and specially used for reserving base address register resources for an idle shortcut peripheral interconnection device.
In the PCIE bridge device shown in fig. 2, in response to detecting that the fast peripheral device interconnection link is in place, the PCIE bridge device creates virtual devices (virtual device a242 and virtual device B246) as occupying devices to reserve the base address register resource, defines the zeroth base address register space contained in the virtual devices (virtual device a242 and virtual device B246) as the first base address register space and the size thereof, and then defines that the virtual devices (virtual device a242 and virtual device B246) are deleted after the configuration of the last base address register space is determined to be completed, so that the integrity of the whole process of scanning and distributing the base address register resource by the bios is ensured, the processing flow of the bios of different manufacturers can be adapted, the requirements of various types of fast peripheral device interconnection devices of different manufacturers can be flexibly adapted, the system-unaware hot-plug function is realized, and the system stability is ensured.
Referring to fig. 1 and 2, in one possible implementation manner, all types of shortcut peripheral device interconnection devices supported by the shortcut peripheral device interconnection bridge device include a shortcut peripheral device interconnection device of a network device type, a shortcut peripheral device interconnection device of a storage device type, and a shortcut peripheral device interconnection device of a remote direct memory access device type. Thus, the requirements of various types of shortcut peripheral device interconnection terminal equipment of different manufacturers are flexibly adapted.
In one possible implementation, the size of the maximum base address register space in all types of peripheral device interconnect express supported by the peripheral device interconnect express bridge device is determined based on the maximum base address register resources required by all types of peripheral device interconnect express supported by the peripheral device interconnect express bridge device. In this way, by defining the size of the zeroth base address register space included in the virtual device to be the size of the largest base address register space in all types of peripheral device interconnect devices supported by the peripheral device interconnect bridge device, by creating a virtual device and allocating base address register resources to the created virtual device, it is achieved that base address register resources corresponding to the size of the largest base address register space in all types of peripheral device interconnect devices supported by the peripheral device interconnect bridge device are reserved under the downstream port corresponding to the free peripheral device interconnect device. The design has the advantages that in the subsequent operation system stage, any type of shortcut peripheral device interconnection terminal equipment is selected from all types of shortcut peripheral device interconnection terminal equipment supported by the shortcut peripheral device interconnection bridge equipment, for example, one equipment type is arbitrarily selected from network equipment types, storage equipment types and remote direct memory access equipment types, the selected equipment or equipment type can be added under a downlink port corresponding to the idle shortcut peripheral device interconnection terminal equipment in a hot plug mode, reserved base address register resources are ensured to be enough to support the operation of newly added equipment, hot plug under no perception of the system is realized, and the requirements of various types of shortcut peripheral device interconnection terminal equipment of different manufacturers and the operation characteristics of the system start flow and the scanning shortcut peripheral device interconnection stage of various basic input/output systems of different manufacturers can be flexibly adapted.
In one possible implementation, when a configuration transaction layer packet corresponding to a last base address register space of the plurality of base address register spaces associated with the virtual device is received, it is determined that the configuration of the last base address register space of the plurality of base address register spaces associated with the virtual device is completed. In this way, in order to ensure that the created virtual device can successfully reserve the designed base address register resource, by defining that the zero-th base address register space is the first base address register space in the base address register spaces defined by the shortcut peripheral device interconnection standard associated with the shortcut peripheral device interconnection bridge device, it is ensured that the basic input/output system must read the information of the first base address register space, i.e. the zero-th base address register space (BAR 0), when scanning to the virtual device, so as to allocate the base address register resource corresponding to the size of the largest base address register space in all types of shortcut peripheral device interconnection end devices supported by the shortcut peripheral device interconnection bridge device, and then, by defining that at least after the configuration of the last base address register space in the base address register spaces associated with the virtual device is determined, the virtual device is deleted, it means that after all the base address register spaces (for example, from BAR0 to BAR 5) are completed, that the basic input/output system is not completely configured, i.e. the basic input/output system is not completely configured, and the basic input system is ensured that the basic input/output system is completely and the basic input system is not completely configured.
In one possible implementation manner, the basic input/output system associated with the peripheral device interconnection bridge device scans a plurality of base address register spaces associated with devices mounted under each downlink port connected to an uplink port of the peripheral device interconnection bridge device in a stage of scanning a peripheral device interconnection topology, and allocates base address register resources required for each of the plurality of base address register spaces one by one in an order from a first base address register space of the plurality of base address register spaces to a last base address register space of the plurality of base address register spaces. Creating the virtual device occurs prior to the scan shortcut interconnect topology phase, so the bios will scan the created virtual device and allocate base address register resources for the virtual device. Here, since the virtual device only includes the zeroth base address register space, the other base address register spaces of the virtual device are empty, which means that the base input output system scans the zeroth base address register space included in the virtual device to determine the size of the zeroth base address register space and allocate corresponding base address register resources, so that the base address register resources allocated to the virtual device are the size corresponding to the largest base address register space in all types of shortcut peripheral interconnection devices supported by the shortcut peripheral interconnection bridge device. Here, since the zeroth base address register space is the first base address register space among the base address register spaces defined by the shortcut peripheral device interconnection standard associated with the shortcut peripheral device interconnection bridge apparatus, when the bios scans the base address register spaces, the first base address register space, that is, the zeroth base address register space, is first scanned, so that it is ensured that the bios allocates a base address register resource corresponding to the size of the zeroth base address register space to the created virtual apparatus in the stage of scanning the shortcut peripheral device interconnection topology.
In some embodiments, the virtual device is created before the bios scans the downstream port corresponding to the idle peripheral device interconnect device, the bios allocates a base address register resource according to the size of the zeroth base address register space included in the virtual device, and the virtual device is deleted after the bios scans the last base address register space of the plurality of base address register spaces associated with the virtual device. At least after determining that the configuration of the last base address register space of the plurality of base address register spaces associated with the virtual device is complete, this means that the basic input output system has scanned the plurality of base address register spaces associated with the virtual device and scanned the last base address register space and the configuration is complete. Therefore, the zeroth base address register space is the first base address register space in a plurality of base address register spaces defined by the shortcut peripheral device interconnection standard associated with the shortcut peripheral device interconnection bridge apparatus, and after the configuration of the last base address register space in the plurality of base address register spaces associated with the virtual apparatus is determined, the basic input/output system is ensured to scan all the plurality of base address register spaces, so that the requirements of various types of shortcut peripheral device interconnection end apparatuses of different manufacturers are flexibly adapted, and the system start-up flow of various basic input/output systems of different manufacturers and the operation characteristics of the scanning shortcut peripheral device interconnection topology stage are also adapted.
In one possible implementation manner, the base address register resource management method further comprises the step of not creating the virtual device when no idle shortcut peripheral device interconnection end device exists under each downlink port connected with the uplink port of the shortcut peripheral device interconnection bridge device. By traversing each downlink port connected with the uplink port of the peripheral device interconnection bridge device, whether peripheral device interconnection terminal devices are mounted under each downlink port can be determined, if no peripheral device interconnection terminal devices are mounted, it means that there is an idle peripheral device interconnection terminal device, so that all idle peripheral device interconnection terminal devices can be recorded by the idle peripheral device interconnection terminal device set associated with the peripheral device interconnection bridge device for subsequent flow of reserving base address register resources. If any He Kongxian shortcut peripheral device interconnection end device is not detected after traversing each downlink port connected with the uplink port of the shortcut peripheral device interconnection bridge device, which means that shortcut peripheral device interconnection end devices are mounted under all downlink ports, then the subsequent process of reserving the base address register resource is not required to be continuously executed. Thus, the method is beneficial to adapting to complex and changeable application environments.
In one possible implementation manner, the plurality of base address register spaces defined by the shortcut peripheral device interconnection standard are the zeroth base address register space, the first base address register space, the second base address register space, the third base address register space, the fourth base address register space, and the fifth base address register space in sequence, wherein the fifth base address register space is the last base address register space in the plurality of base address register spaces defined by the shortcut peripheral device interconnection standard. Thus, the method is beneficial to flexibly adapting to the specific definition of the interconnection standard of the peripheral devices.
In one possible implementation manner, when the configuration of the last base address register space in the plurality of base address register spaces associated with the virtual device is completed, a base address register resource determined based on the size of the zeroth base address register space included in the virtual device is reserved for the downstream port corresponding to the idle peripheral device interconnection device, so that the device hot plug is used for the device hot plug under the downstream port corresponding to the idle peripheral device interconnection device. Therefore, the hot plug of the system under no sense is realized, and the requirements of various types of shortcut peripheral device interconnection terminal equipment of different manufacturers and the operation characteristics of the system starting flow and the scanning shortcut peripheral device interconnection topology stage of various basic input and output systems of different manufacturers can be flexibly adapted.
In some embodiments, the virtual device is created before a bios scan shortcut peripheral device interconnection topology phase associated with the shortcut peripheral device interconnection bridge device, and the virtual device is deleted at least before an os phase, and during the os phase, the os does not perceive a device hot plug under a downstream port corresponding to the idle shortcut peripheral device interconnection device. Therefore, the hot plug function which is not perceived by the system is realized, the requirements of various types of shortcut peripheral device interconnection terminal equipment of different manufacturers can be flexibly adapted, and the system starting flow of various basic input and output systems of different manufacturers and the operation characteristics of the shortcut peripheral device interconnection topology stage can be flexibly adapted.
In one possible implementation manner, the base address register resource management method further comprises deleting a virtual device under a downlink port corresponding to each idle peripheral device interconnect in the idle peripheral device interconnect end device set in response to detecting that the peripheral device interconnect link is not in place. In this way, when the fact that the PCI express link is not in place is detected, for example, the host machine is turned off, the virtual equipment is deleted, and therefore system abnormality is avoided. Typically, the created virtual device should be deleted after the configuration of the last base address register space of the plurality of base address register spaces associated with the virtual device is determined to be complete. And when the fact that the interconnection link of the shortcut peripheral device is out of place is additionally detected, all virtual devices are deleted, so that system abnormality is avoided, and system stability is improved.
In one possible implementation manner, the shortcut peripheral device interconnection bridge device and the shortcut peripheral device interconnection end device mounted under the shortcut peripheral device interconnection bridge device are generated by simulation by a simulator at the embedded central processor side of the data processor. May be generated by a simulator on the Embedded Central Processing Unit (ECPU) side of a data processor (data processing unit, DPU), such as a Quick Emulators (QEMU). As such, various virtualization, paravirtualization techniques, and DPU-based systems may be adapted.
In a possible implementation manner, when any shortcut peripheral device interconnection end device is not mounted under any downlink port connected with the uplink port of the shortcut peripheral device interconnection bridge device, it is determined that an idle shortcut peripheral device interconnection end device exists under any downlink port. Therefore, by traversing each downlink port connected with the uplink port of the peripheral device interconnection bridge device, whether peripheral device interconnection terminal devices are mounted under each downlink port can be determined, if no peripheral device interconnection terminal devices are mounted, the existence of idle peripheral device interconnection terminal devices is indicated, and therefore all idle peripheral device interconnection terminal devices can be recorded through the idle peripheral device interconnection terminal device set associated with the peripheral device interconnection bridge device for subsequent flow of reserving base address register resources. If any He Kongxian shortcut peripheral device interconnection end device is not detected after traversing each downlink port connected with the uplink port of the shortcut peripheral device interconnection bridge device, which means that shortcut peripheral device interconnection end devices are mounted under all downlink ports, then the subsequent process of reserving the base address register resource is not required to be continuously executed.
Fig. 3 is a schematic diagram of a computing device 300 according to an embodiment of the present application, where the computing device 300 includes one or more processors 310, a communication interface 320, and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected by a bus 340. Optionally, the computing device 300 may further include an input/output interface 350, where the input/output interface 350 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functionality of the device embodiments or system embodiments of the present application described above, and the processor 310 can be used to implement some or all of the operational steps of the method embodiments of the present application described above. For example, specific implementations of the computing device 300 performing various operations may refer to specific details in the above-described embodiments, such as the processor 310 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in an embodiment of the present application, the computing device 300 may be configured to implement some or all of the functionality of one or more components of the apparatus embodiments described above, and the communication interface 320 may be configured to implement communication functions and the like necessary for the functionality of the apparatus, components, and the processor 310 may be configured to implement processing functions and the like necessary for the functionality of the apparatus, components.
It should be appreciated that the computing device 300 of fig. 3 may include one or more processors 310, and that the plurality of processors 310 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or the plurality of processors 310 may constitute a processor sequence or processor array, or the plurality of processors 310 may be separated into primary and secondary processors, or the plurality of processors 310 may have different architectures such as employing heterogeneous computing architectures. In addition, the computing device 300 shown in FIG. 3, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 300 may include more or fewer components than shown in fig. 3, or combine certain components, or split certain components, or have a different arrangement of components.
Processor 310 may take many specific forms, for example, processor 310 may include one or more combinations of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), and embodiments of the present application are not limited in this respect. Processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be formed by a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (FPGA) GATE ARRAY, generic array logic (GENERIC ARRAY logic, GAL), or any combination thereof. Processor 310 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or Digital Signal Processor (DSP), etc. The communication interface 320 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless lan interface, etc., for communicating with other modules or devices.
The memory 330 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM, EPROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. Memory 330 may also be volatile memory, which may be random access memory (random access memory, RAM) used as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (double DATA RATE SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM), and direct memory bus random access memory (direct rambus RAM, DR RAM). Memory 330 may also be used to store program code and data such that processor 310 invokes the program code stored in memory 330 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 300 may contain more or fewer components than shown in FIG. 3, or may have a different configuration of components.
Bus 340 may be a express peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIE) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (unified bus, ubus or UB), a computer express link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. The bus 340 may be divided into an address bus, a data bus, a control bus, and the like. The bus 340 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 3 for clarity of illustration, but does not represent only one bus or one type of bus.
The method and the device provided by the embodiment of the application are based on the same inventive concept, and because the principle of solving the problem by the method and the device is similar, the embodiment, the implementation, the example or the implementation of the method and the device can be mutually referred, and the repetition is not repeated. Embodiments of the present application also provide a system comprising a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.
Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), implement the method steps of the method embodiments described above. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the application may be implemented, in whole or in part, in software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit or scope of the embodiments of the application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs, and the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. The present application is also intended to include such modifications and alterations if they come within the scope of the claims and the equivalents thereof.

Claims (15)

1. A base address register resource management method, characterized in that the base address register resource management method comprises:
In response to detecting that a shortcut peripheral device interconnection link associated with a shortcut peripheral device interconnection bridge apparatus is in place, determining whether an idle shortcut peripheral device interconnection end apparatus exists under each downlink port connected with an uplink port of the shortcut peripheral device interconnection bridge apparatus, thereby determining an idle shortcut peripheral device interconnection end apparatus set associated with the shortcut peripheral device interconnection bridge apparatus;
For each idle shortcut peripheral device interconnection end device in the idle shortcut peripheral device interconnection end device set, creating a virtual device only comprising a zeroth base address register space and mounting the virtual device to a downlink port corresponding to the idle shortcut peripheral device interconnection end device, wherein the zeroth base address register space is a first base address register space in a plurality of base address register spaces defined by shortcut peripheral device interconnection standards associated with the shortcut peripheral device interconnection bridge device, the size of the zeroth base address register space contained in the virtual device is the size of the largest base address register space in all types of shortcut peripheral device interconnection end devices supported by the shortcut peripheral device interconnection bridge device, then, at least after the configuration of the last base address register space in the plurality of base address register spaces associated with the virtual device is determined to be completed, deleting the virtual device and configuring the shortcut peripheral device interconnection bridge device not to mount the shortcut peripheral device interconnection end device any more to the corresponding port of the idle peripheral device, and requesting a reply to the data packet as the downlink port of the peripheral device interconnection end device.
2. The method according to claim 1, wherein all types of shortcut peripheral interconnection devices supported by the shortcut peripheral interconnection bridge device include a shortcut peripheral interconnection device of a network device type, a shortcut peripheral interconnection device of a storage device type, and a shortcut peripheral interconnection device of a remote direct memory access device type.
3. The method of claim 1, wherein the size of the maximum base address register space in all types of peripheral device interconnect devices supported by the peripheral device interconnect bridge device is determined based on the maximum base address register resources required by all types of peripheral device interconnect devices supported by the peripheral device interconnect bridge device.
4. The method of claim 1, wherein determining that the configuration of the last base address register space of the plurality of base address register spaces associated with the virtual device is complete is performed when a configuration transaction layer packet corresponding to the last base address register space of the plurality of base address register spaces associated with the virtual device is received.
5. The base address register resource management method according to claim 1, wherein the basic input output system associated with the peripheral device interconnect bridge device scans a plurality of base address register spaces associated with devices mounted under each of the downstream ports to which the upstream ports of the peripheral device interconnect bridge device are connected in the stage of scanning the peripheral device interconnect topology, and allocates the base address register resources required for each of the plurality of base address register spaces one by one in order from a first base address register space of the plurality of base address register spaces to a last base address register space of the plurality of base address register spaces.
6. The method according to claim 5, wherein the virtual device is created before the bios scans the downstream port corresponding to the free peripheral device interconnect device, wherein the bios allocates the base address register resource according to the size of the zeroth base address register space included in the virtual device, and wherein the virtual device is deleted after the bios scans the last base address register space of the plurality of base address register spaces associated with the virtual device.
7. The base address register resource management method of claim 1, wherein said base address register resource management method further comprises:
And when no idle shortcut peripheral device interconnection terminal equipment exists under each downlink port connected with the uplink port of the shortcut peripheral device interconnection bridge equipment, the virtual equipment is not created.
8. The base address register resource management method of claim 1, wherein the plurality of base address register spaces defined by the shortcut peripheral device interconnect standard are, in order, the zeroth base address register space, a first base address register space, a second base address register space, a third base address register space, a fourth base address register space, and a fifth base address register space, wherein the fifth base address register space is a last base address register space of the plurality of base address register spaces defined by the shortcut peripheral device interconnect standard.
9. The method according to claim 1, wherein when the configuration of the last base address register space among the plurality of base address register spaces associated with the virtual device is completed, a base address register resource determined based on the size of the zeroth base address register space included in the virtual device is reserved for the device hot plug under the downlink port corresponding to the idle peripheral device interconnect device.
10. The method of claim 9, wherein the virtual device is created before a bios associated with the peripheral device interconnect bridge device scans a peripheral device interconnect topology stage, and wherein the virtual device is deleted at least before an os stage, and wherein during the os stage, the os does not perceive a device hot plug under a downstream port to which the free peripheral device interconnect device corresponds.
11. The base address register resource management method of claim 1, wherein said base address register resource management method further comprises:
and deleting the virtual equipment under the downlink port corresponding to each idle shortcut peripheral device interconnection end equipment in the idle shortcut peripheral device interconnection end equipment set in response to detecting that the shortcut peripheral device interconnection link is out of place.
12. The method according to claim 1, wherein the shortcut peripheral device interconnection bridge apparatus and the shortcut peripheral device interconnection end apparatus mounted under the shortcut peripheral device interconnection bridge apparatus are both generated by simulation by a simulator of an embedded central processor side of a data processor.
13. The base address register resource management method according to claim 1, wherein when any shortcut peripheral device interconnection end device is not mounted under any downlink port to which an uplink port of the shortcut peripheral device interconnection bridge device is connected, it is determined that an idle shortcut peripheral device interconnection end device exists under any downlink port.
14. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method according to any one of claims 1 to 13 when executing the computer program.
15. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 13.
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