CN119403221A - Array substrate, display device and manufacturing method - Google Patents
Array substrate, display device and manufacturing method Download PDFInfo
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Abstract
The invention discloses an array substrate, a display device and a manufacturing method. The array substrate comprises a plurality of data lines arranged in an array mode along a first direction, a plurality of grid lines arranged along the second direction and positioned in a display area, a pixel group positioned in a pixel area defined by the intersection of two adjacent data lines and two adjacent grid lines, wherein the pattern shape of orthographic projection of grid line parts of the same grid line positioned in different pixel areas on a substrate of the array substrate is the same, the length of each grid line in the second direction is the grid line width, and the first grid line width of the grid line parts positioned in the edge area of the display area is smaller than the second grid line width of the grid line parts positioned in the center area of the display area at the position, corresponding to the same pattern shape, of the grid line parts of the different pixel areas.
Description
Technical Field
The invention relates to the technical field of display. And more particularly, to an array substrate, a display device and a manufacturing method.
Background
In the design of the related display product, as shown in fig. 1, a schematic diagram of a SINGLE GATE (single gate) pixel arrangement is shown in fig. 1, and the data lines D1 to D7 and the gate lines G1 to G3 intersect to form pixel regions, in which only one pixel 30' is defined in each pixel region. Fig. 2 is a schematic diagram of a binding structure of COF (Chip On Film) corresponding to the schematic diagram of pixel arrangement in fig. 1, and as shown in fig. 2, a fan-out area is designed between the data driving module 50 and the display panel, a plurality of binding portions 51 are arranged in the fan-out area to realize signal transmission, and the binding portions 51 are arranged On the long side of the display panel and have a large number.
As the demand for the reduction of the production cost designs the Dual Gate product, the pixel arrangement of the Dual Gate product is shown in fig. 3, and as shown in fig. 4, it can be seen that the number of the binding parts 51 used for the Dual Gate is reduced to one half of the number of the binding parts 51 used for SINGLE GATE.
However, in the Dual Gate product process, a capacitive delay (RC delay) effect occurs in the driving circuit of the array substrate, thereby affecting the in-plane charging rate uniformity of the display area.
Disclosure of Invention
The invention aims to provide an array substrate, a display device and a manufacturing method, which are used for solving at least one of the problems existing in the prior art.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the first aspect of the present invention provides an array substrate, including:
A plurality of data lines arranged in an array along a first direction in the display area, each data line extending along a second direction intersecting the first direction;
a plurality of gate lines arranged along the second direction in the display area, each gate line extending along the first direction, the gate lines being arranged insulated from the data lines, and
The pixel group is positioned in a pixel area defined by the intersection of two adjacent data lines and two adjacent grid lines;
Wherein,
The pattern shape of orthographic projection of the grid line parts of the same grid line in different pixel areas on the substrate of the array substrate is the same,
The length of the grid line in the second direction is the width of the grid line,
The first gate line width of the gate line portion located at the edge region of the display region is smaller than the second gate line width of the gate line portion located at the center region of the display region at positions where the gate line portions of the different pixel regions correspond to the same pattern shape.
Further, each of the pixel groups includes a first pixel and a second pixel arranged along the first direction, each pixel corresponding to one pixel electrode,
Two adjacent pixel groups in the first direction share the same data line as a boundary of a pixel area, and two pixel electrodes of the first pixel and the second pixel are driven by the same data line;
Two gate lines are arranged between two adjacent pixel groups in the second direction, and a first pixel and a second pixel in the same pixel group are driven by the two gate lines defining the pixel area respectively.
Further, the first pixel and the second pixel in the same pixel group are different in color,
In the two adjacent pixel groups in the first direction, the color of the first pixel in one pixel group is different from the color of the first pixel in the other pixel group, and the color of the second pixel in one pixel group is different from the color of the second pixel in the other pixel group.
Further, the array substrate further includes:
a first driving electrode electrically connected to each pixel electrode,
A second driving electrode corresponding to the first driving electrode, the second driving electrode being connected to the data line, and
The plurality of grounding wires are arranged in an array mode in the first direction, and each grounding wire is located between a first pixel and a second pixel of the same pixel group and extends along the second direction.
Further, the orthographic projection of the grid line part on the substrate comprises:
a first overlap projection overlapping the orthographic projection of the data line on the substrate;
a second overlap projection overlapping the orthographic projection of the ground line on the substrate;
a third overlapping projection overlapping the orthographic projection of the first drive electrode or the second drive electrode on the substrate;
a first gap projection between the first and second overlapping projections that does not overlap the orthographic projection of the pixel electrode on the substrate, and
A second gap projection between the second overlap projection and the third overlap projection that does not overlap with an orthographic projection of the pixel electrode on the substrate;
the width difference between the first gate line width and the second gate line width is set at one or more of the first overlap projection, the second overlap projection, the first gap projection, or the second gap projection.
Further, the display region edge region includes a plurality of gate line portions of the same gate line, and a first gate line width of the plurality of gate line portions of the same gate line gradually increases in a direction from the display region edge region to the display region center region.
Further, in the first direction, the number of the gate line portions located in the edge area of the display area is 1/4 to 1/2 of the total number of the gate line portions of the display area in the same gate line.
Further, the width difference between the width of the second grid line and the width of the first grid line is 1.5-3 microns.
Further, the minimum value of the first gate line width is 7 microns or more.
Further, the distance between the boundary of the pixel electrode, which is parallel to the second direction, of the orthographic projection of the substrate and the boundary of the ground line, which is parallel to the second direction, of the orthographic projection of the substrate is a first distance,
The distance between the boundary of the pixel electrode in the orthographic projection of the substrate parallel to the second direction and the boundary of the data line in the orthographic projection of the substrate parallel to the second direction is a second distance,
The first distance is less than the second distance.
Further, the array substrate further includes:
the data driving module is used for outputting data signals;
The plurality of metal connecting wires are positioned in the fan-out area, one end of each metal connecting wire is connected with the output end of the data driving module, and the other end of each metal connecting wire is connected with the data line of the display area;
The first connection line width of the metal connection line corresponding to the data line of the edge region of the display region is greater than the second connection line width of the metal connection line corresponding to the data line of the center region of the display region.
Further, in the first direction, the number of the metal connection lines corresponding to the data lines in the edge area of the display area is 1/4-1/2 of the total number of the metal connection lines in the fan-out area.
The second aspect of the invention provides a display device, which comprises the array substrate according to the first aspect of the invention.
A third aspect of the present invention provides a method of manufacturing an array substrate according to the first aspect of the present invention, the method comprising:
forming a plurality of data lines arranged in an array along a first direction at positions corresponding to the display regions on the substrate, each data line extending along a second direction intersecting the first direction;
Forming a plurality of grid lines which are arranged in an insulating manner with the data lines and are arranged along the second direction on the substrate at positions corresponding to the display areas, wherein each grid line extends along the first direction, the pattern shapes of orthographic projections of grid line parts of the same grid line in different pixel areas on the substrate of the array substrate are the same, the lengths of the grid lines in the second direction are grid line widths, and the first grid line widths of the grid line parts in the edge areas of the display areas are smaller than the second grid line widths of the grid line parts in the central areas of the display areas at positions of the grid line parts of the different pixel areas corresponding to the same pattern shapes;
A pixel group is formed in a pixel region defined by the intersection of two adjacent data lines and two adjacent gate lines.
The beneficial effects of the invention are as follows:
According to the embodiment of the invention, the gate line width of the same gate line in the pixel areas corresponding to the different pixel areas is designed, so that the gate line width of the gate line part of the edge area of the display area is smaller than that of the center area of the display area, and through the arrangement, the impedance difference between the edge area of the display area and the center area of the display area can be improved, the delay effect is reduced, and the in-plane charging rate uniformity of a display product is improved.
Drawings
The following describes the embodiments of the present invention in further detail with reference to the drawings.
Fig. 1 shows a schematic diagram of a pixel arrangement of a related art single gate product;
FIG. 2 is a schematic diagram showing a driving structure of a related art single gate display product;
FIG. 3 shows a schematic diagram of a pixel arrangement of a dual gate product of the related art;
FIG. 4 shows a schematic diagram of a driving structure of a related art dual gate product;
FIG. 5 is a schematic diagram of a structure of a front projection of a gate line on a substrate according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of different designs of the gate line width according to one embodiment of the present invention;
FIGS. 7 and 8 are schematic diagrams showing pixel arrangements and routing designs according to various embodiments of the present invention;
FIG. 9 is a schematic diagram of the layout of traces within a pixel group according to an embodiment of the invention;
FIG. 10 shows a layout diagram of data lines and ground lines in an embodiment of the present invention;
FIG. 11 is a schematic diagram of an array substrate according to an embodiment of the present invention;
FIG. 12 is a schematic view showing the width of a gate line portion of a display region edge region according to an embodiment of the present invention;
FIG. 13 is a schematic view showing the width of a gate line portion in the center region of a display area according to an embodiment of the present invention;
Fig. 14 shows a schematic view of the distance between the ground line and the pixel electrode according to an embodiment of the present invention;
Fig. 15 shows a schematic diagram of the distance between the data line and the pixel electrode according to an embodiment of the present invention;
fig. 16 shows a schematic diagram of the width design of the metal connection lines of the fan-out area according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the present invention, the present invention will be further described with reference to examples and drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.
The delay effect of the driving circuit of the array substrate can cause the problem of uneven in-plane charging rate and uneven color development. In the process of driving the array substrate to display, each metal wiring line has a certain impedance, so that the data signal voltage tends to have a certain delay distortion in the transmission process, and the potential on the pixel electrode of the pixel unit cannot completely reach the potential of the data signal voltage output by the data driving module 50.
Therefore, due to the delay effect of the metal wiring, the charging rates of pixels in different areas in the display area are different, so that the pixels in different areas have different display brightness, different contrast and different color mixing effects, and the display effect and the electrical performance of a display product are affected.
In view of the above, the present invention provides an array substrate, a manufacturing method thereof, and a display device.
As shown in fig. 5 to 9, a first embodiment of the present invention provides an array substrate, which includes:
A plurality of data lines 10 are sequentially arranged along a first direction in the display area AA, and each data line 10 extends along a second direction intersecting the first direction, and in an exemplary embodiment, the first direction is a lateral direction shown in fig. 6, and the second direction is a longitudinal direction shown in fig. 6. In a specific example, the end portions of the data lines 10 shown in fig. 7 are connected to the binding portions 51 located in the fan-out area shown in fig. 6, and are in one-to-one correspondence with the metal connection lines 60 of the binding portions 51, so that signal transmission with the data driving module 50 is achieved.
A plurality of gate lines 20 sequentially arranged along the second direction in the display area AA, each gate line 20 extending along the first direction, the gate lines 20 being disposed insulated from the data lines 10, and
The pixel group 30 is located in a pixel region defined by the intersection of two adjacent data lines 10 and two adjacent gate lines 20.
In the embodiment of the present invention, each gate line 20 includes a plurality of gate line portions 21 located in different pixel regions, the gate line portions 21 are defined as the wiring portions of the gate lines 20 in different pixel regions, since the gate lines 20 are transversely designed in the first direction, i.e. the row direction, the data lines 10 are longitudinally designed in the second direction, i.e. the column direction, the data lines 10 and the gate lines 20 intersect to form a pixel region defining the pixel group 30, and the data lines 10 divide one gate line 20 into a plurality of gate line portions 21, i.e. the gate line portions 21 are the regions of the gate lines 20 corresponding to the boundaries of the pixel regions parallel to the first direction.
In the solution of this embodiment, as shown in fig. 5, the pattern shapes of the orthographic projections of the gate line portions 21 of the same gate line 20 in different pixel regions on the substrate of the array substrate are the same or approximately the same, and considering the wiring design of the display region AA, fig. 5 shows the special-shaped structural design of the gate line portions 21 in one pixel region, and the shapes of the gate line portions 21 of the same gate line 20 in the remaining pixel regions are the same or similar, for example, the shapes of the gate line portions 21 in the central region of the display region are the same, and the shapes of the gate line portions 21 in the edge region of the display region and the shape of the gate line portions 21 in the central region of the display region are approximate due to the gate line width design of the embodiment of the present invention.
It should be noted that the same shape of the orthographic projection pattern in this embodiment refers to the orthographic projection pattern of different pixel regions of the same gate line 20, as shown in fig. 5, where the orthographic projections of the gate lines 20 located in different rows are different, for example, as shown in fig. 5, two adjacent rows of gate lines 20 are disposed in a gap between boundaries of two pixel regions 30 (an upper non-illustrated pixel region 30a and a non-illustrated pixel region 30 b) adjacent in the second direction, for example, one row of gate lines 20a on the side close to the pixel region 30a shown in fig. 5, and a second row of gate lines 20b on the side close to the pixel region 30b, and in the first direction, the first row of gate lines 20a and the second row of gate lines 20b are decomposed into a gate line portion 21a (a dotted line region in the drawing) of the first row and a gate line portion 21b (a dotted line region in the drawing) at positions corresponding to the pixel region 30a or the pixel region 30b, and the orthographic projections of the two gate line portions at the positions are the orthographic projection portions 21a of the first row of gate line portion 21a and the second row of gate line portion 21b in the first direction is the orthographic projection point symmetry of the center of the second row of the line 21b shown in fig. 5.
Further, the two gate line portions located at two sides of the same pixel region are symmetrically designed with the axis of the pixel region along the first direction. In a specific example, two rows of gate lines, namely, a second row of gate lines 20b and a third row of gate lines 20c, are disposed on both sides of the pixel region 30b in the second direction, respectively. Similarly, in the first direction, the third row of gate lines 20c is decomposed into the third row of gate line portions 21c (dotted line areas in the drawing) at positions corresponding to the pixel regions 30a, the first row of gate line portions 21a and the third row of gate line portions 21c located on both sides of the same pixel region 30b are designed to be axisymmetric with respect to an axis of the pixel region 30b parallel to the first direction, and the first row of gate line portions 21a and the third row of gate line portions 21c are designed to be axisymmetric with respect to the axis of the pixel region 30 b.
As shown in fig. 6, 12 and 13, the length of the gate line 20 in the second direction is a gate line width, and based on the structure of the gate line 20 shown in fig. 5, the gate line 20 has different shapes in the structure along the first direction, so the gate line width in the embodiment of the present invention is the length of the gate line in the second direction, that is, the lengths of the gate line 20 in the structures at different positions in the second direction are all defined by the gate line width.
In the embodiment of the invention, the gate line width is designed, and the first gate line width d1 of the gate line portion 21 positioned in the edge area of the display area is smaller than the second gate line width d2 of the gate line portion 21 positioned in the center area of the display area at the same position of the gate line portion 21 of different pixel areas from the boundary distance L of the data line 10.
As shown in fig. 6, the width of the gate line portion 21 located at the edge area of the display area in the second direction in the embodiment of the present invention is defined as a first gate line width d1, that is, as shown in fig. 12, the gate line portion 21 located at the edge of the display area is designed in a special structure, the width mark at each place is the first gate line width, and the first gate line width d1 of the gate line portion 21 at different places can be different values. Based on the same principle, the second gate line width d2 is a width mark of the gate line part 21 located at the center area of the display area in the second direction, as shown in fig. 13, and the second gate line width d2 of the gate line part 21 at a different position may have a different value.
The embodiment of the present invention will be described in terms of the gate line portions 21 of different pixel regions at the same positions from the boundary distance L of the data line 10,
The vertical distance from the data line 10 at the position corresponding to 211 in fig. 12 and the position corresponding to 211 in fig. 13 is L1, the vertical distance from the data line 10 at the position corresponding to 212 in fig. 12 and the position corresponding to 212 in fig. 13 is L2, the vertical distance from the data line 10 at the position corresponding to 213 in fig. 12 and the position corresponding to 213 in fig. 13 is L3, the vertical distance from the data line 10 at the position corresponding to 214 in fig. 12 and the position corresponding to 214 in fig. 13 is L4, the vertical distance from the data line 10 at the position corresponding to 215 in fig. 12 and the position corresponding to 215 in fig. 13 is L5, and the first gate line width d1 is smaller than the second gate line width d2 at the same vertical distance from the different gate line portions 21 and the data line 10 on the same side. Therefore, the gate line portion 21 of the different pixel region of the present embodiment has a plurality of gate line portions, but the same positions as the boundary distances L of the data lines 10 on the same side are the same.
In the embodiment of the invention, the signal lines of the display area are designed, for example, the gate line width of the same gate line 20 in the pixel areas corresponding to the different pixel areas is designed, so that the gate line width of the gate line part 21 of the edge area AA01 of the display area is smaller than that of the center area AA02 of the display area, and by the arrangement, the impedance difference between the edge area AA01 of the display area and the center area AA02 of the display area can be improved, the delay effect is reduced, and the in-plane charging rate uniformity of the display product is improved.
In an alternative embodiment, as shown in fig. 5-9, each of the pixel groups 30 includes a first pixel 31 and a second pixel 32 arranged along the first direction, each pixel corresponding to one pixel electrode 33,
Two pixel groups 30 adjacent in the first direction share the same data line 10 as a boundary of the pixel region, and two pixel electrodes 33 of the first pixel 31 and the second pixel 32 are driven by the same data line 10;
Two gate lines 20 are disposed between two adjacent pixel groups 30 in the second direction, and first and second pixels 31 and 32 in the same pixel group 30 are driven by the two gate lines 20 defining the pixel region, respectively.
The layout design of the wiring in the embodiment of the present invention makes two pixels in each pixel group 30 share one data line 10, and two corresponding gates in each pixel group 30 of each row, by which the number of data lines 10 (the number of binding portions 51) is halved, so that the cost of the data driving module connected with the data lines 10 can be reduced.
In the embodiment of the present invention, the two pixel electrodes 33 of the first pixel 31 and the second pixel 32 are driven by the same data line 10, and the two pixel electrodes 33 of the first pixel 31 and the second pixel 32 of the different pixel groups 30 as shown in fig. 7 are driven by the same data line 10, for example, the first pixel 32 of the first pixel group 30a and the first pixel 31 of the second pixel group 30b located in the first row are driven by the same data line 10, and the second pixel 32 of the second pixel group 30b and the first pixel 31 of the third pixel group 30c are driven by the same data line 10.
In another embodiment, as shown in fig. 8, the two pixel electrodes 33 of the first pixel 31 and the second pixel 32 are driven by the same data line 10, or the first pixel 31 and the second pixel 32 in the same pixel group 30 are driven by the same data line 10, for example, as shown in fig. 8, the first pixel 31 and the second pixel 32 in each pixel group 30 of the first row are driven by the same data line 10, and a person skilled in the art will not be further described herein depending on the design of the line.
In an alternative embodiment, as shown in fig. 7 and 8, the first pixel 31 and the second pixel 32 in the same pixel group 30 are different in color,
In the two pixel groups 30 adjacent in the first direction, the color of the first pixel 31 in one pixel group 30 is different from the color of the first pixel 31 in the other pixel group 30, and the color of the second pixel 32 in one pixel group 30 is different from the color of the second pixel 32 in the other pixel group 30.
Since the pixel group 30 of the embodiment of the present invention is configured as two pixels, and the colors of the pixels for achieving light emission need to be red, green and blue, the embodiment of the present invention designs the arrangement of the pixels with different colors in the pixel group 30, that is, the colors of three pixels are different among four pixels of two adjacent pixel groups 30, wherein there is one pixel with the same color, and the distance between two pixels with the same color among the four pixels is farthest, and in one example, as shown in fig. 7, the colors of the first pixel group 30a and the second pixel group 30b located in the first row are arranged as the first pixel 31 of the first pixel group 30a with red, the second pixel 32 of the first pixel group 30a with green, the first pixel 31 of the second pixel group 30b with blue, and the second pixel 32 of the second pixel group 30b with red, thereby forming a complete light emitting unit.
Based on the arrangement of the pixel groups 30 and the routing arrangement of the display area AA according to the above embodiment of the present invention, the embodiment of the present invention further designs the width of the gate line portion 21 based on the above design.
As shown in fig. 12, a structure of one gate line part 21 is shown, and in the first direction, in the edge region of the display area, each gate line part may be arranged regularly with the structure of fig. 12, in which the first gate line width d1 is the same at the same position of each gate line part 21.
In an alternative embodiment, the display area edge area AA01 includes a plurality of gate line parts 21 of the same gate line 20, and the first gate line width d1 of the plurality of gate line parts 21 of the same gate line 20 at the same position gradually increases in a direction from the display area edge area AA01 to the display area center area AA 02.
It can be understood that the first gate line width d1 of the plurality of gate line portions 21 at the same position in the embodiment of the present invention is gradually increased, and is the arrangement of the plurality of gate line portions 21 for the same gate line 20, that is, the first direction is designed in a manner of repeating the structure, unlike the plurality of gate line portions 21 for the edge region of the display area, and the first gate line width d1 of the plurality of gate line portions 21 at the same position in the embodiment is designed to be increased toward the direction of the center region of the display area.
It should be noted that the increase in the first gate line width according to the embodiment of the present invention is the same position for different gate line portions, and in a specific example, for the dashed line area corresponding to 212 shown in fig. 12, the first gate line widths d1 of the plurality of gate line portions 21 located in the edge area AA01 of the display area at the position are sequentially set to 7.2 micrometers, 8.2 micrometers, and 9.2 micrometers in the direction from the edge to the center of the display area AA. In another specific example, for the broken line area corresponding to 214 shown in fig. 12, the first gate line width d1 of the plurality of gate line parts 21 at the position of the display area edge area AA01 is sequentially set to 19.7 micrometers, 20.7 micrometers, and 21.7 micrometers in the direction from the edge to the center of the display area AA, and a gradual increase design of the first gate line width d1 of the plurality of gate line parts at the same position is achieved to improve the charging rate uniformity in the direction from the display area edge area AA01 to the display area center area AA 02.
Based on the above-described design, although the first gate line width of the gate line portion 21 located at the same position of the display area edge area AA01 is a design scheme of gradually increasing, the maximum value of the first gate line width d1 of the gate line portion 21 located at the display area edge area AA01 is smaller than the second gate line width d2 of the gate line portion 21 located at the display area center area AA02 for the same position.
That is, still taking the dotted line area corresponding to 212 shown in fig. 12 as an example, the maximum value of the first gate line width of the gate line portion 21 located at the display area edge area AA01 is 9.2 micrometers, which is smaller than the second gate line width of the gate line portion 21 located at the display area center area AA02 shown in fig. 13 by 10.2 micrometers, to improve the charging rate uniformity in the direction from the display area edge area AA01 to the display area center area AA 02.
In an alternative embodiment, in the first direction, in the same gate line 20, the number of gate line portions 21 located in the edge area AA01 of the display area is 1/4 to 1/2 of the total number of data lines 10 connected to the metal connection lines 60 of the binding portion 50 located at the edge.
As shown in fig. 6, a plurality of binding portions 51 are sequentially arranged along a first direction in the fan-out area, each binding portion 51 includes a plurality of metal connection lines 60, one end of each metal connection line 60 is connected to an output end of the data driving module 50, and the other end is connected to the data line 10 of the display area AA, that is, the plurality of metal connection lines 60 of one binding portion 51 are respectively connected to the plurality of data lines 10 one by one, and one transversely arranged gate line 20 is decomposed into a plurality of gate line portions 21 by the plurality of vertically arranged data lines 10, so that the gate line portions 21 are designed by the number of data lines 10, and the data lines of the display products with different sizes have different structures, so that the embodiment limits the number of data lines and the number of gate line portions in the edge area AA01 of the display area by using the number of the data lines connected to the binding portion 51 located at the edge area as a design basis, so that the scheme of the embodiment has wide applicability.
In a specific example, as shown in fig. 6, the embodiment of the present invention is provided with 6 binding portions 51, and the scheme of designing the width of the gate line portion 21 in this embodiment is to design the first binding portion 51 and the region of the data line 10 to which the sixth binding portion 51 is connected. In this embodiment, the number of gate line portions 21 located in the edge area AA01 of the display area is designed, for example, the binding portion 50 located at the edge includes 960 metal wires 60, and the number of data lines corresponding to the metal wires 60 located in the edge area AA01 of the display area is 960, and in this structure, the number of gate line portions 20 for width design is 240-480, for example, preferably 1/3, that is, 320. The display area edge area AA01 of the present embodiment may be one or both of the left edge as shown in fig. 6 or the right edge as shown in fig. 6, and is designed according to practical applications.
In an alternative embodiment, the difference between the widths of the second gate line d2 and the first gate line d1 is 1.5-3 micrometers, so that the overall charging rate uniformity of the display area AA can be ensured on the basis of ensuring the process accuracy. In one specific example, if the second gate line width d2 is 10 micrometers, the first gate line width d1 may be set at 7-8.5 micrometers.
Further, the embodiment of the invention designs the minimum value of the first grid line width d1, and the minimum value of the first grid line width d1 is set to be more than or equal to 7 micrometers, so that the in-plane uniformity of the charging rate is effectively ensured on the basis of ensuring the process.
In an alternative embodiment, as shown in fig. 9 and 10, the array substrate further includes:
a first driving electrode 34 electrically connected to each pixel electrode 33,
A second driving electrode 35 corresponding to the first driving electrode 34, the second driving electrode 35 being connected to the data line 10, and
The plurality of ground lines 40 are arranged in an array in the first direction, and each ground line 40 is located between the first pixel 31 and the second pixel 32 of the same pixel group 30 and extends in the second direction.
In the embodiment of the present invention, the first driving electrode 34 may be a source electrode or a drain electrode, the second driving electrode 35 may be a drain electrode or a source electrode, and when the gate line 20 is connected to a gate driving signal and the first driving electrode 34 and the second driving electrode 35 are turned on, the data line 10 transmits a data signal output by the data driving module, and the data signal transmits the data signal to the pixel electrode 33 through the turned-on first driving electrode 34 and the turned-on second driving electrode 35, so as to realize the lighting of the first pixel 31 and the second pixel 32.
The grounding wire 40 of the embodiment of the present invention is used for accessing the VCOM signal, i.e. the ground sensing signal, and one grounding wire 40 is disposed in each pixel group 30, that is, the grounding wire 40 extends longitudinally like the data wire 10. In this embodiment, the materials of the ground line 40 and the data line 10 are the same, so as to improve the process efficiency.
Fig. 10 shows the structure of the data line 10, the first driving electrode 34, the second driving electrode 35, and the ground line 40 in front projection on the substrate according to an embodiment of the present invention. Fig. 5 is a schematic structural diagram of a gate line 20 according to an embodiment of the present invention, and a layout structure formed by orthographically overlapping gate lines 20 of fig. 5 and respective tracks of fig. 10 is shown in fig. 11.
As shown in fig. 11, in an alternative embodiment, the orthographic projection of the gate line portion 21 on the substrate includes:
a first overlap projection 211 that overlaps with the orthographic projection of the data line 10 on the substrate;
a second overlap projection 212 overlapping the orthographic projection of the ground line 40 on the substrate;
a third overlapping projection 213 overlapping the orthographic projection of the first drive electrode 34 or the second drive electrode 35 on the substrate;
A first gap projection 214 between the first overlap projection 211 and the second overlap projection 212, which does not overlap with the orthographic projection of the pixel electrode 33 on the substrate, and
A second gap projection 215 located between the second overlap projection 212 and the third overlap projection 213 that does not overlap with an orthographic projection of the pixel electrode 33 on the substrate;
the width difference between the first gate line width d1 and the second gate line width d2 is set at one or more of the first overlap projection 211, the second overlap projection 212, the first gap projection 214, or the second gap projection 215.
Based on the foregoing embodiment, the orthographic projection of the gate line portion 21 in one pixel region is a special-shaped structure, and the laterally extending gate line portion 21 forms different overlapping projections with other wires, while the gate line width in the embodiment of the present invention has different designs at different positions of the gate line portion 21.
For example, fig. 12 shows the structural design of the overlapping projection of the display area edge area AA01, and fig. 13 shows the structural design of the overlapping projection of the display area center area AA02, with different gate line width designs at the same position of the gate line portion 21 of the two areas.
It should be noted that the screenshot positions of fig. 12 and 13 are located in the pixel regions on both sides of the data line 10 of fig. 11.
In a specific example, at the second overlap projection 212 formed by the gate line portion 21 and the ground line 40, the width of the gate line portion 21 at this position may be designed differently, for example, the width of the gate line portion 21 at this position at the display region edge region AA01 is set to 7.2 micrometers, and at the same second overlap projection 212 position of the gate line portion 21 at the display region center region AA02 shown in fig. 13, the width of the gate line portion 21 at this position is set to 10.2 micrometers.
In another example, at the first overlapping projection 211 overlapping the orthographic projection of the data line 10 on the substrate, the width of the gate line portion 21 at the position may be designed differently, for example, the width of the gate line portion 21 at the display area edge area AA01 at the position is set to 7.2 micrometers, and at the same first overlapping projection 211 of the gate line portion 21 at the display area center area AA02 shown in fig. 13, the width of the gate line portion 21 at the position is set to 10.2 micrometers.
At a position of the first gap projection 214 between the first overlap projection 211 and the second overlap projection 212, which does not overlap with the front projection of the pixel electrode 33 on the substrate, the width of the gate line portion 21 at this position may be designed differently, for example, the width of the gate line portion 21 at this position at the display region edge region AA01 is set to 19.7 micrometers, and at the same projection position of the gate line portion 21 at the display region center region AA02 shown in fig. 13, the width of the gate line portion 21 at this position is set to 22.7 micrometers.
At a position of a second gap projection 215 between the second overlap projection 212 and the third overlap projection 213, which does not overlap with the orthographic projection of the pixel electrode 33 on the substrate, the width of the gate line portion 21 at this position may be designed differently, for example, the width of the gate line portion 21 at this position at the display region edge region AA01 is set to 8.2 micrometers, and at the same position of the first overlap projection 211 of the gate line portion 21 at the display region center region AA02 shown in fig. 13, the width of the gate line portion 21 at this position is set to 11.2 micrometers.
Based on the above embodiment of the present invention, a differentiated gate line width may be set at one or more of the first overlapping projection 211, the second overlapping projection 212, the first gap projection 214, or the second gap projection 215, that is, the gate line width of the embodiment of the present invention is not set at the position of the third overlapping projection 213, so as to protect the design requirements of the gate line portion 21 and the first driving electrode 34 or the second driving electrode 35 at the position, and ensure the circuit performance.
The design of the embodiment of the invention can effectively improve the overall uniformity of the pixel charging rate of the array substrate, thereby improving the display performance of the array substrate.
Furthermore, under the condition of the bright state and the dark state of the backlight, the existence of illumination has the same influence on the conductor characteristics of the active layer of the Dual Gate product, so that the delay effect exists on the voltage accessed by each metal wire, and the stripe with different brightness, called waterfall bad, can be generated on the display product, and the picture display effect is also influenced. In addition, signal lines in the display product are mutually influenced due to capacitive coupling, so that signal transmission is abnormal, and the risk of poor V-cross talk is easy to occur.
Thus, in an alternative embodiment, as shown in fig. 14 and 15, the distance between the boundary of the pixel electrode 33 parallel to the second direction of the front projection of the substrate and the boundary of the ground line 40 parallel to the second direction of the front projection of the substrate is a first distance d3, and the distance between the boundary of the pixel electrode 33 parallel to the second direction of the front projection of the substrate and the boundary of the data line 10 parallel to the second direction of the front projection of the substrate is a second distance d4, and the first distance d3 is smaller than the second distance d4.
The embodiment of the invention designs the first distance d3 between the pixel electrode 33 and the ground line 40 and the second distance d4 between the pixel electrode 33 and the data line 10 to be different, and makes the first distance d3 smaller than the second distance d4, thereby improving the problems of WATERFALL and V-cross talk.
In a specific example, the first distance d3 is 3.5 micrometers, the second distance d4 is 6 micrometers, and compared with the design scheme that the first distance d3 and the second distance d4 are the same and are both 5 micrometers in the related art, the first distance d3 is reduced, the routing area is reduced to improve the influence of illumination, thereby improving the defect of WATERFALL, and the second distance d4 is increased, thereby reducing the pixel capacitance of the data line 10 on the left and right sides of the pixel electrode 33 and the pixel electrode 33, so as to improve the defect of V-cross talk.
In an alternative embodiment, as shown in fig. 16, the array substrate further includes:
a data driving module 50 for outputting a data signal;
a plurality of binding parts 51 sequentially arranged in the first direction and located in the fan-out area, wherein the binding parts 51 comprise a plurality of metal connecting wires 60, one end of each metal connecting wire 60 is connected with the output end of the data driving module 50, and the other end is connected with the data line 10 of the display area AA;
the first connection line width of the metal connection line 60 corresponding to the data line 10 of the display area edge area AA01 is greater than the second connection line width of the metal connection line 60 corresponding to the data line 10 of the display area center area AA 02.
The embodiment of the invention designs the widths of the metal connection lines 60 obtained at different positions, so that the width of the first connection line of the metal connection lines 60 is larger than the width of the second connection line in the direction from the edge area AA01 of the display area to the center area AA02 of the display area, namely, the width of the edge area is large, the width of the center area is small, in a specific example, the width of the first connection line is 8.9 micrometers, and the width of the second connection line is 6.9 micrometers, and the arrangement can effectively reduce the impedance difference between the data lines 10 on both sides and the middle data line 10 on the whole display area AA, thereby improving the display uniformity.
In an alternative embodiment, in the first direction, the number of the metal connection lines 60 corresponding to the data lines 10 of the display area edge area AA01 is 1/4 to 1/2 of the total number of the metal connection lines 60 of the binding portion 51 located at the very edge. The binding portion 50 at the very edge portion includes 960 metal wires 60, and in this structure, the number of the metal wires 60 to be designed is 240 to 480, for example, preferably 1/3 or 320.
That is, on the basis that the gate line parts 21 according to the foregoing embodiment of the present invention are also designed in width, the number of the metal connection lines 60 is set to be identical to the number of the gate line parts 21 designed in width, further ensuring the uniformity of the charging rate in the whole plane of the display area AA.
Based on the array substrate of the foregoing embodiment, an embodiment of the present invention proposes a method for manufacturing the array substrate of the foregoing embodiment, where the method includes:
Forming a plurality of data lines 10 arranged in an array along a first direction at positions corresponding to the display areas AA on the substrate, each data line 10 extending along a second direction intersecting the first direction;
Forming a plurality of grid lines 20 which are arranged in an insulating manner with the data lines 10 and are arranged along the second direction at positions corresponding to the display areas AA on the substrate, wherein each grid line 20 extends along the first direction, the pattern shapes of orthographic projections of the grid line parts 21 of the same grid line 20 positioned in different pixel areas on the substrate of the array substrate are the same, the lengths of the grid lines 20 in the second direction are grid line widths, and the first grid line width d1 of the grid line parts 21 positioned in the edge area AA01 of the display areas is smaller than the second grid line width d2 of the grid line parts 21 positioned in the central area AA02 of the display areas at positions of the grid line parts 21 of different pixel areas corresponding to the same pattern shapes;
The pixel group 30 is formed in a pixel region defined by intersections of the adjacent two data lines 10 and the adjacent two gate lines 20.
According to the manufacturing method, a complex process flow is not increased, and different gate line widths are formed in the array substrate formed by the manufacturing method of the embodiment of the invention in the corresponding different pixel areas, so that the gate line width of the gate line part 21 of the edge area AA01 of the display area is smaller than that of the central area AA02 of the display area, and by the arrangement, the impedance difference between the edge area AA01 of the display area and the central area AA02 of the display area can be improved, the delay effect is reduced, and the in-plane charging rate uniformity of a display product is improved.
Another embodiment of the present invention provides a display device, which is characterized in that the display device includes the array substrate of the first embodiment of the present invention. The display device may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator, which is not limited in this embodiment.
In the description of the present invention, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
It should be understood that the foregoing examples of the present invention are provided merely for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention, and that various other changes and modifications may be made therein by one skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (14)
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310936516.6A CN119403221A (en) | 2023-07-26 | 2023-07-26 | Array substrate, display device and manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310936516.6A CN119403221A (en) | 2023-07-26 | 2023-07-26 | Array substrate, display device and manufacturing method |
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| CN119403221A true CN119403221A (en) | 2025-02-07 |
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| CN202310936516.6A Pending CN119403221A (en) | 2023-07-26 | 2023-07-26 | Array substrate, display device and manufacturing method |
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