CN119401827B - Voltage conversion circuit - Google Patents
Voltage conversion circuit Download PDFInfo
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- CN119401827B CN119401827B CN202411960610.6A CN202411960610A CN119401827B CN 119401827 B CN119401827 B CN 119401827B CN 202411960610 A CN202411960610 A CN 202411960610A CN 119401827 B CN119401827 B CN 119401827B
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 claims description 7
- 230000000630 rising effect Effects 0.000 claims description 4
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 6
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000009194 climbing Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Abstract
本发明提供一种电压转换电路，包括：第一倒相器的输入端作为电压转换电路的输入端，第一倒相器的输出端连接第二NMOS管的栅端，第二NMOS管的漏端连接第一NMOS管的源端，第一NMOS管的栅端连接第五NMOS管的源端、第六NMOS管的漏端，第一NMOS管的漏端连接第一PMOS管的漏端、第三PMOS管的栅端，第三PMOS管的漏端连接第三倒相器的输入端、第三NMOS管的漏端，第三NMOS管的源端连接第四NMOS管的漏端，第四NMOS管的栅端连接第二倒相器的输出端，第三倒相器的输出端为电压转换电路的输出端。本发明电压转换电路转换速度较快。
The present invention provides a voltage conversion circuit, comprising: the input end of a first inverter is used as the input end of the voltage conversion circuit, the output end of the first inverter is connected to the gate end of a second NMOS tube, the drain end of the second NMOS tube is connected to the source end of the first NMOS tube, the gate end of the first NMOS tube is connected to the source end of a fifth NMOS tube and the drain end of a sixth NMOS tube, the drain end of the first NMOS tube is connected to the drain end of a first PMOS tube and the gate end of a third PMOS tube, the drain end of the third PMOS tube is connected to the input end of a third inverter and the drain end of a third NMOS tube, the source end of the third NMOS tube is connected to the drain end of a fourth NMOS tube, the gate end of the fourth NMOS tube is connected to the output end of the second inverter, and the output end of the third inverter is the output end of the voltage conversion circuit. The voltage conversion circuit of the present invention has a fast conversion speed.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a voltage conversion circuit.
Background
In integrated circuit designs, supply voltage diversity is increasingly abundant as circuit scale expands. Communication between signals of different voltages is indispensable, and accordingly, various structures of voltage conversion circuits have been developed. Generally, the voltage conversion circuit needs to transmit (convert) signals as soon as possible, but the most commonly used voltage conversion circuit has a positive feedback latch structure, so that the response speed is difficult to be increased only when the existing latch state is overcome in the voltage signal conversion process, and the bottleneck is encountered in the increase of the conversion speed, especially in the signal conversion between the low voltage domain (0.8V or 1.1V) and the higher voltage domain (more than 5V and 3.3V or 2.5V higher than the common high voltage domain), so that the existing voltage conversion circuit is still more important to catch the forepart, and a new voltage conversion circuit is needed.
Disclosure of Invention
The invention aims to provide a voltage conversion circuit with high conversion speed.
In order to achieve the above purpose, the present invention provides the following technical scheme:
The invention provides a voltage conversion circuit which comprises a first phase inverter, a second phase inverter, a third phase inverter, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube; the input end of the first inverter is used as the input end of the voltage conversion circuit to receive an input signal, the first inverter and the second inverter are sequentially connected in series, the output end of the first inverter is connected with the gate end of the second NMOS tube, the source end of the second NMOS tube is connected with the ground, the drain end of the second NMOS tube is connected with the source end of the first NMOS tube, the gate end of the first NMOS tube is connected with the source end of the fifth NMOS tube and the drain end of the sixth NMOS tube, the source end of the sixth NMOS tube is connected with the ground, the gate end of the sixth NMOS tube is connected with the input end of the third inverter, the drain end of the fifth NMOS tube is connected with the second working voltage, the gate end of the fifth NMOS tube is connected with the output end of the third inverter, the drain end of the first PMOS tube is connected with the drain end of the third PMOS tube, the drain end of the third NMOS tube is connected with the gate end of the third PMOS tube, the gate end of the first PMOS tube is connected with the drain end of the third NMOS tube, the third NMOS tube is connected with the drain end of the third NMOS tube is connected with the third NMOS tube, the drain terminal of the fifth PMOS tube is connected with the input terminal of the third phase inverter, the gate terminal of the fifth PMOS tube is connected with the output terminal of the third phase inverter, the source terminal of the fifth PMOS tube is connected with the third working voltage, the drain terminal of the fourth PMOS tube is connected with the input terminal of the third phase inverter, the gate terminal of the fourth PMOS tube receives a setting signal, the source terminal of the fourth PMOS tube is connected with the third working voltage, the output terminal of the third phase inverter is the output terminal of the voltage conversion circuit, the first phase inverter and the second phase inverter are devices working at the first working voltage, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are devices working at the second working voltage, and the fifth NMOS tube, the sixth NMOS tube, the first PMOS tube, the third NMOS tube, the fourth PMOS tube, the fifth NMOS tube, the third PMOS tube and the third NMOS tube are devices working at the third working voltage and the third working voltage is smaller than the first working voltage and the second working voltage is smaller than the third working voltage.
In an embodiment, the voltage conversion circuit further includes a second PMOS transistor, a source end of the second PMOS transistor is connected to the third operating voltage, a gate end of the second PMOS transistor is connected to a drain end of the second PMOS transistor, and a drain end of the second PMOS transistor is connected to a gate end of the third PMOS transistor.
In an embodiment, the voltage conversion circuit further includes a tri-state gate, an input end of the tri-state gate is connected to the output end of the third inverter, an output end of the tri-state gate is connected to the input end of the third inverter, and an operation state of the tri-state gate is controlled by a latch signal.
In one embodiment, an even number of inverters are further disposed between the output terminal of the second inverter and the gate terminal of the fourth NMOS transistor.
In an embodiment, the fifth NMOS transistor is replaced with a sixth PMOS transistor, a source terminal of the sixth PMOS transistor is connected to the second operating voltage, a drain terminal of the sixth PMOS transistor is connected to the gate terminal of the first NMOS transistor, and the gate terminal of the sixth PMOS transistor is connected to the input terminal of the third inverter.
In one embodiment, the set signal has a process of rising from a low voltage to a high voltage.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the voltage conversion circuit adopts a unidirectional open-loop structure, shortens the conversion delay of signals, and has higher conversion speed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a voltage conversion circuit according to a first embodiment of the present invention;
fig. 2 is a block diagram of a voltage conversion circuit according to a second embodiment of the present invention.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention. It should be noted that the following description order of the embodiments is not intended to limit the preferred order of the embodiments of the present invention. In the following embodiments, the descriptions of the embodiments are focused on, and for the part that is not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
Referring to fig. 1, a first embodiment of the present invention provides a voltage conversion circuit, which includes a first inverter inv1, a second inverter inv2, a third inverter inv3, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first PMOS transistor PM1, a third PMOS transistor PM3, a fourth PMOS transistor PM4, and a fifth PMOS transistor PM5, wherein an input terminal of the first inverter inv1 is used as an input terminal of the voltage conversion circuit to receive an input signal in, and the first inverter inv1, The output end of the first inverter inv1 is connected with the gate end of the second NMOS tube NM2 in series, the source end of the second NMOS tube NM2 is connected with the ground, the drain end of the second NMOS tube NM2 is connected with the source end of the first NMOS tube NM1, the gate end NM1 of the first NMOS tube is connected with the source end of the fifth NMOS tube NM5 and the drain end of the sixth NMOS tube NM6, the source end of the sixth NMOS tube NM6 is connected with the ground, the gate end of the sixth NMOS tube NM6 is connected with the input end of the third inverter inv3, the drain end of the fifth NMOS tube NM5 is connected with the second working voltage MVDD, the gate end of the fifth NMOS tube NM5 is connected with the output end of the third inverter inv3, the drain end of the first NMOS tube NM1 is connected with the drain end of the first PMOS tube PM1, The gate end of the third PMOS tube PM3, the gate end of the first PMOS tube PM1 is connected with the output end of the third inverter inv3, the source end of the first PMOS tube PM1 is connected with the third working voltage HVDD, the source end of the third PMOS tube PM3 is connected with the third working voltage HVDD, the drain end of the third PMOS tube PM3 is connected with the input end of the third inverter inv3, The drain terminal of the third NMOS NM3, the gate terminal of the third NMOS NM3 is connected to the second operating voltage MVDD, the source terminal of the third NMOS NM3 is connected to the drain terminal of the fourth NMOS NM4, the gate terminal of the fourth NMOS NM4 is connected to the output terminal of the second inverter inv2, the source terminal of the fourth NMOS NM4 is connected to ground, the drain terminal of the fifth PMOS PM5 is connected to the input terminal of the third inverter inv3, the gate terminal of the fifth PMOS PM5 is connected to the output terminal of the third inverter inv3, the source terminal of the fifth PMOS PM5 is connected to the third operating voltage HVDD, the drain terminal of the fourth PMOS PM4 is connected to the input terminal of the third inverter inv3, the gate terminal of the fourth PMOS PM4 receives the set signal rtb, the source terminal of the fourth PMOS PM4 is connected to the third operating voltage HVDD, the gate terminal of the third PMOS PM 3 is the output terminal of the inverter hvv 1, The second inverter inv2 is a device operating at a first operating voltage, the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 are devices operating at a second operating voltage MVDD, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the first PMOS transistor PM1, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, and the third inverter inv3 are devices operating at a third operating voltage HVDD, a third inverter is a device operating at a third operating voltage MVDD, a fourth inverter is a device operating at a third operating voltage MVDD, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first PMOS transistor PM1, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth NMOS transistor PM5, and a third inverter inv3 are devices operating at a third operating voltage HVDD, The first operating voltage is smaller than the second operating voltage MVDD, and the second operating voltage MVDD is smaller than the third operating voltage HVDD.
The first operating voltage may be 1.1V or less, for example, 0.8V (hereinafter, may be abbreviated as low voltage), the second operating voltage MVDD may be 3.3V or 2.5V (hereinafter, may be abbreviated as medium voltage), and the third operating voltage HVDD may be 5.0V or more (hereinafter, may be abbreviated as high voltage). Correspondingly, the input signal in is a low-voltage domain signal, and the output signal output by the output end out of the voltage conversion circuit is a high-voltage domain signal, so that the conversion of the signal from the low-voltage domain to the high-voltage domain is realized through the voltage conversion circuit.
The operation principle of the voltage conversion circuit of the present invention will be described with reference to fig. 1. In order to simplify the text and facilitate understanding, in fig. 1, some key nodes are defined, namely, a node la, which is denoted as the output end of the first inverter inv1, the input end of the second inverter inv2, and the gate end of the second NMOS transistor NM2, a node lb, which is denoted as the output end of the second inverter inv2, the gate end of the fourth NMOS transistor NM4, a node hb, which is denoted as the gate end of the first NMOS transistor NM1, the source end of the fifth NMOS transistor NM5, and the drain end of the sixth NMOS transistor NM6, a node hd, which is denoted as the drain end of the first NMOS transistor NM1, the drain end of the first PMOS transistor PM1, and the gate end of the third PMOS transistor PM3, and a node outb, which is denoted as the input end of the third inverter inv3, the drain end of the third NMOS transistor PM3, the drain end of the fifth PMOS transistor PM5, the drain end of the fourth PMOS transistor PM4, and the gate end of the sixth NMOS transistor NM6, and the output end of the third PMOS transistor NM3, and the gate ends of the fifth PMOS transistor PM5 are simultaneously. The symbols of these nodes will be directly used and each element will be described later.
First, in operation, the voltage conversion circuit of the present invention is set by the set signal rtb. In one embodiment, the set signal rtb may have a process of raising from low voltage to high voltage, so that the PM4 is turned on again, the outb is pulled high due to PM4 being turned on, the out phase inverts the outb to low due to inv3, PM5 and PM1 are both turned on, hd is high, NM5 is turned off, NM6 is turned on, hb is low, NM1 is turned off, and initial set is completed.
After initial setting, when in rises from low to high, la falls and NM2 is turned off. lb rises, NM4 is on, and NM3 is in a normally on state, whereupon the charge of outb starts to drain (HVDD and PM5 are also in the drain path). Since the on-resistances of NM3, NM4 are much smaller than the on-resistance of PM5, the potential of outb is pulled down and the potential of out rises (corresponding to in rising, completing the transition). PM5 is off, NM5 is on, and NM1 is on, PM1 is off at this time, and is in high resistance state, and hd is still maintained at high potential because NM2 is off. The high level of out is maintained by the on-state of NM3, NM 4.
When in decreases from high to low, la increases, NM2 is opened, and then hd-NM 1-NM 2 starts to have current, hd decreases in potential, PM3 is turned on gradually, and the charging of the outb starts. At the same time lb also falls, NM4 turns off, whereupon the potential of the outb starts to rise, NM6 also turns on, and the charge on hb starts to drain. When the outb rise is inverted by inv3, out is down (corresponding to in down, complete conversion). PM5 is on and the output is pulled to a relatively high potential. hb is also pulled low because NM5 is off and NM6 is on, resulting in NM1 being off. Finally PM1 is turned on and hd is pulled high again. The low level of out is maintained by feedback from PM 5.
The voltage conversion circuit adopts a unidirectional open-loop structure, shortens the conversion delay of signals, and has higher conversion speed. In addition, the cascade structure from low voltage to medium voltage to high voltage protects low-voltage devices working at high voltage, and the service life of the circuit is prolonged. And the circuit is only sensitive to edge jump, so that direct current power consumption is eliminated. The potential of hd is maintained at a high level except at the moment of edge transition, and PM3 is always off.
The applicant has further studied that if in goes from a low potential to a high potential state for a longer period of time, the hd potential drops to a point where there is a greater leakage (greater than that of PM 1) in a high temperature environment or NM2, resulting in incomplete shutdown of PM 3. At this time, if there is a falling edge of in, the voltage of hd is not reduced from HVDD, but some intermediate voltage, so PM3 is seen to be turned on quickly, and the rising speed of outb is seen to be quick. However, if in is kept at high potential for a short time, even if the leakage of NM2 is large, because hd is not discharged by NM1, NM2, the potential of hd is very close to the HVDD voltage value. If a falling edge occurs at this point in, hd is pulled down from HVDD until PM3 is on. This time is significantly longer. This characteristic results in a signal stream that does not have good delay uniformity when high frequency and low frequency mixed signals are transmitted. Therefore, in an embodiment, the voltage conversion circuit further includes a second PMOS tube PM2 (at a dashed box a in the drawing), the source end of the second PMOS tube PM2 is connected to the third operating voltage HVDD, the gate end of the second PMOS tube PM2 is connected to the drain end of the second PMOS tube PM2, and the drain end of the second PMOS tube PM2 is connected to the gate end of the third PMOS tube PM 3. Thus, when NM1 is on, NM2 is off, PM1 is off, and hd is supplied with power by PM2 (hd is down, PM2 is on, and hd is further supplied with power), so that hd is still maintained at a higher potential. Of course, the second PMOS transistor is also a device operating at the third operating voltage.
Further, referring to fig. 1 again, in an embodiment, the voltage conversion circuit further includes a tri-state gate tri_inv (at a dashed line box B in the figure), an input end of the tri-state gate tri_inv is connected to an output end of the third inverter inv3, an output end of the tri-state gate tri_inv is connected to an input end of the third inverter inv3, and an operation state of the tri-state gate tri_inv is controlled by a latch signal latch. Because in the larger system circuit applying the voltage conversion circuit of the present invention, the first operating voltage and the second operating voltage MVDD are sometimes powered down according to the need (the third operating voltage HVDD is generally not powered down) in the operating process, if the tri-state gate tri_inv is not provided, when the first operating voltage and the second operating voltage MVDD are powered down, the out potential is also randomly changed, and the state before power failure cannot be maintained, thereby causing trouble to the normal operation of the system. According to the invention, a loop is formed by the tri-state gate tri-inv and the third phase inverter inv3, the tri-state gate tri-inv is enabled to work through a latch signal latch before the system is powered down, the out potential is kept in a state before the power down through the loop formed by the tri-state gate tri-inv 3, and the tri-state gate tri-inv is enabled to be in a non-working state through the latch signal latch in a general working process. For example, when the latch signal latch is low, the tri-state gate tri_inv is not operated, and when the latch signal latch is high, the tri-state gate tri_inv is put into an operating state.
Next, referring to fig. 2, the second embodiment of the present invention further provides a voltage converting circuit, and comparing with the first embodiment of fig. 1, the difference between the two is that an even number of inverters (at the dashed line box C in the figure) are further disposed between the output terminal inv2 of the second inverter and the gate terminal of the fourth NMOS transistor NM 4. In this way, more discharge time can be given to hd. Because the delay of the inverter is small in some processes, the PM3 has a small enough on-resistance, so that the slew rate (slew rate) of the outb is slow, that is, the climbing speed is slow, and although the potential change of the out is enough to enable the NM1 to be turned off, the slew rate of the out is slow in the second half, which is unfavorable for shortening the signal conversion time.
Referring to fig. 1 and 2, in an embodiment, the fifth NMOS transistor NM5 may be replaced by a sixth PMOS transistor PM6 (at a dashed box D in the drawing), the source end of the sixth PMOS transistor PM6 is connected to the second operating voltage MVDD, the drain end of the sixth PMOS transistor PM6 is connected to the gate end of the first NMOS transistor NM1, and the gate end of the sixth PMOS transistor PM6 is connected to the input end of the third inverter inv 3. Thus, the wiring of the whole circuit can be reduced, and the circuit structure can be simplified.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
The voltage conversion circuit adopts a unidirectional open-loop structure, shortens the conversion delay of signals, and has higher conversion speed. In addition, the cascade structure from low voltage to medium voltage to high voltage protects low-voltage devices working at high voltage, and the service life of the circuit is prolonged. And the circuit is only sensitive to edge jump, so that direct current power consumption is eliminated. And the latch structure can help to maintain the output result unchanged under the condition that the power of the low-voltage power supply is cut off.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. Furthermore, the foregoing description of the principles and embodiments of the invention has been provided for the purpose of illustrating the principles and embodiments of the invention and for the purpose of providing a further understanding of the principles and embodiments of the invention, and is not to be construed as limiting the invention.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411960610.6A CN119401827B (en) | 2024-12-30 | 2024-12-30 | Voltage conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411960610.6A CN119401827B (en) | 2024-12-30 | 2024-12-30 | Voltage conversion circuit |
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| Publication Number | Publication Date |
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| CN119401827A CN119401827A (en) | 2025-02-07 |
| CN119401827B true CN119401827B (en) | 2025-04-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202411960610.6A Active CN119401827B (en) | 2024-12-30 | 2024-12-30 | Voltage conversion circuit |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104638887A (en) * | 2015-01-30 | 2015-05-20 | 北京时代民芯科技有限公司 | Output driving circuit capable of realizing output high level conversion |
| CN108233917A (en) * | 2016-12-15 | 2018-06-29 | 江苏安其威微电子科技有限公司 | Level shifting circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7397279B2 (en) * | 2006-01-27 | 2008-07-08 | Agere Systems Inc. | Voltage level translator circuit with wide supply voltage range |
| CN117498849A (en) * | 2022-07-25 | 2024-02-02 | 苏州旗芯微半导体有限公司 | Signal conversion circuit |
| CN116545430A (en) * | 2023-04-20 | 2023-08-04 | 上海数明半导体有限公司 | Level conversion circuit, DC/DC converter, and gate driver |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104638887A (en) * | 2015-01-30 | 2015-05-20 | 北京时代民芯科技有限公司 | Output driving circuit capable of realizing output high level conversion |
| CN108233917A (en) * | 2016-12-15 | 2018-06-29 | 江苏安其威微电子科技有限公司 | Level shifting circuit |
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| CN119401827A (en) | 2025-02-07 |
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