CN119400686A - Semiconductor device manufacturing method and semiconductor device - Google Patents
Semiconductor device manufacturing method and semiconductor device Download PDFInfo
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- CN119400686A CN119400686A CN202510000479.7A CN202510000479A CN119400686A CN 119400686 A CN119400686 A CN 119400686A CN 202510000479 A CN202510000479 A CN 202510000479A CN 119400686 A CN119400686 A CN 119400686A
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Abstract
The application provides a semiconductor device manufacturing method and a semiconductor device, and relates to the technical field of semiconductor device manufacturing. The preparation method of the semiconductor device comprises the steps of forming a first epitaxial layer on a substrate, forming a first alignment mark on the first epitaxial layer through a mark mask plate, aligning the device mask plate with an exposure unit through the first alignment mark, forming a preset structure on the first epitaxial layer in the exposure unit through the device mask plate, forming a second epitaxial layer on the first epitaxial layer, forming a second alignment mark on the second epitaxial layer through the mark mask plate, spacing the second alignment mark from the first alignment mark by an integer multiple of the device unit distance, and driving the device mask plate to move the device unit by the integer multiple of the device unit distance after aligning the alignment mark pattern on the device mask plate with the second alignment mark, and forming the preset structure on the second epitaxial layer in the exposure unit through the device mask plate. According to the application, only one mark mask plate is needed, so that the number of the mark mask plates is effectively reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor device preparation, in particular to a semiconductor device preparation method and a semiconductor device.
Background
With the advancement of technology, the demand for semiconductor devices is increasing, wherein a part of semiconductor device manufacturing processes need to be prepared layer by layer in multiple layers, and finally finished semiconductor devices are manufactured. In the process of multilayer layer-by-layer fabrication, semiconductor structures formed in different wafer layers need to be aligned by alignment marks.
In order to avoid that the front layer alignment marks at the same position interfere the reflected light of the alignment marks of the current layer under the alignment illumination, the alignment precision among different wafer layers is affected. Therefore, in the current process, alignment marks are required to be formed at different positions of each wafer layer, and a corresponding alignment mask is required to be designed for each wafer layer, which greatly increases the manufacturing cost of manufacturing the multi-layer semiconductor device.
In view of this, there is a need for a method of fabricating a semiconductor device that reduces the cost of producing the semiconductor device by a multi-layer, layer-by-layer fabrication process.
Disclosure of Invention
In view of the above drawbacks of the prior art, the present invention provides a method for manufacturing a semiconductor device, so as to improve the technical problem that in the existing multilayer layer-by-layer manufacturing process of the semiconductor device, a corresponding alignment mask plate needs to be designed for each wafer layer, resulting in higher manufacturing cost.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor device, comprising at least the steps of:
Forming a first epitaxial layer on a substrate;
providing a mark mask plate, and forming a first alignment mark on the first epitaxial layer through the mark mask plate, wherein the first alignment mark is positioned in a preset exposure unit;
Providing a device mask plate, aligning the device mask plate with the exposure unit by using the first alignment mark, and forming a preset structure on the first epitaxial layer in the exposure unit through the device mask plate;
Forming a second epitaxial layer on the first epitaxial layer;
Forming a second alignment mark on the second epitaxial layer by using the mark mask plate, wherein the second alignment mark is positioned in the exposure unit, and the second alignment mark and the first alignment mark are separated by an integral multiple of the distance of the device unit;
After aligning the alignment mark pattern on the device mask plate with the second alignment mark, driving the device mask plate to move the device unit by an integral multiple distance so as to align the device mask plate with the exposure unit, and forming a preset structure on the second epitaxial layer in the exposure unit through the device mask plate.
In one embodiment of the present invention, the exposure unit includes a chip region and a dicing street provided at a periphery of the chip region.
In one embodiment of the invention, the first alignment mark and the second alignment mark are located in two parallel scribe lines in the exposure unit.
In one embodiment of the invention, the method further comprises the steps of forming a third epitaxial layer on the second epitaxial layer, forming a preset structure on the third epitaxial layer until a preset number of epitaxial layers are formed on the substrate, and forming the preset structure in the preset number of epitaxial layers.
In one embodiment of the present invention, adjacent alignment marks do not overlap each other in the depth direction, and the projection of the adjacent alignment marks on the substrate has the same pitch in the horizontal direction.
In one embodiment of the invention, aligning the device mask plate with the exposure unit by using the first alignment mark, and forming a preset structure on the first epitaxial layer in the exposure unit by using the device mask plate comprises the steps of forming a photoresist layer on the first epitaxial layer; the method comprises the steps of aligning an alignment mark pattern on a device mask plate with a first alignment mark to align the device mask plate with an exposure unit, exposing the photoresist layer to form an injection window by using an injection region pattern on the device mask plate, and injecting impurity ions into the first epitaxial layer exposed by the injection window by taking the photoresist layer outside the injection window as a mask to form a preset structure in the first epitaxial layer.
In one embodiment of the invention, a second alignment mark is formed on the second epitaxial layer by using the mark mask plate, the second alignment mark is positioned in the exposure unit, the distance between the second alignment mark and the first alignment mark is an integral multiple of the device unit distance, the second alignment mark comprises the steps of coating and forming a photoresist layer on the second epitaxial layer, driving the mark mask plate to move the device unit an integral multiple of the distance after aligning the alignment mark pattern on the mark mask plate with the first alignment mark, and forming the second alignment mark on the second epitaxial layer by using the moved mark mask plate.
In one embodiment of the invention, after aligning the alignment mark pattern on the device mask plate with the second alignment mark, driving the device mask plate to move an integral multiple distance of the device unit so as to align the device mask plate with the exposure unit, and forming a preset structure on the second epitaxial layer in the exposure unit through the device mask plate comprises the steps of forming a photoresist layer on the second epitaxial layer, aligning the alignment mark pattern on the device mask plate with the second alignment mark, driving the device mask plate to move the device unit an integral multiple distance so as to align the device mask plate with the exposure unit, forming an injection window on the photoresist layer by using an injection region pattern on the device mask plate, and injecting impurity ions into the second epitaxial layer exposed by the injection window by using the photoresist layer outside the injection window as a mask so as to form the preset structure in the second epitaxial layer.
In one embodiment of the present invention, the first epitaxial layer and the second epitaxial layer are N-type epitaxial layers, and the impurity ions are P-type impurity ions.
The invention also provides a semiconductor device which is prepared by adopting the preparation method of any one of the above.
The invention has the beneficial effects that in combination with the prior art:
In the preparation process of the semiconductor device prepared layer by layer, one or more groups of alignment marks are required to be generated on each epitaxial layer for interlayer alignment, and in order to ensure that the alignment marks between the layers are not overlapped, different mark masking plates are required to be used for each epitaxial layer. The method comprises the steps of generating a first alignment mark on a first epitaxial layer through a mark mask, generating the second alignment mark on the second epitaxial layer by using the same mark mask when the second alignment mark is required to be generated on the second epitaxial layer, aligning the device mask with the second alignment mark when the device mask is required to be aligned, and then moving the same distance as the mark mask along the reverse direction of the moving direction of the mark mask, thereby realizing alignment of the device masks among the epitaxial layers and forming a preset structure on the same position of the epitaxial layers. The method only needs one mark mask plate, effectively reduces the number of the mark mask plates and effectively reduces the production cost.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor device according to an embodiment of the present application;
FIG. 2 is a flowchart of step S130 according to an embodiment of the present application;
FIG. 3 is a flowchart of step S150 according to an embodiment of the present application;
FIG. 4 is a flowchart illustrating the step S160 according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a first epitaxial layer formed according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a first alignment mark according to an embodiment of the application;
FIG. 7 is a schematic diagram illustrating a preset structure according to an embodiment of the present application;
FIG. 8 is a schematic diagram illustrating a second epitaxial layer formation in accordance with one embodiment of the present application;
FIG. 9 is a schematic diagram illustrating generation of a second alignment mark according to an embodiment of the present application;
FIG. 10 is a schematic diagram illustrating the formation of a preset structure on a second epitaxial layer according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a multi-layered epitaxial layer after formation in accordance with one embodiment of the present application;
FIG. 12 is a schematic view of a wafer according to an embodiment of the present application;
FIG. 13 is a schematic diagram of an exposure unit according to an embodiment of the application.
Description of element numbers:
100. The semiconductor device comprises a substrate, 210, a first epitaxial layer, 211, a first alignment mark, 220, a second epitaxial layer, 221, a second alignment mark, 230, a third epitaxial layer, 231, a third alignment mark, 240, a photoresist layer, 270, a seventh epitaxial layer, 271, a seventh alignment mark, 280, an injection window, 290, a preset structure, 300, an exposure unit, 310, a chip area, 320 and a cutting channel.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. It is also to be understood that the terminology used in the examples of the invention is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the invention. The test methods in the following examples, in which specific conditions are not noted, are generally conducted under conventional conditions or under conditions recommended by the respective manufacturers.
Where numerical ranges are provided in the examples, it is understood that unless otherwise stated herein, both endpoints of each numerical range and any number between the two endpoints are significant both in the numerical range. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs and to which this invention belongs, and any method, apparatus, or material of the prior art similar or equivalent to the methods, apparatus, or materials described in the examples of this invention may be used to practice the invention.
It should be understood that the terms such as "upper," "lower," "left," "right," "middle," and "a" and the like are used in this specification for descriptive purposes only and not for purposes of limitation, and that the invention may be practiced without materially departing from the novel teachings and without departing from the scope of the invention.
In the existing preparation process of the semiconductor device prepared layer by layer, one or more groups of alignment marks are required to be generated on each epitaxial layer for interlayer alignment, so that in order to ensure that the alignment marks between the layers do not interfere with each other under alignment illumination, the alignment marks on each epitaxial layer are required to be arranged at different positions, and correspondingly, different mark mask plates are required to be designed and used for each epitaxial layer to form the alignment marks.
Taking Super Junction power devices as an example, with the development of new energy automobiles, the demand for Super Junction MOSFETs (Super Junction > 200V) for high voltage fields is also increasing. The super junction is a groove type structure which is formed by N type and P type longitudinally alternating in an epitaxial layer, after voltage is applied, a depletion layer which is equivalent to the groove depth can be formed, and the diffusion path of the depletion layer is far smaller than that of a general planar MOSFET, so that the on-state resistance (Rdson) of the device can be effectively reduced. Currently, the super junction is mostly manufactured in a planar Multi-EPI (Multi-layer epitaxial stack) mode in the industry.
The Multi-EPI process is earliest and mature, and mainly comprises the steps of doping and thermally propelling for multiple times on a planar silicon substrate by adopting a multilayer epitaxial growth technology, namely, taking 'growth-ion implantation-annealing' as a layer, and repeatedly forming multiple PN junctions for multiple times, so that the super junction MOS structure is realized. The high-voltage source has the advantages that P, N ions are relatively uniform in concentration, the high-voltage source has ultralow on-resistance and junction capacitance, high efficiency and small heating, and can adapt to higher switching frequency, so that the high-voltage source has great advantages in the aspects of electric leakage, high temperature, long-term reliability and the like. But after each epitaxial layer grows, ion implantation is needed, and in order to ensure that interlayer ion implantation can be aligned, the device mask plate is required to be aligned before each ion implantation, and the device mask plate can be aligned through an alignment mark on the epitaxial layer. In order to improve the accuracy of the alignment marks, the alignment marks between different layers are distributed in a staggered mode, so that on one hand, interference among the alignment marks is prevented, and on the other hand, the alignment marks can be ensured to be regular in shape, and the recognition is convenient. In the prior art, the mask plate for forming the alignment mark is different for each layer in the multilayer epitaxial stacking technology, namely, one mark mask plate is needed for each epitaxial layer, so that higher cost is needed. In view of the above, the application provides a method for manufacturing a semiconductor device, which can effectively reduce the number of mark mask plates required in the manufacturing process, thereby reducing the manufacturing cost.
Referring to fig. 1, a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown in fig. 1, where a MOSFET chip is taken as an example to illustrate the method, and the method may include the following steps:
step S110, forming a first epitaxial layer 210 on the substrate 100;
Step S120, providing a mark mask, and forming a first alignment mark 211 on the first epitaxial layer 210 by using the mark mask, where the first alignment mark 211 is located in the preset exposure unit 300;
Step S130, providing a device mask, aligning the device mask with the exposure unit 300 by using the first alignment mark 211, and forming a preset structure 290 on the first epitaxial layer 210 in the exposure unit 300 by using the device mask;
step S140, forming a second epitaxial layer 220 on the first epitaxial layer 210;
Step S150, forming a second alignment mark 221 on the second epitaxial layer 220 by using the mark mask, where the second alignment mark 221 is located in the exposure unit 300, and an integer multiple of a device unit distance is spaced between the second alignment mark 221 and the first alignment mark 211;
Step S160, after aligning the alignment mark pattern on the device mask with the second alignment mark 221, driving the device mask to move by an integer multiple of the device unit distance to align the device mask with the second alignment mark 221, and then moving by an integer multiple of the device unit distance to align the device mask with the exposure unit 300, and forming a preset structure 290 on the second epitaxial layer 220 in the exposure unit 300 by using the device mask.
Referring to fig. 5 to 13, fig. 5 to 13 are schematic views illustrating steps of an exemplary method for manufacturing a semiconductor device according to an embodiment of the present application, in which the semiconductor device adopts a multi-layer epitaxial stacking process, it should be noted that the edges of the chip region 310 and the scribe line 320 in fig. 5 to 13 are drawn as examples, so as to facilitate recognition, and in the actual manufacturing process, the edges of the chip region 310 and the scribe line 320 on the epitaxial layer are not provided. The following describes in detail the method for manufacturing the semiconductor device according to the embodiment of the present application with reference to fig. 5 to 11:
Step S110, forming the first epitaxial layer 210 on the substrate 100, may include the substrate 100 as shown in fig. 5 to 11, where the substrate 100 material includes semiconductor elements, such as silicon or silicon germanium in single crystal, polycrystalline or amorphous structure, and also includes mixed semiconductor materials, such as silicon carbide, gallium nitride, gallium sesquioxide, alloy semiconductor or combinations thereof, without limitation. The substrate 100 in the present embodiment is an already doped substrate 100, and the substrate 100 in the present embodiment is preferably a silicon carbide substrate 100, and an N-type or P-type silicon carbide substrate 100 may be used, and in the present embodiment, the already doped N-type substrate 100 is taken as an example for illustration. The epitaxial layer material includes, but is not limited to, silicon carbide, gallium nitride or gallium oxide, and in this embodiment, silicon carbide is preferable. The substrate 100 may have a device side on which the circuit layer may be formed, and a back side which may be provided as a side opposite to the device side in the substrate 100. In the present embodiment, the first epitaxial layer 210 is based on a planar silicon epitaxial growth process, and a first epitaxial layer 210 of a specified thickness is formed on the surface of the silicon carbide substrate 100, and the first epitaxial layer 210 is an N-type epitaxial layer.
In step S120, a mark mask is provided, and a first alignment mark 211 is formed on the first epitaxial layer 210 by using the mark mask, where the first alignment mark 211 is located in the preset exposure unit 300. Referring to fig. 13, the exposure unit 300 includes a plurality of chip areas 310 and scribe lines 320, the chip areas 310 are reserved in the exposure unit 300 to form a device structure, and the scribe lines 320 are located at the periphery of the chip areas 310. In the exposure unit 300, each of the chip regions 310 is surrounded by a plurality of dicing streets 320, and the dicing streets 320 are used to assist in wafer dicing positioning after semiconductor device fabrication to separate the individual semiconductor devices from each other on the wafer after dicing.
Referring to fig. 6, in step S120, the alignment mark pattern in the mark mask is transferred onto the first epitaxial layer 210 by conventional photolithography to form a first alignment mark 211 on the first epitaxial layer 210. Specifically, a photoresist is coated on the first epitaxial layer 210 to form a photoresist layer 240 on the first epitaxial layer 210, then the photoresist layer 240 is exposed and developed by using a mark mask plate to form an etching window with an alignment mark pattern on the photoresist layer, the patterned photoresist layer 240 is used as a mask, an etching process, such as Reactive Ion Etching (RIE), is used to etch the first epitaxial layer 210 exposed by the window, and a conventional ashing or stripping process is used to remove the photoresist after etching, so that the first alignment mark 211 is formed on the first epitaxial layer 210. The first alignment mark 211 is used for assisting alignment of the device mask plate and the exposure unit 300, the shape of the first alignment mark 211 comprises a rectangle, a strip shape, a Y shape, an X shape, a cross shape, a return shape, a field shape, a mouth shape, a discontinuous return shape and the like, and the first alignment mark 211 can select one shape or a combination of multiple shapes. In some embodiments, a plurality of first alignment mark 211 patterns may be included on the mark mask, thereby forming a plurality of first alignment marks 211 on the first epitaxial layer 210.
In an embodiment of the present invention, the first alignment mark 211 is located in the scribe line 320, and the first alignment mark 211 located in the scribe line 320 does not affect the chip area 310 including the main circuit and the functional portion, thereby reducing the loss of material.
In the process of photoetching and scanning the wafer, the device mask plate is aligned with the exposure unit 300 by using the first alignment mark 211, and a preset structure 290 is formed on the first epitaxial layer 210 in the exposure unit 300 by the device mask plate. The first alignment mark 211 is used for alignment between layers, ensures the accuracy of ion implantation, and ensures the consistency of ion implantation positions between layers.
Referring to fig. 2, fig. 2 is a flowchart of step S130 according to an embodiment of the application, which includes the following steps:
Step S210, forming a photoresist layer 240 on the first epitaxial layer 210;
A photoresist layer 240 is coated on the first epitaxial layer 210.
Step S220, aligning the alignment mark pattern on the device mask with the first alignment mark 211, so as to align the device mask with the exposure unit 300.
In step S220, the alignment of the device mask and the exposure unit 300 is confirmed by matching the reflected light of the first alignment mark 211 under the alignment light with the alignment mark pattern on the device mask. When the device mask is aligned with the exposure unit 300, the device region pattern on the device mask is aligned with the chip region 310 in the exposure unit 300.
In step S230, an implantation window 280 is formed on the photoresist layer 240 by exposing using the implantation region pattern on the device mask as a reference.
The photoresist layer 240 may be a positive photoresist or a negative photoresist. In an example, a photoresist layer 240 is formed by using a positive photoresist, the device mask is disposed above the photoresist layer 240, the first epitaxial layer 210 coated with the photoresist layer 240 is exposed by using light, the characteristics of the photoresist layer 240 are changed after the photoresist layer 240 is sensitized, and the photosensitive portion of the positive photoresist becomes easily dissolved. The first epitaxial layer 210 is then developed and the positive photoresist is dissolved after development, leaving only the non-illuminated portions, thereby forming an implantation window 280 in the exposed photoresist layer 240. If negative photoresist is used, the illuminated portion becomes insoluble and remains after development.
In step S240, impurity ions are implanted into the first epitaxial layer 210 exposed by the implantation window 280 by using the photoresist layer 240 except the implantation window 280 as a mask, so as to form a preset structure 290 in the first epitaxial layer 210.
For example, the first epitaxial layer 210 is an N-type epitaxial layer, and P-type impurity ions are implanted by means of impurity ion implantation to form P-type regions, and the P-type regions and the N-type regions are alternately arranged to form a superjunction structure. The P-type impurity ions may be boron (B), aluminum (Al), gallium (Ga), indium (In), or the like.
With continued reference to fig. 1, in step S140, a second epitaxial layer 220 is formed on the first epitaxial layer 210.
In step S140, a second epitaxial layer 220 identical to the first epitaxial layer 210 may be formed on the first epitaxial layer 210 by any suitable Deposition process, such as chemical Vapor Deposition (Chemical Vapor Deposition, CVD), physical Vapor Deposition (Physical Vapor Deposition, PVD), plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD), atomic layer Deposition (Atomic layer Deposition, ALD), etc., and the second epitaxial layer 220 is formed integrally with the first epitaxial layer 210.
In step S150, a second alignment mark 221 is formed on the second epitaxial layer 220 by using the mark mask, where the second alignment mark 221 is located in the exposure unit 300 where the first alignment mark 211 is located, and an integer multiple of a distance is spaced between the second alignment mark 221 and the first alignment mark 211.
A second alignment mark 221 for interlayer alignment is formed on the second epitaxial layer 220 using the same mark mask, and the second alignment mark 221 is used to assist alignment of the device mask with the exposed area on the second epitaxial layer 220. It should be noted that, the device unit size includes the sum of the sizes of the chip area 310 and the scribe line 320 on one side of the chip area 310 in a horizontal direction, for example, the distance of the mark mask moving one device unit compared to the first alignment mark 211, that is, the distance of the sum of the sizes of the chip area 310 and the scribe line 320 on one side in the horizontal direction is moved, so that the second alignment mark 221 formed on the second epitaxial layer 220 by using the mark mask is still located in the scribe line 320, and does not affect the chip area including the main circuit and the functional portion.
Referring to fig. 3, fig. 3 is a flowchart of step S150 according to an embodiment of the application, which includes the following steps:
Step S310, coating and forming a photoresist layer 240 on the second epitaxial layer 220;
Step 320, after aligning the alignment mark pattern on the mark mask with the first alignment mark 211, driving the mark mask to move an integer multiple distance of the device unit;
The distance between the second alignment mark 221 and the first alignment mark 211 in the horizontal direction can be effectively controlled by moving the mark mask plate by integer times of the device unit distance, so that the alignment marks can be formed at different positions of the epitaxial layers by one mark mask plate, thereby meeting the requirements of forming the alignment marks between different epitaxial layers and meeting the alignment requirements between the epitaxial layers.
Step S330, forming a second alignment mark 221 on the second epitaxial layer 220 by using the moved mark mask. The first alignment mark 211 and the second alignment mark 221 are spaced apart from each other by an integer multiple of the device unit in the horizontal direction and do not overlap in the depth direction.
Illustratively, the first alignment mark 211 and the second alignment mark 221 are positioned within two parallel scribe lines 320 in the exposure unit 300.
The first alignment mark 211 is located in the scribe line 320, and compared with the distance of the moving device unit by an integer multiple when the first alignment mark 211 is formed, the second alignment mark 221 is still formed in the scribe line 320, and the second alignment mark 221 and the first alignment mark 211 are located in the scribe line 320 in parallel, so that the second alignment mark 221 and the first alignment mark 211 are not overlapped in the depth direction, and the influence of the first alignment mark 211 on the second alignment mark 221 is avoided.
With continued reference to fig. 1, in step S160, after the alignment mark pattern on the device mask is aligned with the second alignment mark 221, the device mask is driven to move in the horizontal direction along the second alignment mark 221 toward the first alignment mark 211 by an integer multiple of the distance, so that the device mask is aligned with the exposure unit 300, and a preset structure 290 is formed on the second epitaxial layer 220 in the exposure unit 300 through the device mask.
After the device mask is aligned to the second alignment mark 221, the device mask is moved along the direction opposite to the moving direction of the mark mask by a distance equal to the moving distance of the mark mask, that is, the device mask is moved along the second alignment mark 221 towards the first alignment mark 211 in the horizontal direction, the moving distance is the horizontal distance between the second alignment mark 221 and the first alignment mark 211, so that the device mask is aligned to the first alignment mark 211 in the vertical direction, that is, the device mask is aligned to the exposure unit 300, and the preset structure 290 formed on the second epitaxial layer 220 by the device mask is consistent with the preset structure 290 formed on the first epitaxial layer 210 in position, so that the impurity ions injected or diffused at the preset structure 290 are connected to form an integral area.
Referring to fig. 4, fig. 4 is a flowchart illustrating a step S160 according to an embodiment of the application, which includes the following steps:
Step S410, forming a photoresist layer 240 on the second epitaxial layer 220;
step S420, aligning the alignment mark pattern on the device mask plate with the second alignment mark 221;
Step S430, driving the device mask plate to move the device unit for an integral multiple distance along the second alignment mark 221 towards the first alignment mark 211 in the horizontal direction, so that the device mask plate is aligned with the exposure unit 300;
The moving direction of the device mask is opposite to the moving direction of the mark mask, a second alignment mark 221 which is a certain distance away from the first alignment mark 211 in the horizontal direction is formed after the mark mask moves an integral multiple of the distance of the device unit, after the device mask is aligned with the second alignment mark 221, the device mask moves reversely in the moving direction of the mark mask by a distance equal to the moving distance of the mark mask, so that the device mask reaches the alignment position of the first alignment mark 211, and the device mask is aligned with the exposure unit 300.
Step S440, taking the pattern of the implantation area on the device mask plate as a reference, and exposing on the photoresist layer 240 by using a conventional photolithography method to form an implantation window 280;
in step S450, impurity ions are implanted into the second epitaxial layer 220 exposed by the implantation window 280 by using the photoresist layer 240 outside the implantation window 280 as a mask, so as to form a preset structure 290 in the second epitaxial layer 220.
The preset structure 290 formed on the second epitaxial layer 220 is at the same position in the longitudinal direction as the preset structure 290 formed on the first epitaxial layer 210, and the preset structure 290 of the second epitaxial layer 220 is integrally connected with the preset structure 290 on the first epitaxial layer 210.
Further, the adjacent alignment marks do not overlap each other in the depth direction, and the distances between the projections of the adjacent alignment marks on the substrate 100 in the horizontal direction are the same, so that the alignment of the device mask plate and the alignment marks is facilitated, the device mask plate returns to the first exposure position, and the alignment of the preset structure 290 between the epitaxial layers is ensured.
In an embodiment of the present invention, the method further includes forming a third epitaxial layer 230 on the second epitaxial layer 220, and then forming a preset structure 290 on the third epitaxial layer 230 until a preset number of epitaxial layers are formed on the substrate 100, and forming the preset structure 290 in the preset number of epitaxial layers, so as to satisfy the preparation of the semiconductor device with a multi-layer epitaxial layer structure, such as a multi-layer epitaxial process for a super junction power device.
Referring to fig. 5 to 11, in an embodiment of the present invention, a semiconductor device has 7 epitaxial layers, and the preparation method includes forming 7 epitaxial layers on the substrate 100, and forming the preset structures 290 in the 7 epitaxial layers.
After the second epitaxial layer 220 forms the preset structure 290, the P-type impurity ions on the second epitaxial layer 220 and the P-type impurity ions on the first epitaxial layer 210 form an overall columnar structure, thereby forming a super junction PN junction.
And generating a third epitaxial layer 230 on the second epitaxial layer 220, moving the device unit by an integer multiple distance along the same direction on the basis of forming the second alignment mark 221 by the mark mask, and forming a third alignment mark 231 on the third epitaxial layer 230 by using the moved mark mask. Further, the distance moved by the mark mask when forming the third alignment mark 231 is equal to the distance moved by the mark mask when forming the second alignment mark 221, i.e. the horizontal distance between the first alignment mark 211 and the second alignment mark 221 is the same as the horizontal distance between the second alignment mark 221 and the third alignment mark 231, for example, the distance is one device unit in the horizontal direction, which is more convenient for the alignment of the device mask from layer to layer.
The device mask is aligned with the third alignment mark 231 and then the device mask is moved a total distance of movement of the mark mask in a direction opposite to the direction of movement of the mark mask. In other words, after the device mask is aligned with the third alignment mark 231, the third alignment mark 231 is moved in the horizontal direction by the same distance as the first alignment mark 211 in the direction from the third alignment mark 231 to the first alignment mark 211. Using the device mask, forming an implantation window 280 on the third epitaxial layer 230 by using the lithography means with reference to the implantation region pattern on the device mask, and implanting impurity ions into the second epitaxial layer 220 exposed by the implantation window 280 by using an ion implantation process to form a preset structure 290 on the third epitaxial layer 230. The preset structure 290 formed on the third epitaxial layer 230 is consistent with the preset structure 290 formed on the second epitaxial layer 220 and the preset structure 290 formed on the first epitaxial layer 210, and the third epitaxial layer 230, the second epitaxial layer 220 and the P-type region on the first epitaxial layer 210 are connected to form a super junction PN junction with the N-type epitaxial layer.
The above steps are repeated until a seventh epitaxial layer 270 is formed, and a seventh alignment mark 271 and a preset structure 290 are formed on the seventh epitaxial layer 270.
After all epitaxial layers are formed and all impurity ions are implanted, annealing treatment is carried out to repair lattice damage caused by ion implantation, and the implanted impurity ions are activated at the same time to occupy correct positions in a silicon lattice and form required electrical activity.
In the preparation of the semiconductor device of the present application, other processes are required, and reference is made to the prior art, which is not described in detail herein.
According to the preparation method of the semiconductor device, the alignment marks can be respectively generated on the multiple epitaxial layers only by using one mark mask plate, and compared with the existing method that different mark mask plates are designed for each epitaxial layer, the preparation method has the advantages that the cost is effectively reduced, and the competitiveness is improved.
The application also provides a semiconductor device manufactured by adopting any one of the preparation methods, and other procedures required by the preparation of the semiconductor device refer to the prior preparation technology of the semiconductor device, and the application is not repeated.
According to the preparation method of the semiconductor device, in the multilayer epitaxial stacking process, the alignment marks can be formed on each epitaxial layer respectively only by using one mark mask plate, so that the number of the mark mask plates is effectively reduced, and the cost is reduced. Therefore, the invention effectively overcomes some practical problems in the prior art, thereby having high utilization value and use significance. The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
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|---|---|---|---|---|
| JPH06349705A (en) * | 1993-06-08 | 1994-12-22 | Nikon Corp | Alignment method |
| US6128070A (en) * | 1999-03-26 | 2000-10-03 | Mosel Vitelic Inc. | Monitor method and apparatus for overlay alignment of a stepper |
| US20090040536A1 (en) * | 2007-08-09 | 2009-02-12 | Nanya Technology Corp. | Mark for alignment and overlay, mask having the same, and method of using the same |
| CN102156392A (en) * | 2010-02-11 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Device and method for detecting alignment parameter of photoetching machine |
| US20130001193A1 (en) * | 2011-06-28 | 2013-01-03 | International Business Machines Corporation | Alignment marks for multi-exposure lithography |
| CN112631069A (en) * | 2020-12-22 | 2021-04-09 | 长江存储科技有限责任公司 | Mask plate and method for correcting alignment precision |
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- 2025-01-02 CN CN202510000479.7A patent/CN119400686A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06349705A (en) * | 1993-06-08 | 1994-12-22 | Nikon Corp | Alignment method |
| US6128070A (en) * | 1999-03-26 | 2000-10-03 | Mosel Vitelic Inc. | Monitor method and apparatus for overlay alignment of a stepper |
| US20090040536A1 (en) * | 2007-08-09 | 2009-02-12 | Nanya Technology Corp. | Mark for alignment and overlay, mask having the same, and method of using the same |
| CN102156392A (en) * | 2010-02-11 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Device and method for detecting alignment parameter of photoetching machine |
| US20130001193A1 (en) * | 2011-06-28 | 2013-01-03 | International Business Machines Corporation | Alignment marks for multi-exposure lithography |
| CN112631069A (en) * | 2020-12-22 | 2021-04-09 | 长江存储科技有限责任公司 | Mask plate and method for correcting alignment precision |
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