CN119383999A - Silicon carbide device and preparation method thereof - Google Patents
Silicon carbide device and preparation method thereof Download PDFInfo
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- CN119383999A CN119383999A CN202411488392.0A CN202411488392A CN119383999A CN 119383999 A CN119383999 A CN 119383999A CN 202411488392 A CN202411488392 A CN 202411488392A CN 119383999 A CN119383999 A CN 119383999A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 123
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 121
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 229910052751 metal Inorganic materials 0.000 claims abstract description 78
- 239000002184 metal Substances 0.000 claims abstract description 78
- 238000000034 method Methods 0.000 claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000010949 copper Substances 0.000 claims abstract description 13
- 229910052802 copper Inorganic materials 0.000 claims abstract description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 13
- 239000010937 tungsten Substances 0.000 claims abstract description 13
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 12
- 230000017525 heat dissipation Effects 0.000 claims description 43
- 239000007769 metal material Substances 0.000 claims description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 235000010675 chips/crisps Nutrition 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明公开了一种碳化硅器件及其制备方法。本发明通过在完成晶圆正面工艺步骤后，利用硅通孔工艺技术在晶圆背面的碳化硅衬底部分开设延伸到衬底内部靠近外延层位置的凹槽，在凹槽内填充铜或者钨，并将晶圆背面凹槽外多余的填充金属磨除，后续进行背面金属的生长，完成背面工艺。硅通孔工艺成熟简单，凹槽内所填充的铜和钨作为电阻低、导热性能好的材料，能有效传导出热量，降低晶圆损害概率，能够在保证器件能正常运行的情况下，有效传导出热量，解决碳化硅器件短路耐受能力差的问题。
The present invention discloses a silicon carbide device and a preparation method thereof. After completing the wafer front process steps, the present invention uses a through silicon via process technology to open a groove extending to the inside of the substrate near the epitaxial layer in the silicon carbide substrate portion on the back of the wafer, fills the groove with copper or tungsten, and removes the excess filling metal outside the groove on the back of the wafer, and subsequently grows the back metal to complete the back process. The through silicon via process is mature and simple. The copper and tungsten filled in the groove are materials with low resistance and good thermal conductivity, which can effectively conduct heat and reduce the probability of wafer damage. It can effectively conduct heat while ensuring that the device can operate normally, solving the problem of poor short-circuit tolerance of silicon carbide devices.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a silicon carbide device and a preparation method thereof.
Background
Silicon carbide (SiC) materials have been attracting attention and research due to their superior physical properties. Compared with the traditional Si device, the SiC device has the characteristics of high voltage, high frequency, working withstand voltage and the like. But silicon carbide devices suffer from poor short circuit resistance. At present, after a Wafer (Wafer) is processed through a back thinning process, the thickness of a SiC substrate layer is far higher than that of an epitaxial layer (EPI), and the epitaxial layer serving as an N drift region is low in concentration and high in heat generation. Although SiC has a higher thermal conductivity than Si, the excessively high current density and thicker substrate still make the chip of the SiC device unable to dissipate heat quickly and efficiently.
By comparing the short circuit reliability of the silicon carbide MOSFET with that of the silicon IGBT under 1200V, the short circuit tolerance capability of the silicon carbide MOSFET is only about 3 microseconds (mu s), and the short circuit tolerance capability is quite different from that of the silicon IGBT device (more than or equal to 10 microseconds). Therefore, under the condition of ensuring the normal operation of the device, the heat dissipation efficiency of the SiC device needs to be improved so as to solve the problem of poor short circuit tolerance of the SiC device.
Disclosure of Invention
The invention aims to solve the technical problem of providing a silicon carbide device and a preparation method thereof, which can effectively conduct heat under the condition of ensuring normal operation of the device and solve the problem of poor short-circuit tolerance of the silicon carbide device.
In order to solve the problems, an embodiment of the invention provides a preparation method of a silicon carbide device, which comprises the steps of providing a substrate, wherein the substrate comprises a silicon carbide substrate and an epitaxial layer, the silicon carbide substrate is provided with a front surface and a back surface which are opposite, the epitaxial layer is formed on the front surface of the silicon carbide substrate, a device structure is formed in the epitaxial layer, at least one groove extending into the silicon carbide substrate is formed on the back surface of the silicon carbide substrate by adopting a through silicon via technology, a metal heat dissipation structure is formed in the groove, and a back metal layer covering the back surface of the silicon carbide substrate and all the metal heat dissipation structures is formed.
In some embodiments, the recess does not expose the epitaxial layer.
In some embodiments, the depth of the groove is less than the thickness of the silicon carbide substrate, and the depth of the groove is greater than half the thickness of the silicon carbide substrate.
In some embodiments, the silicon carbide substrate has a thickness of less than or equal to 110 microns, the recess has a depth of less than or equal to 100 microns, the recess has a depth of greater than 55 microns, and the recess has an opening width in the range of 25 microns to 40 microns.
In some embodiments, the step of forming at least one recess extending into the silicon carbide substrate on the back surface of the silicon carbide substrate using through silicon via technology specifically includes forming a plurality of the recesses extending in a direction perpendicular to the back surface of the silicon carbide substrate and uniformly distributed in a direction parallel to the back surface of the silicon carbide substrate.
In some embodiments, the step of forming the metal heat dissipation structure in the groove specifically includes depositing a first metal material to form a first metal material layer that fills the groove and covers the back surface of the silicon carbide substrate, and removing the first metal material layer outside the groove, wherein the remaining first metal material layer in the groove forms the metal heat dissipation structure.
In some embodiments, the step of removing the first metal material layer outside the recess specifically includes removing the first metal material layer outside the recess by chemical mechanical polishing.
In some embodiments, the step of forming a back metal layer covering the back surface of the silicon carbide substrate and all the metal heat dissipation structures specifically includes performing a metal sputtering process to form a second metal material layer as the back metal layer.
In some embodiments, the material of the metal heat dissipation structure is metallic copper or metallic tungsten, and the material of the back metal layer is selected from titanium, nickel, silver, or an alloy thereof.
In order to solve the above problems, an embodiment of the present invention further provides a silicon carbide device, where the silicon carbide device is prepared by using the method for preparing a silicon carbide device according to the present invention.
According to the technical scheme, after the front-side process step of the wafer is completed, a groove which extends to the position, close to the epitaxial layer, inside the substrate is formed in the silicon carbide substrate part on the back side of the wafer by utilizing the through-silicon-via process technology, copper or tungsten is filled in the groove, redundant filling metal outside the groove on the back side of the wafer is removed, and then growth of back-side metal is carried out, so that the back-side process is completed. The silicon through hole technology is mature and simple, copper and tungsten filled in the groove are used as materials with low resistance and good heat conduction performance, heat can be effectively conducted, the wafer damage probability is reduced, the heat can be effectively conducted under the condition that the device can normally operate, and the problem that the short circuit tolerance capability of the silicon carbide device is poor is solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram showing steps of a method for fabricating a silicon carbide device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a device structure of a substrate according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a device after forming a recess according to an embodiment of the present invention;
Fig. 4A to fig. 4B are schematic views of a device structure after forming a metal heat dissipation structure according to an embodiment of the present invention;
Fig. 5 is a schematic view of a device structure after forming a back metal layer according to an embodiment of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
An embodiment of the invention provides a preparation method of a silicon carbide device, which is characterized in that after the front process step of a wafer is finished, a groove which extends to the position close to an epitaxial layer (EPI) in the substrate is formed in a silicon carbide substrate part on the back of the wafer by utilizing a Through Silicon Via (TSV) process technology, copper or tungsten is filled in the groove, redundant filling metal outside the groove on the back of the wafer is ground, and then the growth of the back metal is carried out, so that the back process is finished. The TSV process is mature and simple, copper and tungsten filled in the grooves are used as materials with low resistance and good heat conduction performance, heat can be effectively conducted, the wafer damage probability is reduced, the heat can be effectively conducted under the condition that the device can normally operate, and the problem that the short circuit tolerance capability of the silicon carbide device is poor is solved.
Referring to fig. 1 to 5, fig. 1 is a schematic step diagram of a method for manufacturing a silicon carbide device according to an embodiment of the present invention;
fig. 3 is a schematic view of a device structure after forming a groove according to an embodiment of the present invention, fig. 4A to fig. 4B are schematic views of a device structure after forming a metal heat dissipation structure according to an embodiment of the present invention, and fig. 5 is a schematic view of a device structure after forming a back metal layer according to an embodiment of the present invention.
As shown in FIG. 1, the preparation method of the silicon carbide device of the embodiment comprises the following steps of S1, providing a substrate, wherein the substrate comprises a silicon carbide substrate and an epitaxial layer, the silicon carbide substrate is provided with a front surface and a back surface which are opposite, the epitaxial layer is formed on the front surface of the silicon carbide substrate, a device structure is formed in the epitaxial layer, S2, forming at least one groove extending into the silicon carbide substrate on the back surface of the silicon carbide substrate by adopting a through silicon via technology, S3, forming a metal heat dissipation structure in the groove, and S4, forming a back metal layer covering the back surface of the silicon carbide substrate and all the metal heat dissipation structures.
Referring to step S1 and fig. 2, a base is provided, the base includes a silicon carbide substrate 21 and an epitaxial layer 22, wherein the silicon carbide substrate 21 has a front surface 211 and a back surface 210 opposite to each other, the epitaxial layer 22 is formed on the front surface 211 of the silicon carbide substrate 211, and device structures 291, 292 are formed in the epitaxial layer 22. That is, the substrate provided in this embodiment has completed the wafer front side process steps.
In this embodiment, the silicon carbide substrate 21 is used to support the epitaxial layer 22 and the device structures 291, 292 formed therein thereon. The device structures 291, 292 may be respective SiC power devices. In this embodiment, the silicon carbide substrate 21 is made of silicon carbide (SiC). In this embodiment, the silicon carbide substrate 21 has excellent thermal conductivity, high temperature resistance and mechanical strength, and is suitable for applications in high power, high frequency and high temperature environments. In addition, the silicon carbide substrate 21 has lower leakage current and higher breakdown voltage, and can provide better electrical performance. The epitaxial layer 22 is a thin film layer having substantially the same crystal structure and electrical properties as those of the SiC substrate, which is epitaxially grown (EPI for short) on the silicon carbide substrate 21. The epitaxial layer 22 may be grown using a chemical vapor deposition (Chemical Vapor Deposition, CVD for short). CVD is a method of forming a thin film by chemical reaction of one or more gas-phase compounds or elements containing thin film elements on the surface of a substrate.
Referring to step S2 and fig. 3, at least one recess 30 extending into the silicon carbide substrate 21 is formed on the back surface 210 of the silicon carbide substrate 21 by using a through-silicon via technique. That is, the present embodiment utilizes a Through Silicon Via (TSV) process technique to form a recess in the wafer backside after the wafer front side process step is completed. Specifically, the recess 30 extends to a position inside the silicon carbide substrate 21 near the epitaxial layer 22.
In some embodiments, the wafer may be flipped after the wafer front side process step is completed and the backside 210 of the silicon carbide substrate 21 may be thinned. Wherein the thickness of the silicon carbide substrate 21 thinned depends on the pressure resistance of the silicon carbide device.
Through silicon vias (Through Silicon Via, abbreviated as TSV) are techniques that make vertical openings by etching or laser between chips, wafers and wafers, and then fill the holes with conductive materials such as copper, tungsten, polysilicon, etc. Compared with the inductively coupled plasma etching (ICP) method which utilizes gas glow discharge to generate plasma and realizes the pattern transfer process from a photoresist mask to the chip surface through the dual actions of chemistry and physics, the through silicon via technology adopted in the embodiment has mature and simple process and low cost.
In this embodiment, the recess 30 does not expose the epitaxial layer 22. That is, the groove 30 extends to a position inside the silicon carbide substrate 21 near the epitaxial layer 22, and the bottom of the groove 30 is located in the silicon carbide substrate 21 and does not expose the epitaxial layer 22, so as to avoid affecting the epitaxial layer 22 and the device structure in the epitaxial layer 22, and ensure that the device can operate normally.
In some embodiments, the depth H2 of the recess 30 is less than the thickness H1 of the silicon carbide substrate 21, such that the recess 30 does not expose the epitaxial layer 22. Further, the depth H2 of the groove 30 is greater than half the thickness H1 of the silicon carbide substrate 21. I.e., H1> H2> H1/2. The depth of the groove is deepened as much as possible, but the epitaxial layer is not exposed, so that the heat radiating area of a subsequently formed metal heat radiating structure can be increased as much as possible, heat is effectively conducted, the problem of poor short circuit tolerance of a silicon carbide device is solved, the epitaxial layer 22 and the device structure in the epitaxial layer 22 can be prevented from being influenced, and the normal operation of the device is ensured.
In some embodiments, the thickness H1 of the silicon carbide substrate 21 is less than or equal to 110 micrometers, the depth H2 of the groove 30 is less than or equal to 100 micrometers, the depth H2 of the groove 30 is greater than 55 micrometers, and the opening width W2 of the groove 30 has a size ranging from 25 micrometers to 40 micrometers. The depth H2 of the grooves 30 may be, for example, 60 microns, 65 microns, 70 microns, 75 microns, 80 microns, 85 microns, 90 microns, 95 microns, 99 microns, 100 microns, etc. The opening width W2 of the recess 30 may be, for example, 25 microns, 28 microns, 30 microns, 32 microns, 35 microns, 38 microns, 40 microns, etc.
In this embodiment, the step of forming at least one groove 30 extending into the silicon carbide substrate 21 on the back surface 210 of the silicon carbide substrate 21 by using the through-silicon via technology specifically includes forming a plurality of grooves 30, where the plurality of grooves 30 extend in a direction perpendicular to the back surface 210 of the silicon carbide substrate 21 and are uniformly distributed in a direction parallel to the back surface 210 of the silicon carbide substrate 21. Specifically, the density of the grooves 30 in the silicon carbide substrate 21 is determined according to the actual process requirements.
Referring to step S3 and fig. 4B, a metal heat dissipation structure 41 is formed in the recess 30.
In this embodiment, the step of forming the metal heat dissipation structure 41 in the recess 30 specifically includes (1) depositing a first metal material to form a first metal material layer 410 that fills the recess 30 and covers the back surface 210 of the silicon carbide substrate 21, as shown in fig. 4A, (2) removing the first metal material layer 410 except for the recess 30, and forming the metal heat dissipation structure 41 by the first metal material layer 410 remaining in the recess 30, as shown in fig. 4B.
In the above embodiment, the step of removing the first metal material layer 410 outside the recess 30 specifically includes removing the first metal material layer 410 outside the recess 30 by Chemical Mechanical Polishing (CMP). By adopting the chemical mechanical polishing process, the exposed surface of the metal heat dissipation structure 41 is a smooth surface, and the exposed surface of the metal heat dissipation structure 41 is flush with the back surface 210 of the silicon carbide substrate 21, which is beneficial to the formation of the subsequent back metal layer.
In some embodiments, the thickness of the metal heat dissipation structure 41 (i.e., the depth H2 of the groove 30) is less than or equal to 100 micrometers, the thickness of the metal heat dissipation structure 41 is greater than 55 micrometers, and the width of the metal heat dissipation structure 41 (i.e., the opening width W2 of the groove 30) ranges from 25 micrometers to 40 micrometers. The thickness of the metal heat dissipation structure 41 may be, for example, 60 microns, 65 microns, 70 microns, 75 microns, 80 microns, 85 microns, 90 microns, 95 microns, 99 microns, 100 microns, etc. The width of the metal heat dissipation structure 41 may be, for example, 25 microns, 28 microns, 30 microns, 32 microns, 35 microns, 38 microns, 40 microns, etc.
In this embodiment, the material of the metal heat dissipation structure 41 is metal copper or metal tungsten. By filling the grooves 30 on the back surface 210 of the silicon carbide substrate 21 with copper and tungsten materials with low resistance and good heat conduction performance, the heat dissipation of the silicon carbide substrate 21 is enhanced, the heat can be effectively conducted, the thermal resistance of the device is reduced, the heat dissipation performance of the device is improved, and the wafer damage probability is reduced.
Referring to step S4 and fig. 5, a back metal layer 51 is formed to cover the back surface 210 of the silicon carbide substrate 21 and all the metal heat dissipation structures 41.
In this embodiment, the step of forming the back metal layer 51 covering the back surface 210 of the silicon carbide substrate 21 and all the metal heat dissipation structures 41 specifically includes performing a metal sputtering process to form a second metal material layer as the back metal layer 51, and turning over the wafer again after the process is completed.
In some embodiments, the material of the back metal layer 51 is selected from titanium, nickel, silver, or alloys thereof. Specifically, the back metal layer 51 may be formed by sputtering deposition of metal Ti/Ni/Ag on the back surface 210 of the silicon carbide substrate 21 using a magnetron sputtering technique.
Based on the same inventive concept, an embodiment of the present invention provides a silicon carbide device, which is manufactured by adopting the method for manufacturing the silicon carbide device.
Referring to fig. 1-5, the silicon carbide device of the present embodiment includes a silicon carbide substrate 21, an epitaxial layer 22, device structures 291, 292 formed in the epitaxial layer 22, at least one recess 30 formed on the back surface of the silicon carbide substrate 21, a metal heat dissipation structure 41 filled in the recess 30, and a back metal layer 51 formed on the back surface of the silicon carbide substrate 21.
Specifically, the silicon carbide substrate 21 has a front surface 211 and a back surface 210 opposite to each other, and the epitaxial layer 22 is formed on the front surface 211 of the silicon carbide substrate 211. The recess 30 is formed using a through silicon via technique and extends from the back surface 210 of the silicon carbide substrate 21 into the silicon carbide substrate 21. The exposed surface of the metal heat dissipation structure 41 is a smooth surface, and the exposed surface of the metal heat dissipation structure 41 is flush with the back surface 210 of the silicon carbide substrate 21. The back metal layer 51 covers the back surface 210 of the silicon carbide substrate 21 and all of the metal heat dissipating structure 41.
In this embodiment, the thickness of the metal heat dissipation structure 41 (i.e., the depth H2 of the groove 30) is smaller than the thickness H1 of the silicon carbide substrate 21, so that the metal heat dissipation structure 41 does not contact the epitaxial layer 22. Further, the thickness of the metal heat dissipation structure 41 is greater than half the thickness H1 of the silicon carbide substrate 21. The depth of the groove is deepened as much as possible, but the epitaxial layer is not exposed, so that the heat radiating area of the formed metal heat radiating structure can be increased as much as possible, heat is effectively conducted, the problem of poor short circuit tolerance of the silicon carbide device is solved, the epitaxial layer 22 and the device structure in the epitaxial layer 22 can be prevented from being influenced, and normal operation of the device is ensured.
In some embodiments, the thickness H1 of the silicon carbide substrate 21 is less than or equal to 110 micrometers, the thickness of the metal heat dissipation structure 41 (i.e., the depth H2 of the groove 30) is less than or equal to 100 micrometers, the thickness of the metal heat dissipation structure 41 is greater than 55 micrometers, and the width of the metal heat dissipation structure 41 (i.e., the opening width W2 of the groove 30) ranges from 25 micrometers to 40 micrometers. The thickness of the metal heat dissipation structure 41 may be, for example, 60 microns, 65 microns, 70 microns, 75 microns, 80 microns, 85 microns, 90 microns, 95 microns, 99 microns, 100 microns, etc. The width of the metal heat dissipation structure 41 may be, for example, 25 microns, 28 microns, 30 microns, 32 microns, 35 microns, 38 microns, 40 microns, etc.
After the front-side process step of the wafer is completed, the silicon carbide substrate part on the back side of the wafer is provided with the groove extending to the position close to the epitaxial layer inside the substrate by utilizing the through-silicon-via process technology, copper or tungsten is filled in the groove, redundant filling metal outside the groove on the back side of the wafer is removed, and then the back-side metal is grown, so that the back-side process is completed. The TSV process is mature and simple, copper and tungsten filled in the grooves are used as materials with low resistance and good heat conduction performance, heat can be effectively conducted, the wafer damage probability is reduced, the heat can be effectively conducted under the condition that the device can normally operate, and the problem that the short circuit tolerance capability of the silicon carbide device is poor is solved.
It should be noted that the terms "comprising" and "having" and their variants are referred to in the document of the present invention and are intended to cover non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. The term "one or more" depends at least in part on the context and may be used to describe a feature, structure, or characteristic in a singular sense or may be used to describe a feature, structure, or combination of features in a plural sense. The term "based on" may be understood as not necessarily intended to express an exclusive set of factors, but may instead, also depend at least in part on the context, allow for other factors to be present that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present invention. In the foregoing embodiments, each embodiment is mainly described for differences from other embodiments, and the same/similar parts between the embodiments are referred to each other.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (10)
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| CN202411488392.0A CN119383999A (en) | 2024-10-23 | 2024-10-23 | Silicon carbide device and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119835979A (en) * | 2025-03-17 | 2025-04-15 | 杭州谱析光晶半导体科技有限公司 | SiC VDMOSFET structure with high heat dissipation and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119835979A (en) * | 2025-03-17 | 2025-04-15 | 杭州谱析光晶半导体科技有限公司 | SiC VDMOSFET structure with high heat dissipation and preparation method thereof |
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