CN119377156A

CN119377156A - SPI communication system and SPI communication method

Info

Publication number: CN119377156A
Application number: CN202411396783.XA
Authority: CN
Inventors: 杜增权
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2024-10-08
Filing date: 2024-10-08
Publication date: 2025-01-28

Abstract

The present disclosure relates to an SPI communication system and an SPI communication method, wherein the SPI communication system includes a master SPI device and a slave SPI device, wherein the slave SPI device is used to: receive a read instruction in an instruction period, and send a read clock signal and a read data signal in a read data period; the master SPI device is used to send an instruction clock signal and a read instruction data signal in an instruction period; and receive a read data signal in a read data period. The embodiment of the present disclosure enables the master SPI device to receive a read data signal sent by a slave SPI device according to a read clock signal sent by the slave SPI device, and since both the read clock signal and the read data signal are driven by the slave SPI device, the read clock signal and the read data signal can maintain a good fixed timing relationship at both the slave/master SPI device end, and the master SPI device uses the read clock signal sent by the slave SPI device, so that it is easy to accurately sample the read data signal sent by the slave SPI device, thereby facilitating the improvement of the SPI communication rate.

Description

SPI communication system and SPI communication method

Technical Field

The disclosure relates to the field of communication technologies, and in particular, to an SPI communication system and an SPI communication method.

Background

At present, in the data reading stage of the SPI (SERIAL PERIPHERAL INTERFACE ) device, the master SPI device sends a clock signal CLK, the slave SPI receives the clock signal CLK sent by the master SPI, and sends read data to the data signal line according to the clock signal CLK, the master SPI receives the read data returned from the SPI, and a large delay is generated during the period, because of the delay, the clock signal CLK and the data signal Dx are originally at the slave SPI device end, the timing sequence of the clock signal CLK and the data signal Dx is good (the rising edge of the CLK is at the center point of each group of bits Dx, wherein each group of bits may be 1bit,2bit,4bit, etc.), and at the master SPI device end, the timing sequence of the clock signal CLK and the data signal Dx is greatly changed relative to the signal at the transmitting end, so that the problem of large read data delay and delay change exists, and the SPI master device needs to adjust the sampling point of the read data, so that accurate sampling to the read data can be ensured, and the data is ensured to be correct.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided an SPI communication system including a master SPI device and a slave SPI device, wherein:

The slave SPI equipment is used for receiving the command clock signal and the command data signal sent by the master SPI equipment in a command period to receive a read command;

The master SPI device is used for sending an instruction clock signal and a read instruction data signal to the slave SPI device in an instruction period, and receiving the read data signal sent by the slave SPI device according to the read clock signal sent by the slave SPI device in a read data period.

In one possible implementation, the master SPI device is used for sending an instruction clock signal and a write instruction data signal to the slave SPI device in an instruction period;

In one possible implementation, the slave SPI device is used for receiving the command clock signal and the command data signal sent by the master SPI device to receive a write command in a command period, and receiving the write clock signal and the write data signal sent by the master SPI device to receive write data in a write data period.

In a possible embodiment, the rising edge of the command clock signal corresponds to a middle position of a first command data signal and the falling edge of the command clock signal corresponds to a middle position of a second command data signal, the cycle being followed by the second command data signal being the next adjacent command data signal to the first command data signal;

In one possible implementation, the rising edge of the write clock signal corresponds to an intermediate position of a first write data signal, and the falling edge of the write clock signal corresponds to an intermediate position of a second write data signal, which is an adjacent next write data signal of the first write data signal, in a cycle;

in one possible embodiment, the rising edge of the read clock signal corresponds to an intermediate position of a first read data signal and the falling edge of the read clock signal corresponds to an intermediate position of a second read data signal, the second read data signal being an adjacent next read data signal of the first read data signal, in a cycle.

In one possible implementation manner, the SPI transmitting ends in the master SPI device and the slave SPI device are configured to:

setting the clock period of the clock signal to 2T, transmitting successive first and second data signals in each clock period, T being the time of a positive value, in each clock period:

Transmitting a first data signal at a start time of a clock cycle;

after T/2, sending rising edge of clock signal;

After T/2, transmitting a second data signal;

after T/2, transmitting the falling edge of the clock signal;

After T/2, the next clock cycle begins.

In one possible implementation, the master SPI device and the slave SPI device are both chips.

According to another aspect of the disclosed embodiments, the disclosed embodiments also provide an SPI communication method applied to an SPI communication system including a master SPI device and a slave SPI device, wherein the method includes receiving an instruction clock signal and an instruction data signal sent by the master SPI device by the slave SPI device in an instruction period to receive a read instruction;

And receiving the read data signal sent by the slave SPI equipment according to the read clock signal sent by the slave SPI equipment in the read data period.

In one possible embodiment, the method further comprises:

Transmitting a command clock signal and a write command data signal to the slave SPI equipment in a command period by using the master SPI equipment;

And receiving the write clock signal and the write data signal sent by the master SPI equipment in the write data period to receive write data.

In one possible embodiment, the method further comprises:

the following steps are executed by using the SPI transmitting end in the master SPI equipment and the slave SPI equipment:

Transmitting a first data signal at a start time of a clock cycle;

after T/2, sending rising edge of clock signal;

After T/2, transmitting a second data signal;

after T/2, transmitting the falling edge of the clock signal;

After T/2, the next clock cycle begins.

According to an aspect of the disclosure, there is provided an electronic device comprising a processor, a memory for storing processor-executable instructions, wherein the processor is configured to invoke the instructions stored in the memory to perform the above method.

According to an aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method.

According to the embodiment of the disclosure, under the condition that the slave SPI device receives the read command of the master SPI device, the read clock signal and the read data signal are sent, so that the master SPI device receives the read data signal according to the read clock signal, and because the read clock signal is driven by the slave SPI device, the read clock signal and the data signal can keep a good fixed time sequence relationship at the slave/master SPI device end, and the master SPI device can accurately sample the read data signal sent by the slave SPI device by using the clock signal sent by the slave SPI device, so that the SPI communication rate can be conveniently improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.

FIG. 1 illustrates a block diagram of an SPI communication system, in accordance with an embodiment of the present disclosure.

FIG. 2a illustrates a timing diagram of a master SPI device write operation, according to an embodiment of the present disclosure.

FIG. 2b shows a timing diagram of a master SPI device read operation in the related art.

FIG. 3 illustrates a timing diagram of a master SPI device read operation, in accordance with an embodiment of the present disclosure.

FIG. 4 shows a single rate (SDR-SINGLE DATA RATE) SPI communication schematic diagram of SPI mode 0 as an example in the related art.

FIG. 5 illustrates an SPI communication schematic in accordance with an embodiment of the present disclosure.

FIG. 6 shows a flowchart of an SPI communication method, according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

In the description of the present disclosure, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication between two elements or in an interaction relationship between two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean that a exists alone, while a and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Referring to fig. 1, fig. 1 shows a block diagram of an SPI communication system according to an embodiment of the present disclosure.

As shown in fig. 1, the SPI communication system includes a master SPI device 10 and a slave SPI device 20, wherein:

The slave SPI device 20 is used for receiving the command clock signal and the command data signal sent by the master SPI device 10 in a command period to receive a read command, and sending the read clock signal and the read data signal to the master SPI device 10 in a read data period;

The master SPI device 10 is used for transmitting a command clock signal and a read command data signal to the slave SPI device 20 in a command period, and receiving the read data signal transmitted from the slave SPI device 20 according to the read clock signal transmitted from the slave SPI device 20 in a read data period.

According to the embodiment of the disclosure, the slave SPI device 20 receives the command clock signal and the command data signal sent by the master SPI device 10 in a command period to receive a read command, sends the read clock signal and the read data signal to the master SPI device 10 in a read data period, and receives the read data signal sent by the slave SPI device according to the read clock signal sent by the slave SPI device in the read data period, and the read clock signal and the data signal can keep a good fixed time sequence relationship at a slave/master SPI device end because the read clock signal is driven by the slave SPI device 20, the master SPI device 10 can easily and accurately sample the read data signal sent by the slave SPI device 20 by using the clock signal sent by the slave SPI device 20, so that the SPI communication rate is convenient to improve, and the master SPI device 10 can improve the accuracy of read data when receiving the read data signal.

The command period in the embodiment of the present disclosure may refer to a period when the master SPI device 10 sends a command clock signal and a command data signal, and the read data period may refer to a period when the slave SPI device 20 sends a read clock signal and a read data signal to the master SPI device 10, and correspondingly, the command period further includes a write data period when the master SPI device 10 sends a write clock signal and a write data signal to the slave SPI device 20, and specific settings of parameters of the write data period, the command period and the read data period may be set by those skilled in the art according to actual situations and needs, so that the embodiment of the present disclosure is not limited.

In one possible implementation, the master SPI device 10 and the slave SPI device 20 may each be a terminal device or a chip, and the terminal device may implement the corresponding functions, for example, by the processing component calling computer readable instructions stored in the memory. In one example, a chip or processing component includes, but is not limited to, a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller in an electronic device having the functionality to execute instructions, and may be implemented in any suitable manner, for example, by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements. Within the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application SPECIFIC INTEGRATED Circuits (ASIC), programmable logic controllers, and embedded microcontrollers.

The terminal device may be a User Equipment (UE), a Mobile device, a User terminal, a handheld device, a computing device, or a vehicle-mounted device, etc., and examples of some terminals are a Mobile Phone, a tablet, a laptop, a palm computer, a Mobile internet device (Mobile Internetdevice, MID), a wearable device, a Virtual Reality (VR) device, an augmented Reality (Augmentedreality, AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in unmanned (SELFDRIVING), a wireless terminal in teleoperation (Remote medical Surgery), a wireless terminal in Smart grid (SMART GRID), a wireless terminal in transportation security (Transportation Safety), a wireless terminal in Smart city (SMART CITY), a wireless terminal in Smart Home (Smart Home), a wireless terminal in the internet of vehicles, etc. For example, the server may be a local server or a cloud server.

Illustratively, SPI communications generally include a chip select signal line (CS), a clock signal line (CLK), and a number of data signal lines (Dx). To speed up data transmission, the data signal lines are typically 2 (DUAL) or 4 (QUAD), or more. To distinguish between reads/writes, an operation may be divided into a first half instruction period (Command Phase) and a second half data period (DATA PHASE). In the related art, the command period is when the master SPI device 10 issues a command (including (read/write) command, address, length, etc. information) to the slave SPI device 20. In the write data period, the master SPI device 10 transmits write data, receives write data from the SPI device 20, and all data signal lines are driven by the master SPI device 10 and are never driven. In the read data period, read data is sent from SPI device 20, while master SPI device 10 receives read data, all data lines are driven from SPI device 20.

Table 1 shows a signal driving description of a write operation in the related art.

TABLE 1

As can be seen from table 1:

master SPI device 10 drives a chip select signal line to transmit chip select signal CS, and receives chip select signal CS from SPI device 20.

Master SPI device 10 drives a clock signal line to transmit clock signal CLK, and slave SPI device 20 receives clock signal CLK.

Write command period master SPI device 10 drives data signal line Dx to transmit a write command, and data signal line Dx is sampled from SPI device 20 to receive a write command.

During a write data period, master SPI device 10 drives data signal line Dx to transmit write data, and data signal line Dx is sampled from SPI device 20 to receive write data.

Referring to FIG. 2a, FIG. 2a shows a timing diagram of a write operation of the master SPI device 10, in accordance with an embodiment of the present disclosure.

As can be seen from FIG. 2a, in the write operation, whether it is a write command period or a write data period, the data signal Dx is transmitted from the master SPI device 10 and received from the SPI device 20, the clock signal CLK Delay (Delay 1) and the data signal Dx Delay (Delay 2) are the same, and the timing relationship between the clock signal CLK and the data signal Dx is consistent between the master SPI device 10 and the slave SPI device 20, such as the rising edge of the clock signal CLK in FIG. 2a is located exactly in the middle of each segment of the data signal Dx, which is convenient for the receiving end to receive data and also convenient for improving the SPI communication rate.

Table 2 shows a signal driving description of a read operation in the related art.

TABLE 2

As can be seen from table 2:

During the read command period, the master SPI device 10 drives the data signal line Dx to send a read command, and the data signal line Dx is sampled from the SPI device 20 to receive the read command.

Read switch period (Turnaround Phase) is where neither master SPI device 10 nor slave SPI device 20 drives data signal line Dx, switch period data signal line Dx is driven by master SPI device 10 to driven by slave SPI device 20, and data signal line Dx is not driven simultaneously by master SPI device 10/slave SPI device 20 during the switch period.

Read data period-read data is sent from SPI device 20 driving data signal line Dx, and master SPI device 10 samples data signal line Dx to receive read data.

Referring to FIG. 2b, FIG. 2b shows a timing diagram of a read operation of the master SPI device 10 in the related art.

As can be seen in fig. 2b, the read operation, read command period, is facilitated by receiving a read command from SPI device 20. In the read data period, master SPI device 10 transmits clock signal CLK, slave SPI device 20 receives master clock signal CLK (Delay 1), and then transmits read data according to the clock signal CLK to drive onto data signal line Dx, and master SPI device 10 receives read data returned from slave SPI device 20 (Delay 2). Because of these delays, the clock signal CLK and the data signal Dx are well timed (CLK rising edge is in the middle of each segment Dx) at the slave SPI device 20, and the clock signal CLK and the data signal Dx are greatly varied relative to the slave SPI device 20 at the master SPI device 10, so that debugging is required to find the stable middle point of the read data signal for sampling and receiving, and the received read data is ensured to be correct.

In summary, in the related art, the master SPI device 10 drives the clock signal CLK, the master SPI device 10/slave SPI device 20 switches the SPI communication method of the driving data signal Dx according to the write/read data direction, the timing of the write operation is good, and the read operation has the problems of large read data delay and delay variation:

The delay from the clock signal CLK of the master SPI device 10 to the receipt of the read data Dx by the master SPI device 10 is relatively large;

The master SPI device 10 clock signal CLK to master SPI device 10 receiving read data Dx Delay (Delay 3), which is the sum of the Delay of master SPI device 10 clock signal CLK transmitted to slave SPI device 20 (Delay 1) and the Delay of slave SPI device 20 data signal Dx transmitted to master SPI device 10 (Delay 2) (Delay 3 = Delay1+ Delay 2);

The delay from the clock signal CLK of the master SPI device 10 to the receipt of the read data Dx of the master SPI device 10 is easily changed, for example, the delay may be significantly changed according to the working conditions such as the working temperature, and the delay may be changed due to the different wiring inside the chip and the board level wiring, and the reason for causing the delay change is various and not exhaustive herein.

Under the conditions of large delay and delay change of the above read data, in order to accurately receive the read data, the debug needs to be carried out for each chip system, the higher SPI rate can be supported to the greatest extent, and the device can adapt to various change limits (such as high temperature and low temperature) and is complicated in debugging. And various change delay limits such as high temperature and low temperature are required to be supported, and only one of the relatively low rates can be selected to adapt to the change limit under the aim of pursuing the highest SPI rate (fast data transmission) as possible, so that the received data is ensured to be correct.

Therefore, the problems of complicated debugging and limited speed caused by large read data delay and delay change are needed to be solved, so that the efficiency and accuracy of SPI communication are improved.

In view of this, in the SPI communication system according to the embodiment of the present disclosure, the slave SPI device 20 receives the command clock signal and the command data signal sent by the master SPI device 10 in the command period to receive the read command, sends the read clock signal and the read data signal to the master SPI device 10 in the read data period, and the master SPI device receives the read data signal sent by the slave SPI device 20 according to the read clock signal sent by the slave SPI device 20 in the read data period, and since the read clock signal and the read data signal are driven by the slave SPI device 20, both the read clock signal and the read data signal can maintain a good fixed timing relationship at the slave/master SPI device, the master SPI device 10 can easily and accurately sample the read data signal sent by the slave SPI device 20 by using the read clock signal sent by the slave SPI device 20, so as to facilitate improving the SPI communication rate.

In the SPI communication system of the embodiment of the present disclosure, when the clock signal is driven on the same side as the data signal, that is, when the data transmitting terminal (master SPI apparatus 10/slave SPI apparatus 20) drives the data signal, it is also responsible for driving the clock signal, instead of always driving the clock signal by the master SPI apparatus 10. In the embodiment of the disclosure, the clock signal and the data signal are driven by the data transmitting end, and the delay of the data transmitted to the data receiving end is the same (the delay change caused by working conditions such as consistent wiring, temperature and the like is the same). The timing relationship between the clock signal and the data signal is determined at the transmitting end, and is also determined at the receiving end. The data receiving terminal is convenient to receive data, the receiving logic is simple, and each product does not need to be debugged excessively and fussy.

The embodiments of the present disclosure do not limit specific implementation manners of the master SPI device 10 and the slave SPI device 20, and by way of example, the master SPI device 10 and the slave SPI device 20 may be chips, and through the SPI communication scheme of the embodiments of the present disclosure, SPI communication between the chips is implemented, so that communication efficiency between the chips can be effectively improved.

Referring to FIG. 3, FIG. 3 illustrates a timing diagram of a read operation of the master SPI device 10, in accordance with an embodiment of the present disclosure.

Referring to table 3 together, table 3 shows a signal driving description of a read operation of an embodiment of the present disclosure.

TABLE 3 Table 3

Illustratively, as shown in Table 3, during each period of the read operation, master SPI device 10 drives chip select signal CS to transmit a chip select, and receives chip select signal CS from SPI device 20.

Illustratively, as shown in Table 3, the read command period is when the master SPI device 10 drives the clock signal CLK to transmit the clock signal CLK to receive the clock signal CLK from the SPI device 20, the master SPI device 10 drives the data signal Dx to transmit the read command, the data signal Dx is sampled from the SPI device 20 to receive the read command, and the timing relationship between the clock signal CLK and the data signal Dx received from the SPI device 20 is determined.

Illustratively, as shown in Table 3, read transition period (Turnaround Phase) is where neither master SPI device 10 nor slave SPI device 20 drives CLK/Dx, the transition period CLK/Dx is transitioned from being driven by master SPI device 10 to being driven by slave SPI device 20, and neither master SPI device 10 nor slave SPI device 20 simultaneously drives CLK/Dx during the transition.

Illustratively, as shown in Table 3, the data reading period includes the steps of driving the clock signal CLK from the SPI device 20, receiving the clock signal CLK by the master SPI device 10, driving the data signal Dx from the SPI device 20, sampling the data signal Dx by the master SPI device 10 and receiving the read data, wherein the timing relationship between the clock signal CLK received by the master SPI device 10 and the data signal Dx is identical to the timing relationship between the clock signal CLK and the data signal Dx of the slave SPI device 20 at the transmitting end, the rising edge of the clock signal CLK is exactly in the middle of the data signal Dx, and the master SPI device 10 at the receiving end (no special debugging is needed) is easy to conveniently and accurately sample and receive the read data.

Illustratively, as can be seen in FIG. 3, the read operation, read command period, and CLK/Dx timing relationship for receiving a read command from SPI device 20 determines that the CLK rising edge is well in the middle of each segment of data for ease of reception. And in the time period of the read data, the CLK/Dx time sequence relation of the read data received by the main SPI is determined, and the rising edge of the CLK is just in the middle of each piece of data, so that the data is convenient to receive.

According to the determined time sequence, the receiving and transmitting logic is designed, and the normal work can be realized without complicated debugging. The working conditions such as high temperature and low temperature are the same, delay changes of the clock signal CLK/data signal Dx are the same, and change limits are the same, so that higher SPI communication rate can be supported.

While the description above describes the data transmitting end as the slave SPI device 20 in the SPI communication system of the embodiment of the disclosure, the master SPI device 10 may also be used as the data transmitting end, for example, in one possible implementation manner, the master SPI device 10 is configured to transmit the command clock signal and the write command data signal to the slave SPI device 20 in the command period, transmit the write clock signal and the write data signal to the slave SPI device 20 in the write data period, and in one possible implementation manner, the slave SPI device 20 is configured to receive the command clock signal and the command data signal transmitted by the master SPI device 10 in the command period to receive the write command, and receive the write clock signal and the write data signal transmitted by the master SPI device 10 in the write data period to receive the write data.

It should be noted that, the manner in which the master SPI apparatus 10 is used as the data transmitting end to transmit data is referred to the foregoing description, and will not be described herein.

In the SPI communication system according to the disclosed embodiments, the slave SPI device 20 sends the read clock signal and the read data signal when receiving the read command of the master SPI device 10, so that the master SPI device 10 receives the read data signal according to the read clock signal, and since the read clock signal is driven by the slave SPI device 20, the read clock signal and the data signal can both maintain a good fixed timing relationship at the slave/master SPI device end, the master SPI device 10 can easily and accurately sample the read data signal sent from the SPI device 20 by using the clock signal sent from the SPI device 20, and thus the SPI communication rate can be improved. By adopting the same side driving of the clock signal and the data signal, namely when the master SPI device 10/the slave SPI device 20 drives the data signal, the clock signal is also driven at the same time, instead of always being driven by the master SPI device 10, compared with the mode of driving the clock signal by the master SPI, the SPI working speed can be improved, the accuracy of data transmission is improved, and the debugging difficulty is reduced.

As an example, the same project is tested, the SPI communication designed by the original scheme (both the write operation and the read operation are performed by the master SPI driving clock signal), the SPI rate for debugging stable operation is 15MHz, and the debugging is complicated. The scheme provided by the embodiment of the disclosure (driven by the same side of the clock signal and the data signal) is adopted, and under the condition that other adjustments are the same, the SPI stable working rate of the scheme provided by the embodiment of the disclosure is 30MHz, and the debugging process is simpler.

Referring to fig. 4, fig. 4 shows a schematic diagram of single rate (SDR-SINGLE DATA RATE) SPI communication in the related art, for example, SPI mode 0.

As shown in fig. 4, the data transmitting terminal transmits data to Dx on the falling edge of the clock signal (CLK), keeps the data unchanged on the rising edge of the clock signal (CLK), and transmits the next data on the falling edge of the next clock signal (CLK). The data Dx remains stable for an entire Clock (CLK) period between two falling edges of the clock signal (CLK).

As shown in fig. 4, the data receiving end samples and receives Dx data at the rising edge of the clock signal (CLK), and this sampling point is just the middle point of the data signal Dx that remains stable for the whole Clock (CLK) period, satisfying the best setup time and hold time.

As can be seen, the shortfalls of SDR SPI communication exist:

the rate of the clock CLK is 2 times the rate of the data Dx, and the clock CLK needs to be changed 2 times (1 rise and 1 fall) within a period in which the data Dx is changed once (0 to 1 or1 to 0).

If the clock CLK and PAD of the data Dx have the same driving capability, the highest communication rate is limited by the communication (driving) capability of the clock CLK.

If the PAD driving capability of the clock CLK is increased in order to adapt the rate of the clock CLK to the data Dx, the PAD area of the clock CLK needs to be increased. Also, the clock CLK requires a rising/falling time, and a high-low level is maintained for a period of time. The PAD area and driving capability of the clock CLK are always increased, and the communication rate of the clock CLK cannot be linearly increased.

Therefore, in order to solve the problem that the rate of the clock CLK is 2 times that of the data Dx, and the communication rate is limited by the CLK communication capability, the accuracy of the SPI data transmission is further improved, and the SPI communication technology of DDR (Dual Data Rate) of the embodiments of the present disclosure samples data on rising/falling edges of the clock signal CLK.

Illustratively, the aforementioned "intermediate position" may be a center point of the length of the data signal (e.g., the midpoint of the Dx data in fig. 2 a).

For example, two (or two beats) of data signals corresponding to the same clock signal may be regarded as a pair of data signals, the middle position of the first data signal corresponds to the rising edge of the clock signal, the middle position of the second data signal corresponds to the falling edge of the clock signal, as described above, the first command data signal and the second command data signal may be regarded as a pair of command data signals, the first command data signal is the first command data signal of the pair of command data signals, the second command data signal is the next adjacent command data signal of the first command data signal, and the rising edge of the command clock signal corresponds to the middle position of the first command data signal, and the falling edge of the command clock signal corresponds to the middle position of the second command data signal, and the cycle is repeated.

In one possible implementation, the SPI transmitting ends in the master SPI device 10 and the slave SPI device 20 are configured to:

Transmitting a first data signal at a start time of a clock cycle;

after T/2, sending rising edge of clock signal;

After T/2, transmitting a second data signal;

after T/2, transmitting the falling edge of the clock signal;

After T/2, the next clock cycle begins.

Referring to fig. 5, fig. 5 shows a schematic diagram of SPI communication according to an embodiment of the present disclosure.

Illustratively, as shown in fig. 5, the SPI transmitting end (including the master SPI device 10, the slave SPI device 20):

Data is firstly sent to Dx, after T/2 is passed, rising edge of a clock CLK is sent, after T/2 is passed, next data is sent to Dx, after T/2 is passed, falling edge of the clock CLK is sent, and the clock CLK and the data Dx are kept at T/2. Thus, one cycle of 2 data is completed. And (5) repeating the cycle, and ending after all data are transmitted.

In this period of 2 data, the clock CLK changes at the same frequency as the data Dx, and changes after maintaining one T. The clock CLK is staggered from the data Dx by T/2 to ensure that the SPI receiver has good setup time (T/2) and hold time (T/2) when the data Dx is sampled on the rising/falling edge of the clock CLK.

The SPI communication technology of DDR (Dual Data Rate) for sampling data on rising/falling edges of a clock signal CLK in the embodiment of the disclosure has the following advantages:

the clock CLK is reduced to half the rate of change compared to SDR communications.

The clock CLK is the same as the data Dx in frequency, and the communication capability is no longer limited by the clock CLK.

The clock CLK and the data Dx can be multiplexed into the same PAD design, the PAD of the clock CLK does not need to be designed independently, and the PAD area and the driving capability of the clock CLK do not need to be increased.

The same PAD is used for the clock CLK and the data Dx, and compared with the SDR, the DDR mode communication rate can be doubled (the practical application is also limited by other conditions).

As an example, the same project was tested, the same PAD design was multiplexed with CLK and Dx using the SPI communication of the original design SDR, and the CLK rate of the SPI for debugging steady operation was 15MHz (corresponding to 15Mbps for single line data communication rate, 30Mbps for two line data communication rate, and 60Mbps for four line data communication rate).

According to the DDR technical scheme of the embodiment of the disclosure, under the condition that the PAD design of CLK and Dx is not changed, the CLK rate of the SPI which is debugged and stably works is 15MHz (30 Mbps corresponding to single line data communication rate, 60Mbps corresponding to double line data communication rate and 120Mbps corresponding to four line data communication rate). It can be seen that the data communication rate is doubled.

Referring to fig. 6, fig. 6 shows a flowchart of an SPI communication method according to an embodiment of the present disclosure.

The method is applied to an SPI communication system comprising a master SPI device 10 and a slave SPI device 20.

As shown in fig. 6, the method includes:

step S11, receiving the command clock signal and the command data signal sent by the master SPI device 10 by the slave SPI device 20 in a command period to receive a read command, and sending the read clock signal and the read data signal to the master SPI device 10 in a read data period;

Step S12, transmitting a command clock signal and a read command data signal to the slave SPI device 20 by using the master SPI device 10 in a command period, and receiving the read data signal transmitted from the slave SPI device 20 according to the read clock signal transmitted from the slave SPI device 20 in a read data period.

In the case that the slave SPI device 20 receives the read command of the master SPI device 10 in the command period, the read clock signal and the read data signal are sent in the read data period, so that the master SPI device 10 receives the read data signal according to the read clock signal, and since the read clock signal is driven by the slave SPI device 20, the master SPI device 10 can improve the accuracy of the read data when receiving the read data signal, and the read clock signal and the data signal can both maintain a good fixed timing relationship at the slave/master SPI device side, the master SPI device 10 can easily and accurately sample the read data signal sent from the slave SPI device 20 by using the clock signal sent from the slave SPI device 20, and the SPI communication rate can be improved.

In one possible implementation, the method further includes transmitting a command clock signal and a write command data signal to slave SPI device 20 during a command period using master SPI device 10;

In one possible implementation, the method further includes receiving a command clock signal and a command data signal sent by the master SPI device 10 to receive a write command using the slave SPI device 20 during a command period, and receiving a write clock signal and a write data signal sent by the master SPI device 10 to receive write data during a write data period.

In one possible embodiment, the method further comprises:

the following steps are performed by using the master SPI apparatus 10 and the SPI transmitting terminal in the slave SPI apparatus 20:

Transmitting a first data signal at a start time of a clock cycle;

after T/2, sending rising edge of clock signal;

After T/2, transmitting a second data signal;

after T/2, transmitting the falling edge of the clock signal;

After T/2, the next clock cycle begins.

It will be appreciated that the above-mentioned method embodiments of the present disclosure may be combined with each other to form a combined embodiment without departing from the principle logic, and are limited to the description of the present disclosure. It will be appreciated by those skilled in the art that in the above-described methods of the embodiments, the particular order of execution of the steps should be determined by their function and possible inherent logic.

In some embodiments, the SPI communication method provided in the embodiments of the present disclosure corresponds to the aforementioned SPI communication system, and specific implementation thereof may refer to the description of the foregoing method embodiments, which is not repeated herein for brevity.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An SPI communication system, characterized in that the SPI communication system includes a master SPI device and a slave SPI device, wherein:

The slave SPI device is used to: receive the instruction clock signal and instruction data signal sent by the master SPI device in the instruction period to receive the read instruction; send the read clock signal and the read data signal to the master SPI device in the read data period;

The master SPI device is used to: send an instruction clock signal and a read instruction data signal to the slave SPI device in an instruction period; and receive a read data signal sent by the slave SPI device according to the read clock signal sent by the slave SPI device in a read data period.

2. The SPI communication system according to claim 1, characterized in that:

The master SPI device is used to: send a command clock signal and a write command data signal to the slave SPI device during the command period; send a write clock signal and a write data signal to the slave SPI device during the write data period;

The slave SPI device is used to: receive the instruction clock signal and instruction data signal sent by the master SPI device in the instruction period to receive the write instruction; receive the write clock signal and write data signal sent by the master SPI device in the write data period to receive the write data.

3. The SPI communication system according to claim 2, characterized in that:

The rising edge of the instruction clock signal corresponds to the middle position of the first instruction data signal, and the falling edge of the instruction clock signal corresponds to the middle position of the second instruction data signal, and the cycle repeats, wherein the second instruction data signal is the next instruction data signal adjacent to the first instruction data signal;

The rising edge of the write clock signal corresponds to the middle position of the first write data signal, and the falling edge of the write clock signal corresponds to the middle position of the second write data signal, and the cycle repeats, wherein the second write data signal is the next write data signal adjacent to the first write data signal;

The rising edge of the read clock signal corresponds to the middle position of the first read data signal, and the falling edge of the read clock signal corresponds to the middle position of the second read data signal, and the cycle repeats, wherein the second read data signal is the next read data signal adjacent to the first read data signal.

4. The SPI communication system according to claim 1, wherein the SPI transmitting end in the master SPI device and the slave SPI device is used for:

Set the clock period of the clock signal to 2T, send the first data signal and the second data signal continuously in each clock period, T is a positive value of time, wherein in each clock period:

At the beginning of the clock cycle, the first data signal is sent;

After T/2, the rising edge of the clock signal is sent;

After T/2, the second data signal is sent;

After T/2, the falling edge of the clock signal is sent;

After T/2, the next clock cycle begins.

5. The SPI communication system according to claim 1, wherein the master SPI device and the slave SPI device are both chips.

6. A SPI communication method, characterized in that the method is applied to a SPI communication system including a master SPI device and a slave SPI device, wherein the method comprises:

The slave SPI device receives the instruction clock signal and instruction data signal sent by the master SPI device in the instruction period to receive the read instruction; and sends the read clock signal and the read data signal to the master SPI device in the read data period;

The master SPI device is used to send an instruction clock signal and a read instruction data signal to the slave SPI device during an instruction period; and a read data signal sent by the slave SPI device is received according to the read clock signal sent by the slave SPI device during a read data period.

7. The SPI communication method according to claim 6, characterized in that the method further comprises: using the master SPI device to send a command clock signal and a write command data signal to the slave SPI device during the command period; sending a write clock signal and a write data signal to the slave SPI device during the write data period;

The slave SPI device is used to receive the instruction clock signal and instruction data signal sent by the master SPI device in the instruction period to receive the write instruction; and to receive the write clock signal and write data signal sent by the master SPI device in the write data period to receive the write data.

8. The SPI communication method according to claim 7, characterized in that:

9. The SPI communication method according to claim 6, characterized in that the method further comprises:

The following steps are performed using the SPI transmitter in the master SPI device and the slave SPI device:

At the beginning of the clock cycle, the first data signal is sent;

After T/2, the rising edge of the clock signal is sent;

After T/2, the second data signal is sent;

After T/2, the falling edge of the clock signal is sent;

After T/2, the next clock cycle begins.

10. The SPI communication method according to claim 6, wherein the master SPI device and the slave SPI device are both chips.