CN119376642A - Storage device and electronic system - Google Patents

Abstract

The invention discloses a storage device and an electronic system. The storage device comprises a storage controller and N memories, wherein N is a natural number, the storage controller is connected with the N memories, the memories comprise reserved spaces and storage spaces for data storage, the storage controller detects whether fault blocks exist in the storage spaces or not in the operation process of the memories, if yes, whether the reserved spaces have enough unallocated spaces or not is judged, and if yes, the fault blocks are replaced with target spaces in the reserved spaces to serve as data storage spaces. The invention provides a storage scheme which has the advantages of both cost and reliability.

Description

Storage device and electronic system

Technical Field

The present invention relates to the field of electronic technologies, and in particular, to a storage device and an electronic system.

Background

With the development of electronic technology, various electronic products have increasingly demanded memory reliability.

Currently, in the use stage of various electronic products, when a memory device is detected to be faulty or at the end of life, a new storage medium is often replaced and started, and data is moved to the new storage medium, so that the electronic products can continue to operate. This results in a large cost and resource waste.

Disclosure of Invention

The present invention has been made in view of the above problems, and has as its object to provide a storage device and an electronic system which overcome or at least partially solve the above problems.

In a first aspect, there is provided a storage device comprising:

A storage controller and N memories, wherein N is a natural number;

the storage controller is connected with the N memories, and the memories comprise reserved spaces and storage spaces for data storage;

And in the running process of the memory, the memory controller detects whether a fault block exists in the memory space, if so, judges whether the reserved space has enough unallocated space, and if so, replaces the fault block with the target space in the reserved space to serve as a data memory space.

Optionally, if the storage controller detects that a fault block exists in the storage space, but the reserved space does not have enough unallocated space, isolating the fault block, and feeding back storage capacity reduction information to a master device connected to the storage device, where the storage capacity reduction information includes available storage capacity of the memory after removing capacity of the fault block.

Optionally, the reserved space occupies 1/16-1/8 of the total storage capacity of the memory.

Optionally, the storage controller acquires the wear degree of each section in the memory, and allocates the storage address of the data in the memory according to the inverse relation between the access frequency of the data and the wear degree.

Optionally, the storage device further comprises an open industry standard interconnection interface connected with the storage controller for communication between the storage controller and the main control unit.

Optionally, the storage device further comprises a cache module, the storage controller further comprises a cache controller, and the cache controller is connected with the cache module, wherein the cache controller synchronizes the data stored in the cache module with the cache data stored in the main control unit based on the open industry standard interconnection interface.

Optionally, the N memories comprise a dynamic random access memory and a nonvolatile memory, and the access of the main control unit to the storage device is sequentially performed according to the sequence of the cache module, the dynamic random access memory and the nonvolatile memory based on the open industry standard interconnection interface.

Optionally, the storage controller comprises an equalization module, wherein the equalization module is connected with the nonvolatile memory to set the storage address of the nonvolatile memory in an equalization mode according to the use condition of the storage area in the nonvolatile memory.

Optionally, in the process of writing the write data into the storage device, writing the write data into the cache module, sequentially storing the write data into the dynamic random access memory and the nonvolatile memory according to a preset algorithm, in the process of reading the read data from the storage device, firstly querying the cache data in the cache module, if hit, acquiring the read data from the cache module, if miss, querying the data in the dynamic random access memory, if hit, acquiring the read data from the dynamic random access memory, if not hit, and then querying the data in the nonvolatile memory.

In a second aspect, an electronic system is provided, comprising:

a main control unit and the storage device of any one of the first aspect;

The storage device communicates with the master control unit via an open industry standard interconnect interface.

The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:

The storage device and the electronic system provided by the embodiment of the invention are characterized in that the storage controller is connected with N memories, and the memories comprise reserved spaces and storage spaces for data storage. In the running process of the memory, whether the memory space has a fault block is checked through the memory controller, if the memory space has the fault block and the reserved space has enough space, a target space in the reserved space is started to replace the fault block as a data memory space so as to ensure that the data memory space capacity of the memory is not influenced by the fault block, thereby avoiding the memory replacement caused by the abnormal part of memory addresses, maintaining the reliable use of the memory device and effectively reducing the long-term use cost of the memory device.

The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

Fig. 3 is a schematic structural diagram of an electronic system according to an embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

Referring to fig. 1, an embodiment of the present application provides a memory device, which includes a memory controller 1 and N memories 2, N taking a natural number. The memory controller 1 is connected to N memories 2, the memories 2 including a reserved space and a memory space for data storage. In the process of operating the memory 2, the memory controller 1 detects whether a fault block exists in a memory space, if so, determines whether the reserved space has enough unallocated space, and if so, replaces the fault block with a target space in the reserved space as a data memory space.

The memory 2 may be a volatile memory or a nonvolatile memory. The N memories 2 may be the same type of memory or different types of memory, and are not limited herein.

The structure and operation of the memory device will be described in detail.

In an alternative embodiment, the reserved space in the memory 2 may be set to be 1/16-1/8 of the total storage capacity of the memory 2. Therefore, enough substitution space can be provided for the fault blocks in the using process, and excessive occupation of the data storage space can be avoided.

In the implementation process, the fault block in the storage space can be a damaged address segment space with sudden faults in the operation process, or can be a failed address segment space reaching the end of life. The method of detecting whether there is a fault block in the storage space by the storage controller 1 may be writing and reading each address segment, detecting whether the read data matches the written data, and if there is no match exceeding the preset number of times, determining that the address segment space is a fault block. After determining that the fault block exists, a target space with the same capacity as the fault block is allocated from the reserved space, and the address of the fault block is mapped to the target space, so that the fault block is replaced by the target space to provide a data storage space, the memory 2 does not need to be replaced, and the maintenance cost is saved.

In an alternative embodiment, if the storage controller 1 detects that there is a faulty block in the storage space of the memory 2, but the reserved space has insufficient unallocated space, the faulty block is isolated, and the storage capacity reduction information including the available storage capacity of the memory 2 after removing the capacity of the faulty block is fed back to a host device (e.g., a CPU or a motherboard chip) connected to the storage device.

Specifically, each time a defective block is detected by the storage controller 1, a target space of a corresponding capacity is allocated from the reserved space to replace the defective block for data storage, which results in less and less unallocated space remaining in the reserved space (i.e., space in the reserved space that has not been allocated as the target space to replace the defective block). Under the condition that a fault block is detected, but enough space in the reserved space can be used for replacing the fault block, the fault block can be isolated and not used any more, the residual space capacity of the memory 2 which can be used for storing data after the fault block is isolated is determined, and then the storage capacity reduction information carrying the residual capacity is fed back to the main control equipment, so that the main control equipment can timely adjust the system address space corresponding to the memory 2, and the normal use of the memory equipment can be ensured.

For example, assume that the storage space capacity of the memory 2 is 8G, the reserved space is 1G, and the space capacity of the corresponding record in the master control device is 8G. When the storage controller 1 detects that there is a 1G defective block, a 1G target space is allocated from the reserved space to map the address of the defective block, thereby replacing the defective block. When the storage controller detects a 1G fault block subsequently, the reserved space has insufficient unallocated space, the fault block is isolated, and the residual capacity fed back to the main control equipment memory 2 is 7G, so that the system address space corresponding to the main control equipment regulator is 7G, and the subsequent normal operation is ensured.

In an alternative embodiment, the storage controller 1 may be further configured to obtain the wear degree of each section in the memory 2, and allocate the storage address of the memory 2 according to the inverse relation between the access frequency of the data and the wear degree.

Specifically, it is possible to determine which data are data which are more frequently accessed by the master device based on the history of access experience and history of access data, and store the data which are more frequently accessed in the address space which is less worn in the memory 2. The address space may be allocated according to the predicted access frequency in inverse relation to the wear level during data writing, or the access frequency of the data already stored in the memory 2 may be monitored, and the memory address may be adjusted periodically or triggered according to the access frequency to meet the requirement that the access frequency is inversely related to the wear level. The wear degree of each address space in the memory 2 may be obtained by counting the cumulative access times of each address space, and if the access times are large, the wear degree is high.

In an alternative embodiment, as shown in FIG. 2, the storage controller may also include an open industry standard interconnect interface 3 (Compute Express Link, CXL) interface module that can be used to connect processors, accelerators, memory buffers, intelligent network interfaces, storage devices, and the like. The open industry standard interconnection interface 3 is connected with the storage controller 1, and is used for communication between the storage controller 1 and the main control unit 201, and can transmit an access request issued by the main control unit 201 to the storage controller 1.

In an alternative embodiment, as shown in fig. 2, the storage device may further include a cache module 4, and the corresponding storage controller 1 further includes a cache controller 11, where the cache controller 11 is connected to the cache module 4. The cache controller 11 synchronizes the cache data stored in the cache module and the main control unit 201 based on the open industry standard interconnection interface 3.

Specifically, based on the protocol (for example, the cache protocol) of the open industry standard interconnect interface 3, the cache controller 11 manages the cache module 4, so that the data stored in the cache module 4 and the cache data in the main control unit 201 can be synchronized. When the main control unit 201 is powered down, data cached in each level in the main control unit 201 is timely and synchronously brushed down to the cache module 4 of the storage device, so as to avoid data loss.

In an alternative embodiment, as shown in FIG. 2, the N memories 2 connected to the Memory controller 1 include a dynamic random access Memory 21 (Dynamic Random Access Memory, DRAM) and a Non-Volatile Memory 22 (NVM). Based on the open industry standard interconnect interface 3, the access of the main control unit 201 to the storage device is performed sequentially in the order of the buffer module 4, the dynamic random access memory 21, and the nonvolatile memory 22. Since the dynamic random access memory 21 has the advantages of low cost and relatively high access speed, the dynamic random access memory 21 can be used as the next-stage storage medium of the cache module 4 to effectively consider the cost and the access speed, and the dynamic random access memory 21 is used as the upper-layer cache of the nonvolatile memory 22, so that the abrasion to the nonvolatile memory 22 can be reduced, and the service life of the whole storage device can be prolonged. The nonvolatile memory 22 is low in cost and large in capacity, and can effectively achieve both data storage capacity and cost as a final storage medium. By combining the three, the cache module 4, the dynamic random access memory 21 and the nonvolatile memory 22 are sequentially accessed in order, and the access speed, the cost, the capacity and the service life can be effectively considered.

Specifically, in the process of writing the write data into the storage device, the write data is written into the buffer module 4, and then sequentially stored into the dynamic random access memory 21 and the nonvolatile memory 22 according to a preset algorithm. The preset algorithm may be that the write data is written into the dynamic random access memory 21 and the nonvolatile memory 22 sequentially and synchronously as long as the write data is written into the cache module 4, or may be that the write data is stored as cache data after being written into the cache module 4, when the data is written into the cache module 4 next time and occupies the storage address space of the write data, the data is stored in the dynamic random access memory 21 in a obsolete mode, and similarly, when the data is written into the dynamic random access memory 21 next time and occupies the storage address space of the write data, the write data is stored in the nonvolatile memory 22 in a obsolete mode. Therefore, when the cache module 4 stores the write data so as to enable the subsequent read data to hit in the cache module 4 quickly, the read speed is improved, the write data is stored in the dynamic random access memory 21 and the nonvolatile memory 22 so as to prevent the write data from being replaced and updated by the subsequently written data in the cache module 4, and the write data can be read in the dynamic random access memory 21 and the nonvolatile memory 22, thereby taking the access speed and the data reliability into consideration.

In the process of reading the read data from the storage device, firstly, the cache data in the cache module 4 is queried, if the read data is hit, the read data is obtained from the cache module, if the read data is not hit and then the data in the dynamic random access memory 21 is queried, if the read data is hit, the read data is obtained from the dynamic random access memory 21, and if the read data is still not hit, the read data is queried again in the nonvolatile memory 22. In case of read data read from the dynamic random access memory 21 and the non-volatile memory 22, the read data may be stored back in the cache module 4 for faster access next time. Therefore, the data reading speed can be effectively improved by inquiring the data in the cache module 4 with higher reading speed.

In an alternative embodiment, as shown in fig. 2, the storage controller 1 may also be provided to include a data management module 12. Based on the protocols of the open industry standard interconnect interface 3 (e.g., its. Cache,. Mem and. Io protocols), the memory controller 1 is capable of communicating with both volatile and nonvolatile memory, wherein the data management module 12 is capable of managing data storage of the memory 2, is also capable of taking charge of interactions of data between the respective memories 2 and between the memory 2 and the Cache module 4, is also capable of managing the reserved space of the memory 2 (including setting a target space replacement failure block) and managing addresses at the time of data storage (including assigning storage addresses of the data to the memory 2 in accordance with a relationship of the access frequency of the data inversely related to the degree of wear).

In an alternative embodiment, as shown in fig. 2, the memory controller 1 may also be provided to include an equalization module 13. The balancing module 13 is connected to the nonvolatile memory 22 to balance the storage addresses of the nonvolatile memory 22 according to the usage of the storage area in the nonvolatile memory 22. Specifically, the balancing module 13 stores a memory address mapping table of the nonvolatile memory 22, which characterizes a mapping relationship between a logical address and a physical address, and can correspond to the physical address of the nonvolatile memory 22 based on the logical address of the access request according to the mapping table. The balancing module 13 records the usage conditions of each physical area in the nonvolatile memory 22 to set the memory address mapping table in a balanced manner, so as to avoid the consumption of the service life of the memory block caused by excessive use of partial memory blocks, and set the physical addresses of the data memory in a balanced manner to ensure the balanced wear of the memory block.

In an alternative embodiment, as shown in fig. 2, the memory controller 1 may also be configured to include a memory interface module 14, where the memory interface module 14 is configured to connect and access N memories 2. For example, in FIG. 2 the memory interface module 14 is used to access the storage media of the DRAM 21 and the nonvolatile memory 22.

Based on the same inventive concept, an embodiment of the present application further provides an electronic system, as shown in fig. 3, including:

The main control unit 201 and the storage device 301 provided in the foregoing embodiments.

The storage device 301 includes a storage controller and N memories, N being a natural number;

The storage controller is connected with the N memories, and the memories comprise reserved spaces and storage spaces for data storage, wherein in the running process of the memories, the storage controller detects whether a fault block exists in the storage spaces, if so, judges whether the reserved spaces have enough unallocated spaces, and if so, replaces the fault block with a target space in the reserved spaces to serve as a data storage space;

The memory device 301 communicates with the master control unit 201 via an open industry standard interconnect interface.

In an alternative embodiment, based on the extensibility and the multiport optional mechanism of the open industry standard interconnect interface technology, the electronic system may be configured to include a plurality of master control units 201, and the storage device 301 is communicatively connected to the plurality of master control units 201 based on the open industry standard interconnect interface, such that the plurality of master control units share the storage device 301.

Since the storage device 301 included in the electronic system described in the embodiment of the present application is just the storage device described in the embodiment of the present application, the principle and structure of the storage device and the connection manner between the storage device and the main control unit 201 have been described in detail previously, so that the description is omitted here. All electronic systems including the memory device according to the embodiments of the present application are within the scope of the present application.

The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:

The storage device and the electronic system provided by the embodiment of the invention are characterized in that the storage controller is connected with N memories, and the memories comprise reserved spaces and storage spaces for data storage. In the running process of the memory, whether the memory space has a fault block is checked through the memory controller, if the memory space has the fault block and the reserved space has enough space, a target space in the reserved space is started to replace the fault block as a data memory space so as to ensure that the data memory space capacity of the memory is not influenced by the fault block, thereby avoiding the memory replacement caused by the abnormal part of memory addresses, maintaining the reliable use of the memory device and effectively reducing the long-term use cost of the memory device.

The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general-purpose systems may also be used with the teachings herein. The required structure for a construction of such a system is apparent from the description above. In addition, the present invention is not directed to any particular programming language. It will be appreciated that the teachings of the present invention described herein may be implemented in a variety of programming languages, and the above description of specific languages is provided for disclosure of enablement and best mode of the present invention.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects.

Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including the abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including the accompanying abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention. Any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the invention. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In an embodiment in which several means are recited, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.

Claims (10)

1. A memory device, comprising:

A storage controller and N memories, wherein N is a natural number;

the storage controller is connected with the N memories, and the memories comprise reserved spaces and storage spaces for data storage;

And in the running process of the memory, the memory controller detects whether a fault block exists in the memory space, if so, judges whether the reserved space has enough unallocated space, and if so, replaces the fault block with the target space in the reserved space to serve as a data memory space.

2. The storage device of claim 1, wherein:

and if the storage controller detects that a fault block exists in the storage space, but the reserved space does not have enough unallocated space, isolating the fault block, and feeding back storage capacity reduction information to a main control device connected with the storage device, wherein the storage capacity reduction information comprises the available storage capacity of the memory after the capacity of the fault block is removed.

3. The storage device of claim 1, wherein:

the reserved space occupies 1/16-1/8 of the total storage capacity of the memory.

4. The storage device of claim 1, wherein:

And the storage controller acquires the abrasion degree of each section in the memory, and distributes the storage address of the data in the memory according to the inverse relation between the access frequency of the data and the abrasion degree.

5. The storage device of claim 1, further comprising:

And the open industry standard interconnection interface is connected with the storage controller and used for communicating the storage controller with the main control unit.

6. The storage device of any of claims 1-4, wherein:

the storage device also comprises an open industry standard interconnection interface which is connected with the storage controller and is used for the communication between the storage controller and the main control unit;

the storage device further comprises a cache module, the storage controller further comprises a cache controller, and the cache controller is connected with the cache module;

the cache controller synchronizes data stored in the cache module with cache data stored in the main control unit based on the open industry standard interconnection interface.

7. The storage device of claim 6, wherein the N memories comprise:

Dynamic random access memory and/or nonvolatile memory;

Based on the open industry standard interconnection interface, the access of the main control unit to the storage device is sequentially performed according to the sequence of the cache module, the dynamic random access memory and the nonvolatile memory.

8. The storage device of claim 7, wherein:

The memory controller includes an equalization module;

the balancing module is connected with the nonvolatile memory to balance and set the storage address of the nonvolatile memory according to the use condition of the storage area in the nonvolatile memory.

9. The storage device of claim 7, wherein:

Writing the write data into the cache module in the process of writing the write data into the storage device, and sequentially storing the write data into the dynamic random access memory and the nonvolatile memory according to a preset algorithm;

In the process of reading the read data from the storage device, firstly, searching the cache data in the cache module, if the cache data is hit, acquiring the read data from the cache module, if the cache data is not hit, then, searching the data in the dynamic random access memory, if the cache data is hit, acquiring the read data from the dynamic random access memory, and if the cache data is not hit, then, searching the data in the nonvolatile memory.

10. An electronic system, comprising:

a main control unit and a storage device;

the storage device comprises a storage controller and N memories, wherein N is a natural number;

The storage controller is connected with the N memories, and the memories comprise reserved spaces and storage spaces for data storage, wherein in the running process of the memories, the storage controller detects whether a fault block exists in the storage spaces, if so, judges whether the reserved spaces have enough unallocated spaces, and if so, replaces the fault block with a target space in the reserved spaces to serve as a data storage space;

The storage device communicates with the master control unit via an open industry standard interconnect interface.