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CN119375559A - Test circuit and working method thereof - Google Patents

Test circuit and working method thereof Download PDF

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Publication number
CN119375559A
CN119375559A CN202310919875.0A CN202310919875A CN119375559A CN 119375559 A CN119375559 A CN 119375559A CN 202310919875 A CN202310919875 A CN 202310919875A CN 119375559 A CN119375559 A CN 119375559A
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CN
China
Prior art keywords
time node
level
control
terminal
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310919875.0A
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Chinese (zh)
Inventor
王立鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202310919875.0A priority Critical patent/CN119375559A/en
Publication of CN119375559A publication Critical patent/CN119375559A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/20—Modifications of basic electric elements for use in electric measuring instruments; Structural combinations of such elements with such instruments
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/64—Testing of capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The test circuit is used for measuring a nominal value of an element to be tested, and comprises a first input end, a first output end, a first control end and a second control end, wherein the first input end is coupled with a power supply voltage end, the second transmission gate comprises a second input end, a second output end, a third control end and a fourth control end, the second output end is connected with the first output end, the second input end is grounded, a first inverter, the input end of the first inverter is connected with the first control end, the output end of the first inverter is connected with the second control end, the input end of the second inverter is connected with the fourth control end, the output end of the second inverter is connected with the third control end, and the first end of the element to be tested is connected with the first output end. The test circuit can accurately measure the nominal value of the element to be tested.

Description

Test circuit and working method thereof
Technical Field
The present invention relates to the field of testing technologies, and in particular, to a testing circuit and a working method of the testing circuit.
Background
In the test of an integrated circuit, capacitance is one of the most basic test items, and for a MOS tube, accurate measurement of capacitance value is the basis for accurately establishing a model, however, as the size of the MOS tube is reduced, on one hand, the magnitude of capacitance value of each part is continuously reduced, on the other hand, due to the fact that parasitic capacitance is generated more and more, the relative error of capacitance measurement value is larger and more, a great amount of errors are introduced in the process of establishing the MOS tube model, so that the model is inaccurate, and finally the performance and reliability of circuit design are affected.
In the prior art, a test structure based on a charge injection effect is adopted, and the value of the capacitor to be measured is calculated by measuring the charge quantity required by the capacitor to be measured according to the relation between the charge quantity required by the capacitor to be measured for charging and the capacitance value to be measured, but the test structure based on the charge injection effect has larger limitation on measurement accuracy due to the influence of the charge injection effect and the mismatch between a reference end and a device at a measurement end.
In the test structure without the charge injection effect, the charge injection effect is not required to be considered, and only one measurement branch is needed, compared with the test structure based on the charge injection effect, the structure does not need to consider the influence caused by the mismatching of the reference end and the measurement end device, but because the transfer voltage capacity of the MOS tube is limited and the conduction voltage of the MOS tube is influenced by the drain end voltage, the voltage at two ends of the device to be measured is difficult to accurately control in the actual measurement process, a certain voltage difference exists at two ends of the device to be measured in the parasitic capacitance measurement process, the measurement value is inaccurate, and finally the calculated capacitance value to be measured has a larger error.
Disclosure of Invention
The invention solves the technical problem that the measured value of the element to be measured has errors.
In order to solve the technical problems, the embodiment of the invention provides a test circuit for measuring a nominal value of an element to be tested, which comprises a first transmission gate, a second transmission gate, a first inverter and a second inverter, wherein the first transmission gate comprises a first input end, a first output end, a first control end and a second control end, the first input end is coupled with a power supply voltage end, the second transmission gate comprises a second input end, a second output end, a third control end and a fourth control end, the second output end is connected with the first output end, the second input end is grounded, the first inverter is connected with the first control end, the output end of the first inverter is connected with the second control end, the second inverter is connected with the fourth control end, the output end of the second inverter is connected with the third control end, and the first end of the element to be tested is connected with the first output end.
Optionally, the test circuit further comprises a ammeter, wherein a first end of the ammeter is connected with the power supply voltage end, and a second end of the ammeter is connected with the first input end.
Optionally, the first transmission gate includes a first PMOS and a first NMOS, where a gate of the first PMOS is a first control end, a gate of the first NMOS is a second control end, a source of the first PMOS is coupled to a drain of the first NMOS and is used as a first input end, and a drain of the first PMOS is coupled to a source of the first NMOS and is used as a first output end.
Optionally, the second transmission gate comprises a second PMOS and a second NMOS, the gate of the second PMOS is a third control end, the gate of the second NMOS is a fourth control end, the source of the second PMOS is coupled to the drain of the second NMOS and is used as a second output end, and the drain of the second PMOS is coupled to the source of the second NMOS and is used as a second input end.
Optionally, the element under test includes a capacitor under test.
Optionally, the test circuit further comprises a test module coupled to the first control terminal, the third control terminal, the first input terminal and the second terminal of the device under test, wherein the test module is configured to apply a clock signal to the first control terminal and the third control terminal, apply a control signal to the second terminal of the device under test, obtain a current result of the first input terminal, and obtain a nominal value of the device under test based on the current result.
Optionally, the clock signal includes a first clock signal and a second clock signal, the control signal includes a first control signal and a second control signal, the current result includes a first current result and a second current result, the test module is configured to apply the first clock signal to the first control terminal, apply the second clock signal to the third control terminal, apply the first control signal or the second control signal to the second terminal of the element to be tested, and obtain the first current result of the first input terminal after applying the first clock signal, the second clock signal and the first control signal, obtain the second current result of the first input terminal after applying the second control signal, and obtain the nominal value of the element to be tested according to the first current result and the second current result.
Optionally, the first clock signal, the second clock signal, the first control signal and the second control signal have the same frequency, and include a first time node, a second time node, a third time node, a fourth time node and a fifth time node in sequence in a measurement period, wherein in the measurement period, the first clock signal keeps the second level to the fourth time node after the first time node is converted from the first level to the second level and keeps the first level to the fifth time node after the fourth time node is converted from the second level to the first level, and in the measurement period, the second clock signal keeps the second level to the third time node after the second time node is converted from the first level to the second level and keeps the first level to the fifth time node after the third time node is converted from the second level to the first level.
Optionally, the first control signal maintains the second level from the first time node to the fifth time node.
Optionally, the measurement module obtains a first current result of the first input end between the second time node and the third time node.
Optionally, the second control signal is switched from the second level to the first level between the first time node and the second time node, and keeps the first level to the third time node, and is switched from the first level to the second level between the third time node and the fourth time node, and keeps the second level to the fifth time node.
Optionally, the measurement module obtains the second current result of the first input terminal between the second time node and the third time node or between the fourth time node and the fifth time node.
The technical scheme of the invention also provides a working method of the test circuit, which comprises the steps of applying a clock signal to a first control end and a third control end, applying a control signal to a second end of the element to be tested, obtaining a current result of the first input end, and obtaining a nominal value of the element to be tested based on the current result
Optionally, the clock signal comprises a first clock signal and a second clock signal, the control signal comprises a first control signal and a second control signal, the current result comprises a first current result and a second current result, the clock signal is applied to the first control end and the third control end, the control signal is applied to the second end of the element to be detected, the current result of the first input end is obtained, and the nominal value of the element to be detected is obtained based on the current result.
Optionally, the first clock signal, the second clock signal, the first control signal and the second control signal have the same frequency, and include a first time node, a second time node, a third time node, a fourth time node and a fifth time node in sequence in a measurement period, wherein in the measurement period, the first clock signal keeps the second level to the fourth time node after the first time node is converted from the first level to the second level and keeps the first level to the fifth time node after the fourth time node is converted from the second level to the first level, and in the measurement period, the second clock signal keeps the second level to the third time node after the second time node is converted from the first level to the second level and keeps the first level to the fifth time node after the third time node is converted from the second level to the first level.
Optionally, the first control signal maintains the second level from the first time node to the fifth time node.
Optionally, obtaining the first current result of the first input terminal includes obtaining the first current result of the first input terminal between the second time node and the third time node.
Optionally, the second control signal is switched from the second level to the first level between the first time node and the second time node, and keeps the first level to the third time node, and is switched from the first level to the second level between the third time node and the fourth time node, and keeps the second level to the fifth time node.
Optionally, obtaining the second current result of the first input terminal includes obtaining the second current result of the first input terminal between the second time node and the third time node or between the fourth time node and the fifth time node.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
The test circuit provided by the technical scheme of the invention is provided with the first transmission gate and the second transmission gate, when the nominal value of the element to be tested is measured, the element to be tested is charged and discharged through the first transmission gate and the second transmission gate, so that the voltage is completely transferred, and the voltage at two ends of the element to be tested can be accurately controlled.
Furthermore, the test circuit provided by the technical scheme of the invention is provided with the ammeter, and the charging currents in different states are obtained through the ammeter, so that the high-precision test of the nominal value of the element to be tested is finally realized.
Furthermore, the first transmission gate and the second transmission gate in the technical scheme of the invention are both composed of the PMOS tube and the NMOS tube, when the on-resistance in the NMOS tube is increased, the on-resistance in the PMOS tube is reduced, the on-resistance value in the transmission gate is kept balanced, and the on-resistance value is not influenced by the source terminal voltage or the drain terminal voltage.
According to the working method of the test circuit provided by the technical scheme of the invention, different levels are applied to the first transmission gate, the second transmission gate and the second end of the element to be tested in a measurement period, so that voltages at two ends of the element to be tested are the same or opposite to each other, a first current result and a second current result are obtained, and a nominal value of the element to be tested is obtained according to the first current result and the second current result.
Drawings
FIG. 1 is a schematic diagram of a test structure based on charge injection effect;
FIG. 2 is a schematic diagram of a test structure without charge injection effect;
FIG. 3 is a schematic diagram of a test circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a test circuit according to an embodiment of the present invention;
FIG. 5 is a timing diagram of signals in a test circuit according to an embodiment of the present invention;
fig. 6 is a timing diagram of a signal in a test circuit according to an embodiment of the invention.
Detailed Description
The problem that the accuracy of measurement and the single measurement object cannot be considered in the existing test structure can be known by the background technology, and the analysis reason of the existing test structure is combined:
Fig. 1 is a schematic structural diagram of a test structure based on a charge injection effect.
Referring to fig. 1, the test structure includes a first PMOS tube PM1, a second PMOS tube PM2, a first NMOS tube NM1, a second NMOS tube NM2, a first ammeter I', a second ammeter I, a first Metal interconnect line Metal1 and a second Metal interconnect line Metal2, wherein the first PMOS tube PM1 and the first NMOS tube NM1 form a first inverter, and the second PMOS tube PM2 and the second NMOS tube NM2 form a second inverter.
The operation principle of the capacitance test structure based on the charge injection effect of fig. 1 is explained below.
In fig. 1, the first inverter side is connected to the capacitance calibration structure, and the second inverter side is connected to the grounded capacitance structure to be measured, the first ammeter I' and the second ammeter I measure the currents flowing through the first inverter and the second inverter respectively, the input signals of the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1 and the second NMOS transistor NM2 are controlled by two non-overlapping clock signals V1 and V2 respectively, the frequencies of the clock signals V1 and V2 are the same, but the duty ratio in the signal periods is different, i.e. the low level duration of V1 completely includes the low level duration of V2, and the high level duration of V2 completely includes the high level duration of V1, so that only one device in the NMOS and PMOS transistors can be turned on at any moment of measuring the capacitance value.
When the NMOS tube is turned on and the PMOS tube is turned off, the charges are released to the grounding end, the PMOS tube and the NMOS tube can respectively realize charge and discharge of the capacitor structure to be tested, and the current caused by the charge change can be measured through a current meter, so that the capacitor CDUT to be tested can be calculated through the following formula:
I-I' = CDUT ·vdd·f, where f is the signal frequency of the clock signals V1 and V2 and Vdd is the supply voltage.
In the scheme, the capacitance value to be measured is measured by adding the capacitance on the left side and the right side, but the addition of the two Metal interconnection lines Metal1 and Metal2 can bring parasitic capacitance to the measurement structure, and the measurement structure based on the charge injection effect has larger limitation on measurement accuracy due to the influence of the charge injection effect and the mismatch between the reference end and the measurement end device, so that the measurement accuracy of the capacitance value to be measured is influenced.
FIG. 2 is a schematic diagram of a test structure without charge injection effect.
Referring to fig. 2, the charge injection induced error-free structure includes a PMOS transistor V p, an NMOS transistor V N, a ammeter a, a capacitor to be tested C, and a PAD control circuit, wherein the capacitor test structure without charge injection effect further includes a parasitic capacitor C P.
In the above scheme, compared with a test structure based on the charge injection effect, the structure does not need to consider the influence caused by the mismatching of the reference end and the device at the measuring end, but because the MOS tube is completely turned off when Vgs < Vth, the transfer voltage capability of the MOS tube is limited, and the conduction voltage of the MOS tube is influenced by the voltage at the drain end, therefore, in the actual measurement process, the voltage at the two ends of the device to be measured is difficult to accurately control, a certain voltage difference exists at the two ends of the device to be measured in the parasitic capacitance measurement process, the measured value is inaccurate, and the calculated capacitance value to be measured has larger error.
In order to solve the problem that the measured value of the element to be tested in the test circuit has errors, the technical scheme of the invention provides the test circuit and the working method of the test circuit, and the test structure charges and discharges the element to be tested through the first transmission gate and the second transmission gate, so that the complete transmission of voltage is realized, and the voltage at two ends of the element to be tested can be accurately controlled.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures 3 to 6 are described in detail below.
Fig. 3 is a schematic diagram of a test circuit according to an embodiment of the invention.
Referring to fig. 3, the technical scheme of the present invention provides a test circuit for measuring a nominal value of a device under test 5, which comprises a first transmission gate 1 including a first input terminal, a first output terminal, a first control terminal and a second control terminal, the first input terminal being coupled to a power supply voltage terminal VDD, a second transmission gate 2 including a second input terminal, a second output terminal, a third control terminal and a fourth control terminal, the second output terminal being connected to the first output terminal, the second input terminal being grounded, a first inverter 3, the input terminal of the first inverter 3 being connected to the first control terminal, the output terminal of the first inverter 3 being connected to the second control terminal, a second inverter 4, the input terminal of the second inverter 4 being connected to the fourth control terminal, the output terminal of the second inverter 4 being connected to the third control terminal, the device under test 5, the first terminal of the device under test 5 being connected to the first output terminal.
In this embodiment, the test circuit further includes a ammeter 7, a first end of the ammeter 7 is connected to the power supply voltage terminal VDD, and a second end of the ammeter 7 is connected to the first input terminal.
In this embodiment, the first transmission gate 1 includes a first PMOS transistor MP1 and a first NMOS transistor MN1, where a gate of the first PMOS transistor MP1 is a first control end, a gate of the first NMOS transistor MN1 is a second control end, a source of the first PMOS transistor MP1 is coupled to a drain of the first NMOS transistor MN1 and is used as a first input end, and a drain of the first PMOS transistor MP1 is coupled to a source of the first NMOS transistor MN1 and is used as a first output end.
In a specific embodiment, the input voltage at the first input terminal includes any voltage value less than the second level range.
In this embodiment, the second transmission gate 2 includes a second PMOS transistor MP2 and a second NMOS transistor MN2, where the gate of the second PMOS transistor MP2 is a third control end, the gate of the second NMOS transistor MN2 is a fourth control end, the source of the second PMOS transistor MP2 is coupled to the drain of the second NMOS transistor MN2 and is used as a second output end, and the drain of the second PMOS transistor MP2 is coupled to the source of the second NMOS transistor MN2 and is used as a second input end.
Fig. 4 is a schematic diagram of a test circuit according to an embodiment of the invention.
Referring to fig. 4, the device under test 5 includes a capacitor under test C DUT.
In other embodiments, the device under test 5 further includes a resistor and an inductor, and the technical scheme of the present invention is not limited thereto, and other types of devices under test 5 are all within the scope of the present invention.
With continued reference to fig. 3, the test circuit further includes a test module coupled to the first control terminal, the third control terminal, the first input terminal, and the second terminal of the device under test, the test module being configured to apply a clock signal to the first control terminal and the third control terminal, apply a control signal to the second terminal of the device under test, obtain a current result of the first input terminal, and obtain a nominal value of the device under test 5 based on the current result.
In this embodiment, the clock signal includes a first clock signal Vp and a second clock signal Vn, the control signal includes a first control signal Vapp1 and a second control signal Vapp2, the current result includes a first current result I 1 and a second current result I 2, the test module is configured to apply the first clock signal Vp to the first control terminal, apply the second clock signal Vn to the third control terminal, apply the first control signal Vapp1 or the second control signal Vapp2 to the second terminal of the device under test 5, and obtain a first current result I 1 of the first input terminal after applying the first clock signal Vp, the second clock signal Vn and the first control signal Vapp1, obtain a second current result I 2 of the first input terminal after applying the second control signal Vapp2, and obtain a nominal value of the device under test 5 according to the first current result I 1 and the second current result I 2.
In this embodiment, a parasitic element 6 is also present in the test circuit, a first end of the parasitic element 6 is connected to the first output end and the second output end, a second end of the parasitic element 6 is connected to the second input end, and a type of the parasitic element 6 is consistent with a type of the element 5 to be tested, for example, when the element 5 to be tested is the capacitor C DUT to be tested, the first parasitic element 6 is the parasitic capacitor C PAR.
Fig. 5 is a timing diagram of signals in a test circuit according to an embodiment of the invention.
Fig. 6 is a timing diagram of a signal in a test circuit according to an embodiment of the invention.
Referring to fig. 5 or fig. 6, in one period, the frequencies of the first clock signal Vp, the second clock signal Vn, the first control signal Vapp1 and the second control signal Vapp2 are the same, and one measurement period sequentially includes a first time node Q1, a second time node Q2, a third time node Q3, a fourth time node Q4 and a fifth time node Q5.
In a specific embodiment, the first clock signal Vp and the second clock signal Vn are non-overlapping clock signals.
In this embodiment, the time sequence of the first clock signal Vp and the second clock signal Vn is specifically that in one measurement period, the first clock signal Vp keeps the second level to the fourth time node Q4 after the first time node Q1 is shifted from the first level to the second level, and keeps the first level to the fifth time node Q5 after the fourth time node Q4 is shifted from the second level, and in one measurement period, the second clock signal Vn keeps the second level to the third time node Q3 after the second time node Q2 is shifted from the first level to the second level, and keeps the first level to the fifth time node Q5 after the third time node Q3 is shifted from the second level to the first level.
In this embodiment, please continue to refer to fig. 5, the timing process of the control signal specifically includes that the first control signal Vapp1 maintains the second level from the first time node Q1 to the fifth time node Q5. In this embodiment, a first current result I 1 at the first input terminal is obtained between the second time node Q2 and the third time node Q3.
In this embodiment, please continue to refer to fig. 6, the timing sequence of the control signal specifically further includes the second control signal Vapp2 transitioning from the second level to the first level between the first time node Q1 and the second time node Q2 and maintaining the first level to the third time node Q3, and transitioning from the first level to the second level between the third time node Q3 and the fourth time node Q4 and maintaining the second level to the fifth time node Q5.
In this embodiment, the second current result I 2 of the first input terminal is obtained between the second time node Q2 and the third time node Q3 or between the fourth time node Q4 and the fifth time node Q5.
The operation of the test circuit of this embodiment will be specifically described with reference to fig. 4, 5 and 6, taking the voltage value of the first level as 0V and the voltage value of the second level as 1.05V as an example.
Referring to fig. 5, between the second time node Q2 and the third time node Q3, a second level (i.e., 1.05V) is applied to the first control terminal and the input terminal of the first inverter 3, such that the first PMOS transistor MP1 and the first NMOS transistor MN1 are both in an off state, a second level (i.e., 1.05V) is applied to the third control terminal and the input terminal of the second inverter 4, such that the second PMOS transistor MP2 and the second NMOS transistor MN2 are both in an on state, a second level (i.e., 1.05V) is applied to the second terminal of the capacitor under test C DUT, at this time, the second output terminal pulls down the first terminal of the parasitic capacitor C PAR to the first level (i.e., 0V), the second input terminal pulls up the second terminal of the parasitic capacitor C PAR to the second level (i.e., 1.05V), such that the voltages at the two ends of the parasitic capacitor C PAR are opposite, the second output terminal of the capacitor under test C DUT is pulled down to the first level (i.e., 0V), such that the current of the capacitor under test C DUT is opposite to the charging result of the first capacitor under test C charge of the first capacitor under test C DUT, and the current of the first capacitor under test C is measured, and the current of the parasitic capacitor under test C is measured at the charging state of the first input end of the capacitor C DUT is measured.
Referring to fig. 6, between the second time node Q2 and the third time node Q3, a second level (i.e., 1.05V) is applied to the first control end and the input end of the first inverter 3, such that the first PMOS transistor MP1 and the first NMOS transistor MN1 are both in an off state, a second level (i.e., 1.05V) is applied to the third control end and the input end of the second inverter 4, such that the second PMOS transistor MP2 and the second NMOS transistor MN2 are both in an on state, a first level (i.e., 0V) is applied to the second end of the capacitor under test C DUT, at this time, the second output end pulls down the first end of the parasitic capacitor C PAR to the first level (i.e., 0V), the second input end pulls up the second end of the parasitic capacitor C PAR to the second level (i.e., 1.05V), such that the voltages at the two ends of the parasitic capacitor C PAR are opposite, and are in a charging state, the second output end pulls down the first end of the capacitor under test C DUT to the first level (i.e., 0V), such that the current at the two ends of the parasitic capacitor under test C DUT is equal, and the current at the two ends of the capacitor under test C DUT is equal, and the current of the second end of the capacitor under test C DUT is equal to the charging current, and the current of the first end of the capacitor under test C is measured b.3 is measured.
With continued reference to fig. 6, between the fourth time node Q4 and the fifth time node Q5, a first level (i.e., 0V) is applied to the first control end and the input end of the first inverter 3, so that the first PMOS transistor MP1 and the first NMOS transistor MN1 are both in a conducting state, a first level (i.e., 0V) is applied to the third control end and the input end of the second inverter 4, so that the second PMOS transistor MP2 and the second NMOS transistor MN2 are both in an off state, a second level (i.e., 1.05V) is applied to the second end of the capacitor under test C DUT, at this time, the first output end pulls up the first end of the parasitic capacitor C PAR to the second level (i.e., 1.05V), the second end of the parasitic capacitor C PAR is grounded, i.e., the first level (i.e., 0V) is opposite in voltage at two ends of the parasitic capacitor C PAR, the first output end pulls up the first end of the capacitor under test C DUT to the second level (i.e., 1.05V) is in a charging state, and the second end of the capacitor under test C DUT is no current measured at the second end of the first end of the capacitor under test C PAR, and the second end of the capacitor under test C DUT is no current measured at the second end of the first end of the capacitor under test 2 is charged.
In this embodiment, the capacitance value of the capacitor C DUT to be measured is obtained according to the first current result I 1 and the second current result I 2 Wherein V DD is the supply voltage and f is the frequency.
In this embodiment, between the first time node Q1 and the fourth time node Q4, the second level duration of the first clock signal Vp is longer than the second level duration of the second clock signal Vn, so that the second transmission gate 2 is controlled to be turned on when the first transmission gate 1 is completely turned off.
In the present embodiment, between the third time node Q3 and the fifth time node Q5, the first level duration of the second clock signal Vn is longer than the first level duration of the first clock signal Vp, so that the first transmission gate 1 is controlled to be turned on when the second transmission gate 2 is completely turned off.
Referring to fig. 3, the present invention further provides a working method of the test circuit, which includes applying a clock signal to the first control terminal and the third control terminal, applying a control signal to the second terminal of the element 5 to be tested, obtaining a current result of the first input terminal, and obtaining a nominal value of the element 5 to be tested based on the current result.
Referring to FIG. 5 or FIG. 6, the clock signal includes a first clock signal Vp and a second clock signal Vn, the control signal includes a first control signal Vapp1 and a second control signal Vapp2, the current result includes a first current result I 1 and a second current result I 2, the clock signal is applied to the first control terminal and the third control terminal, the control signal is applied to the second terminal of the device under test 5 and the current result of the first input terminal is obtained, and the nominal value of the device under test 5 is obtained based on the current result, including applying the first clock signal Vp to the first control terminal, applying the second clock signal Vn to the third control terminal, and applying the first control signal Vapp1 to the second terminal of the device under test 5 and obtaining the first current result I 1 of the first input terminal, applying the first clock signal Vp to the first control terminal, applying the second clock signal Vn to the third control terminal, and applying the second control signal Vapp2 to the second terminal of the device under test 5, obtaining the second current result I 2 of the first input terminal and obtaining the nominal current result I3824 of the first device under test 5 according to the first current result I3725 and the second current result I3824 of the first device under test 5.
In this embodiment, the first clock signal Vp, the second clock signal Vn, the first control signal Vapp1 and the second control signal Vapp2 have the same frequency, and sequentially include a first time node Q1, a second time node Q2, a third time node Q3, a fourth time node Q4 and a fifth time node Q5 in a measurement period, wherein the first clock signal Vp keeps the second level to the fourth time node Q4 after the first time node Q1 is switched from the first level to the second level, and keeps the first level to the fifth time node Q5 after the fourth time node Q4 is switched from the second level, and the second clock signal Vn keeps the second level to the third time node Q3 after the second time node Q2 is switched from the first level to the second level, and keeps the first level to the fifth time node Q5 after the third time node Q3 is switched from the second level to the first level.
In the present embodiment, the first control signal Vapp1 maintains the second level from the first time node Q1 to the fifth time node Q5.
In this embodiment, obtaining the first current result I 1 at the first input terminal includes obtaining the first current result I 1 at the first input terminal between the second time node Q2 and the third time node Q3.
In the present embodiment, the second control signal Vapp2 is switched from the second level to the first level between the first time node Q1 and the second time node Q2 and keeps the first level to the third time node Q3, and is switched from the first level to the second level between the third time node Q3 and the fourth time node Q4 and keeps the second level to the fifth time node Q5.
In this embodiment, obtaining the second current result I 2 at the first input terminal includes obtaining the second current result I 2 at the first input terminal between the second time node Q2 and the third time node Q3 or between the fourth time node Q4 and the fifth time node Q5.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (19)

1.一种测试电路，用于测量待测元件的标称值，其特征在于，包括：1. A test circuit for measuring the nominal value of a component under test, characterized in that it comprises: 第一传输门，包括第一输入端、第一输出端、第一控制端以及第二控制端，所述第一输入端耦接电源电压端；A first transmission gate, comprising a first input terminal, a first output terminal, a first control terminal and a second control terminal, wherein the first input terminal is coupled to a power supply voltage terminal; 第二传输门，包括第二输入端、第二输出端、第三控制端以及第四控制端，所述第二输出端连接所述第一输出端，所述第二输入端接地；A second transmission gate comprises a second input terminal, a second output terminal, a third control terminal and a fourth control terminal, wherein the second output terminal is connected to the first output terminal, and the second input terminal is grounded; 第一反相器，所述第一反相器的输入端连接所述第一控制端，所述第一反相器的输出端连接所述第二控制端；A first inverter, wherein an input end of the first inverter is connected to the first control end, and an output end of the first inverter is connected to the second control end; 第二反相器，所述第二反相器的输入端连接所述第四控制端，所述第二反相器的输出端连接所述第三控制端；A second inverter, wherein an input terminal of the second inverter is connected to the fourth control terminal, and an output terminal of the second inverter is connected to the third control terminal; 待测元件，所述待测元件的第一端连接所述第一输出端。A device under test, wherein a first end of the device under test is connected to the first output end. 2.如权利要求1所述的测试电路，其特征在于，还包括：电流计，所述电流计的第一端连接所述电源电压端，所述电流计的第二端连接所述第一输入端。2. The test circuit as claimed in claim 1, characterized in that it further comprises: an ammeter, a first end of the ammeter is connected to the power supply voltage end, and a second end of the ammeter is connected to the first input end. 3.如权利要求1所述的测试电路，其特征在于，所述第一传输门包括：第一PMOS管和第一NMOS管，所述第一PMOS管的栅极为所述第一控制端，所述第一NMOS管的栅极为所述第二控制端，所述第一PMOS管的源极与所述第一NMOS管的漏极耦接，并作为所述第一输入端，所述第一PMOS管的漏极与所述第一NMOS管的源极耦接，并作为所述第一输出端。3. The test circuit as described in claim 1 is characterized in that the first transmission gate comprises: a first PMOS tube and a first NMOS tube, the gate of the first PMOS tube is the first control terminal, the gate of the first NMOS tube is the second control terminal, the source of the first PMOS tube is coupled to the drain of the first NMOS tube and serves as the first input terminal, and the drain of the first PMOS tube is coupled to the source of the first NMOS tube and serves as the first output terminal. 4.如权利要求1所述的测试电路，其特征在于，所述第二传输门包括：第二PMOS管和第二NMOS管，所述第二PMOS管的栅极为所述第三控制端，所述第二NMOS管的栅极为所述第四控制端，所述第二PMOS管的源极与所述第二NMOS管的漏极耦接，并作为所述第二输出端，所述第二PMOS管的漏极与所述第二NMOS管的源极耦接，并作为所述第二输入端。4. The test circuit according to claim 1 is characterized in that the second transmission gate comprises: a second PMOS tube and a second NMOS tube, the gate of the second PMOS tube is the third control terminal, the gate of the second NMOS tube is the fourth control terminal, the source of the second PMOS tube is coupled to the drain of the second NMOS tube and serves as the second output terminal, and the drain of the second PMOS tube is coupled to the source of the second NMOS tube and serves as the second input terminal. 5.如权利要求1所述的测试电路，其特征在于，所述待测元件包括待测电容。5 . The test circuit as claimed in claim 1 , wherein the component under test comprises a capacitor under test. 6.如权利要求1所述的测试电路，其特征在于，还包括：与所述第一控制端、所述第三控制端、所述第一输入端以及所述待测元件的第二端耦接的测试模块，所述测试模块用于施加时钟信号至所述第一控制端和所述第三控制端，施加控制信号至所述待测元件的第二端，并获取所述第一输入端的电流结果，以及基于所述电流结果获取所述待测元件的标称值。6. The test circuit as described in claim 1 is characterized in that it also includes: a test module coupled to the first control end, the third control end, the first input end and the second end of the component under test, the test module is used to apply a clock signal to the first control end and the third control end, apply a control signal to the second end of the component under test, and obtain a current result of the first input end, and obtain a nominal value of the component under test based on the current result. 7.如权利要求6所述的测试电路，其特征在于，所述时钟信号包括第一时钟信号和第二时钟信号，所述控制信号包括第一控制信号和第二控制信号，所述电流结果包括第一电流结果和第二电流结果；7. The test circuit according to claim 6, wherein the clock signal comprises a first clock signal and a second clock signal, the control signal comprises a first control signal and a second control signal, and the current result comprises a first current result and a second current result; 所述测试模块用于施加第一时钟信号至所述第一控制端，施加第二时钟信号至所述第三控制端；施加第一控制信号或第二控制信号至所述待测元件的第二端，并在施加第一时钟信号、第二时钟信号和第一控制信号之后，获取所述第一输入端的第一电流结果，在施加第二控制信号之后，获取第一输入端的第二电流结果，以及根据所述第一电流结果和所述第二电流结果获取所述待测元件的标称值。The test module is used to apply a first clock signal to the first control end, and apply a second clock signal to the third control end; apply a first control signal or a second control signal to the second end of the component under test, and obtain a first current result of the first input end after applying the first clock signal, the second clock signal and the first control signal, and obtain a second current result of the first input end after applying the second control signal, and obtain a nominal value of the component under test based on the first current result and the second current result. 8.如权利要求7所述的测试电路，其特征在于，所述第一时钟信号、所述第二时钟信号、所述第一控制信号和所述第二控制信号的频率相同，且一个测量周期内依次包括第一时间节点、第二时间节点、第三时间节点、第四时间节点以及第五时间节点；8. The test circuit according to claim 7, wherein the frequencies of the first clock signal, the second clock signal, the first control signal and the second control signal are the same, and a measurement cycle includes a first time node, a second time node, a third time node, a fourth time node and a fifth time node in sequence; 在一个测量周期内，所述第一时钟信号在第一时间节点自第一电平转换至第二电平后，保持第二电平至第四时间节点，并在第四时间节点从第二电平转换为第一电平后，保持第一电平至第五时间节点；In one measurement cycle, after the first clock signal is converted from the first level to the second level at the first time node, it maintains the second level to a fourth time node, and after the first clock signal is converted from the second level to the first level at the fourth time node, it maintains the first level to a fifth time node; 在一个测量周期内，所述第二时钟信号在第二时间节点自第一电平转换至第二电平后，保持第二电平至第三时间节点，并在第三时间节点从第二电平转换为第一电平后，保持第一电平至第五时间节点。In a measurement cycle, after the second clock signal is converted from the first level to the second level at the second time node, it maintains the second level to a third time node, and after it is converted from the second level to the first level at the third time node, it maintains the first level to a fifth time node. 9.如权利要求8所述的测试电路，其特征在于，所述第一控制信号自第一时间节点至第五时间节点保持第二电平。9 . The test circuit as claimed in claim 8 , wherein the first control signal maintains a second level from the first time node to a fifth time node. 10.如权利要求9所述的测试电路，其特征在于，所述测量模块在第二时间节点到第三时间节点之间，获取所述第一输入端的第一电流结果。10 . The test circuit according to claim 9 , wherein the measurement module obtains the first current result of the first input terminal between the second time node and the third time node. 11.如权利要求8所述的测试电路，其特征在于，所述第二控制信号在第一时间节点至第二时间节点之间自第二电平转换为第一电平，并保持第一电平至第三时间节点，在第三时间节点至第四时间节点之间自第一电平转换为第二电平，并保持第二电平至第五时间节点。11. The test circuit as described in claim 8 is characterized in that the second control signal is converted from the second level to the first level between the first time node and the second time node, and maintains the first level to the third time node, and is converted from the first level to the second level between the third time node and the fourth time node, and maintains the second level to the fifth time node. 12.如权利要求11所述的测试电路，其特征在于，所述测量模块在第二时间节点到第三时间节点之间或在第四时间节点到第五时间节点之间，获取所述第一输入端的第二电流结果。12 . The test circuit according to claim 11 , wherein the measurement module obtains the second current result of the first input terminal between the second time node and the third time node or between the fourth time node and the fifth time node. 13.一种如权利要求1至5任一项所述测试电路的工作方法，其特征在于，包括：13. A working method of the test circuit according to any one of claims 1 to 5, characterized in that it comprises: 施加时钟信号至第一控制端和第三控制端，施加控制信号至待测元件的第二端，并获取第一输入端的电流结果，以及基于所述电流结果获取所述待测元件的标称值。A clock signal is applied to the first control terminal and the third control terminal, a control signal is applied to the second terminal of the DUT, and a current result of the first input terminal is obtained, and a nominal value of the DUT is obtained based on the current result. 14.如权利要求13所述测试电路的工作方法，其特征在于，所述时钟信号包括第一时钟信号和第二时钟信号，所述控制信号包括第一控制信号和第二控制信号，所述电流结果包括第一电流结果和第二电流结果；14. The working method of the test circuit according to claim 13, characterized in that the clock signal includes a first clock signal and a second clock signal, the control signal includes a first control signal and a second control signal, and the current result includes a first current result and a second current result; 所述施加时钟信号至所述第一控制端和所述第三控制端，施加控制信号至所述待测元件的第二端，并获取所述第一输入端的电流结果，以及基于所述电流结果获取所述待测元件的标称值，包括：The step of applying a clock signal to the first control terminal and the third control terminal, applying a control signal to the second terminal of the device under test, obtaining a current result of the first input terminal, and obtaining a nominal value of the device under test based on the current result comprises: 施加第一时钟信号至第一控制端，施加第二时钟信号至第三控制端，以及施加第一控制信号至所述待测元件的第二端，获取第一输入端的第一电流结果；Applying a first clock signal to the first control terminal, applying a second clock signal to the third control terminal, and applying a first control signal to the second terminal of the device under test to obtain a first current result of the first input terminal; 施加第一时钟信号至第一控制端，施加第二时钟信号至第三控制端，以及施加第二控制信号至所述待测元件的第二端，获取第一输入端的第二电流结果；Applying a first clock signal to the first control terminal, applying a second clock signal to the third control terminal, and applying a second control signal to the second terminal of the device under test to obtain a second current result of the first input terminal; 根据所述第一电流结果和第二电流结果，获取所述待测元件的标称值。The nominal value of the device under test is obtained according to the first current result and the second current result. 15.如权利要求14所述测试电路的工作方法，其特征在于，所述第一时钟信号、所述第二时钟信号、所述第一控制信号和所述第二控制信号的频率相同，且一个测量周期内依次包括第一时间节点、第二时间节点、第三时间节点、第四时间节点以及第五时间节点；15. The working method of the test circuit according to claim 14, characterized in that the frequencies of the first clock signal, the second clock signal, the first control signal and the second control signal are the same, and a measurement cycle includes a first time node, a second time node, a third time node, a fourth time node and a fifth time node in sequence; 在一个测量周期内，所述第一时钟信号在第一时间节点自第一电平转换至第二电平后，保持第二电平至第四时间节点，并再第四时间节点从第二电平转换为第一电平后，保持第一电平至第五时间节点；In one measurement cycle, after the first clock signal is converted from the first level to the second level at the first time node, it maintains the second level to a fourth time node, and after it is converted from the second level to the first level at the fourth time node, it maintains the first level to a fifth time node; 在一个测量周期内，所述第二时钟信号在第二时间节点自第一电平转换至第二电平后，保持第二电平至第三时间节点，并在第三时间节点从第二电平转换为第一电平后，保持第一电平至第五时间节点。In a measurement cycle, after the second clock signal is converted from the first level to the second level at the second time node, it maintains the second level to a third time node, and after it is converted from the second level to the first level at the third time node, it maintains the first level to a fifth time node. 16.如权利要求15所述测试电路的工作方法，其特征在于，所述第一控制信号自第一时间节点至第五时间节点保持第二电平。16 . The operating method of the test circuit as claimed in claim 15 , wherein the first control signal maintains a second level from the first time node to a fifth time node. 17.如权利要求16所述测试电路的工作方法，其特征在于，所述获取第一输入端的第一电流结果包括：在第二时间节点到第三时间节点之间，获取所述第一输入端的第一电流结果。17 . The working method of the test circuit according to claim 16 , wherein obtaining the first current result of the first input terminal comprises: obtaining the first current result of the first input terminal between the second time node and the third time node. 18.如权利要求15所述测试电路的工作方法，其特征在于，所述第二控制信号在第一时间节点至第二时间节点之间自第二电平转换为第一电平，并保持第一电平至第三时间节点，在第三时间节点至第四时间节点之间自第一电平转换为第二电平，并保持第二电平至第五时间节点。18. The operating method of the test circuit as described in claim 15 is characterized in that the second control signal is converted from the second level to the first level between the first time node and the second time node, and maintains the first level to the third time node, and is converted from the first level to the second level between the third time node and the fourth time node, and maintains the second level to the fifth time node. 19.如权利要求18所述测试电路的工作方法，其特征在于，所述获取第一输入端的第二电流结果包括：在第二时间节点到第三时间节点之间或在第四时间节点到第五时间节点之间，获取所述第一输入端的第二电流结果。19. The working method of the test circuit as claimed in claim 18, characterized in that obtaining the second current result of the first input terminal comprises: obtaining the second current result of the first input terminal between the second time node and the third time node or between the fourth time node and the fifth time node.
CN202310919875.0A 2023-07-25 2023-07-25 Test circuit and working method thereof Pending CN119375559A (en)

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