CN119364836A - Semiconductor structure, method for manufacturing semiconductor structure, and CMOS device - Google Patents
Semiconductor structure, method for manufacturing semiconductor structure, and CMOS device Download PDFInfo
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Abstract
The embodiment of the application provides a semiconductor structure, a manufacturing method of the semiconductor structure and a CMOS device, wherein the semiconductor structure comprises a substrate; the metal grid electrode is formed on the substrate, the surface of the metal grid electrode is provided with a groove, the groove extends along the surface of the metal grid electrode away from the substrate towards the direction close to the substrate, the groove is provided with a bottom surface side surface, the grid electrode contact structure is formed on one side of the metal grid electrode away from the substrate, and the grid electrode contact structure is in contact with the bottom surface and the side surface of the groove. By the embodiment of the application, the contact area of the gate contact structure and the metal gate is increased, the contact resistance between the gate contact structure and the metal gate is reduced, and the performance of the CMOS device is improved.
Description
Technical Field
Embodiments of the present application relate to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a CMOS device.
Background
CMOS transistors (Complementary Metal Oxide Semiconductor Field-Effect Transistor, CMOS FETs, complementary metal oxide semiconductor field effect transistors) are the primary semiconductor devices in large scale integrated circuits. With the improvement of the integration level of semiconductor devices, the feature size of the CMOS transistor is continuously reduced, and for process nodes of 40nm and below, physical effects such as short channel effect, hot carrier effect and the like may cause the decrease of the threshold voltage control capability of the CMOS transistor and the increase of leakage current, resulting in the substantial decrease of the performance of the CMOS transistor.
In the prior art, HKMG (High-K METAL GATE, high dielectric constant metal gate) is mainly used to replace the conventional polysilicon gate to improve the performance of the CMOS transistor. Specifically, the material of the HKMG gate dielectric layer is a dielectric material with a high dielectric constant, and the gate electrode is a conductive material containing a metal element. To enhance the performance of CMOS transistors containing HKMG, HKMG is mainly prepared using a Gate-Last Process (Gate-Last Process). After the CMOS transistor containing HKMG is fabricated using existing gate-last processes, CMOS devices can be fabricated based on the CMOS transistor.
However, when testing the above CMOS device manufactured based on the CMOS transistor including HKMG, the developer found that the contact resistance of HKMG in the CMOS transistor with the gate contact structure was large.
Disclosure of Invention
In view of this, various embodiments of the present application provide a semiconductor structure, a method of manufacturing a semiconductor structure, and a CMOS device to reduce contact resistance between HKMG and a gate contact structure in the CMOS device.
In one aspect, one embodiment of the application provides a semiconductor structure, which comprises a substrate, a metal gate formed on the substrate, wherein the surface of the metal gate is provided with a groove, the groove extends along the surface of the metal gate away from the substrate and towards the direction close to the substrate, the groove is provided with a bottom surface and a side surface, and a gate contact structure is formed on one side of the metal gate away from the substrate, wherein the gate contact structure is in contact with both the bottom surface and the side surface of the groove.
Optionally, the extending direction of the groove is the depth direction of the groove and the height direction of the metal grid, and the ratio of the depth of the groove to the height of the metal grid falls into the range of 1:4-2:5 along the extending direction of the groove.
The semiconductor structure further comprises an interlayer dielectric layer formed on the metal gate, wherein the interlayer dielectric layer is provided with a dielectric layer opening corresponding to the contact portion, the gate contact structure is contacted with the contact portion through the dielectric layer opening, and an air gap is formed between the gap portion and the interlayer dielectric layer.
In another aspect, one embodiment of the application provides a method for manufacturing a semiconductor structure, which comprises providing a substrate, wherein the substrate is provided with a gate groove, the gate groove is provided with a bottom surface and a side surface, the normal direction of the bottom surface of the gate groove is a first direction, the normal direction of the side surface of the gate groove is a second direction, a metal gate material is deposited on the substrate, a metal gate with a groove on the surface is formed in the gate groove, the deposition amount of the metal gate material along the first direction is larger than the deposition amount along the second direction, the groove extends along the surface of the metal gate away from the substrate to a direction close to the substrate, the groove is provided with a bottom surface and a side surface, a gate contact structure is formed on one side of the metal gate away from the substrate, and the gate contact structure is contacted with the bottom surface and the side surface of the groove.
Optionally, the groove is provided with a groove depth along the extending direction of the groove, the step of providing a base comprises the steps of providing a substrate, wherein the substrate comprises an NMOS region and a PMOS region, forming a dielectric layer on the substrate, wherein the distance between the surface of the dielectric layer away from the substrate and the substrate is not smaller than a specified value, the specified value is the sum of a gate base height value and the groove depth value, etching the dielectric layer, forming an NMOS dielectric layer opening and a PMOS dielectric layer opening in the dielectric layer corresponding to the NMOS region and the PMOS region, forming an NMOS gate dielectric layer and an NMOS dummy gate in the NMOS dielectric layer opening, and forming a PMOS gate dielectric layer and a PMOS dummy gate in the PMOS dielectric layer opening, wherein the distance between the surface of the NMOS dummy gate and the surface of the PMOS dummy gate away from the substrate is equal to the distance between the surface of the dielectric layer away from the substrate and the substrate, removing the dummy gate and the PMOS gate, obtaining a metal stop layer with a gate transition trench, and the base with a work function is formed on the surface of the transition metal stop layer.
Optionally, the step of depositing a metal gate material on the substrate and forming a metal gate with a groove on the surface in the gate groove comprises the steps of depositing the metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom surface and the side surface of the gate groove, wherein the metal gate material layer comprises a flat part formed on the surface of the substrate, a groove bottom formed on the bottom surface of the gate groove and a groove side part formed on the side surface of the gate groove, a metal gate groove is formed among the flat part, the groove bottom and the groove side part, the metal gate groove is filled, planarization treatment is carried out, and a metal gate with the groove on the surface and the filling part are formed in the gate groove, wherein the filling part is in contact with the bottom surface and the side surface of the groove.
Optionally, the step of depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom surface and the side surfaces of the gate trench comprises the steps of performing first deposition to obtain a first metal gate material layer formed on the surface of the substrate and the bottom surface and the two side surfaces of the gate trench, wherein the first metal gate material layer comprises a first flat portion formed on the surface of the substrate, a first trench bottom formed on the bottom surface of the gate trench and a first trench side portion formed on the side surfaces of the gate trench, the thickness of the first flat portion and the first trench bottom along the first direction is equal to the thickness of the first trench side portion along the second direction, and performing second deposition to obtain a second metal gate material layer formed on the surface of the first flat portion and the surface of the first trench bottom, wherein the second metal gate material layer comprises a second flat portion formed on the surface of the first flat portion and a first trench bottom portion and a first trench side portion formed on the side surface of the gate trench, the thickness of the first flat portion and the second trench bottom portion is equal to the thickness of the first flat portion and the second trench bottom portion along the second direction.
Optionally, the step of depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom surface and two sides of the gate trench includes performing third deposition to obtain a third metal gate material layer formed on the surface of the substrate and the bottom surface and two sides of the gate trench, wherein the third metal gate material layer includes a third flat portion formed on the surface of the substrate, a third trench bottom portion formed on the bottom surface of the gate trench, and a second trench side portion formed on the side surface of the gate trench, the thickness of the third flat portion along the first direction is equal to the thickness of the third trench bottom portion along the first direction, the thickness of the third flat portion along the first direction is greater than the thickness of the second trench side portion along the second direction, the metal gate trench is formed between the third flat portion, the third trench bottom portion, and the second trench side portion, and the metal gate material deposition rate along the first direction is within a range of 1:24 in the third deposition process.
Optionally, the groove comprises a contact part contacted with the grid contact structure, before the step of forming the grid contact structure on the side, far away from the substrate, of the metal grid, an interlayer dielectric layer is formed on the metal grid, the interlayer dielectric layer and the filling part corresponding to the contact part are removed, so that a dielectric layer opening corresponding to the contact part is formed in the interlayer dielectric layer, and the grid contact structure is contacted with the contact part through the dielectric layer opening.
Optionally, removing the interlayer dielectric layer and the filling part corresponding to the contact part under the condition that materials of the interlayer dielectric layer and the filling part are the same, so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact part, wherein the step of etching and removing the interlayer dielectric layer and the filling part corresponding to the contact part based on specified etching process parameters so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact part, and the interlayer dielectric layer and the filling part are removed in the same process step.
Optionally, the groove further comprises a gap part, and the step of removing the interlayer dielectric layer and the filling part corresponding to the contact part under the condition that materials of the interlayer dielectric layer and the filling part are different so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact part comprises the steps of removing the interlayer dielectric layer corresponding to the contact part based on specified etching process parameters, removing the filling part so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact part, and forming an air gap between the gap part and the interlayer dielectric layer.
In another aspect, an embodiment of the present application provides a CMOS device, which includes the semiconductor structure described in the above embodiment or a semiconductor structure manufactured according to the method for manufacturing a semiconductor structure described in the above embodiment.
In various embodiments of the present application, a metal gate is prepared by depositing a metal gate material on a substrate having a gate trench, wherein the gate trench has a bottom surface and a side surface, the normal direction of the bottom surface of the gate trench is a first direction, the normal direction of the side surface of the gate trench is a second direction, and during the deposition of the metal gate material, the deposition amount of the metal gate material along the first direction is controlled to be greater than the deposition amount along the second direction, so that the metal gate surface prepared by the deposition process has a groove, the groove also has a bottom surface and a side surface, and then a gate contact structure is prepared on a side of the metal gate away from the substrate, so that the gate contact structure is in contact with both the bottom surface and the side surface of the groove.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed to describe the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is an image of a gate contact structure and a metal gate contact provided in the related art.
Fig. 2 is a flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the application.
Fig. 3 is a schematic flow chart of providing a substrate according to an embodiment of the present application.
Fig. 4 is a schematic diagram of forming a dielectric layer on a substrate according to an embodiment of the present application.
Fig. 5 is a schematic diagram illustrating the formation of an NMOS dielectric opening and a PMOS dielectric opening according to an embodiment of the present application.
Fig. 6 is a schematic diagram of forming an NMOS gate dielectric layer, an NMOS dummy gate, a PMOS gate dielectric layer, and a PMOS dummy gate according to an embodiment of the present application.
Fig. 7 is a schematic view of a transition substrate according to an embodiment of the present application.
Fig. 8 is a schematic diagram of sequentially forming an etching stop layer and a first sub-work function material layer on a surface of a transition substrate according to an embodiment of the present application.
Fig. 9 is a schematic diagram of forming a photolithography functional layer on a surface of a first sub-work function layer according to an embodiment of the present application.
Fig. 10 is a schematic diagram of removing a first sub-work function material layer corresponding to an NMOS region according to an embodiment of the present application.
FIG. 11 is a schematic view of a substrate according to an embodiment of the present application.
Fig. 12 is a schematic flow chart of forming a metal gate with a groove on the surface in a gate trench according to an embodiment of the application.
Fig. 13 is a schematic diagram of sequentially forming a first metal gate material layer and a second metal gate material layer on a substrate according to an embodiment of the present application.
Fig. 14 is a schematic view illustrating forming a third metal gate material layer on a substrate according to another embodiment of the present application.
Fig. 15 is a schematic view of forming a metal gate and a filling portion after a planarization process according to an embodiment of the present application.
Fig. 16 is a schematic view of forming a dielectric layer opening corresponding to a contact portion in an interlayer dielectric layer according to an embodiment of the present application.
Fig. 17 is a three-dimensional schematic diagram of a metal gate with grooves on the surface according to an embodiment of the present application.
Fig. 18 is a three-dimensional schematic diagram of a gate contact structure contacting a metal gate through a recess according to an embodiment of the present application.
Fig. 19 is a schematic view of an air gap formed according to an embodiment of the present application.
Fig. 20 is a schematic diagram of forming a gate contact structure according to an embodiment of the present application.
Description of the structural reference numerals
100. Substrate, 101, NMOS region, 102, PMOS region, 103, separation region, 110, dielectric layer, 111, dielectric material portion, 112, sidewall portion, 113, NMOS dielectric layer opening, 114, PMOS dielectric layer opening, 120, NMOS gate dielectric layer, 130, NMOS gate etch stop layer, 140, NMOS dummy gate, 150, PMOS gate dielectric layer, 160, PMOS gate etch stop layer, 170, PMOS dummy gate, 180, gate transition trench, 181, NMOS gate transition trench, 182, PMOS gate transition trench, 200, transition substrate, 210, etch stop layer, 220, first sub-work function layer, 230, photolithography function layer, 231, bottom anti-reflection coating, 232, photoresist layer, 240, second sub-work function layer, 300, substrate, 301, gate trench, 310, first metal gate material layer, 320, second metal gate material layer, 330, third metal gate material layer, 340, metal gate, 341, recess 3411, contact portion, 3412, gap portion, 350, fill portion, 360, dielectric layer, 370, gate contact structure, 372, 380, air gap portion, air contact structure.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments.
The drawings provided in the embodiments of the present application are merely to illustrate the basic idea of the present application by way of illustration, in which only the components related to the present application are shown instead of being drawn according to the number, shape and size of the components in actual implementation, the form, number and proportion of the components in actual implementation may be changed, and the layout forms of the components may be more complicated.
In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc. refer to an orientation or a positional relationship based on that shown in the drawings, only for convenience of description of the present application, and do not indicate or imply that the apparatus or components referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features.
With the development of semiconductor technology, the performance of conventional CMOS transistors using polysilicon as a gate material has been difficult to meet the requirements of high performance integrated circuits due to polysilicon depletion, boron transfer effect and fermi pinning effect of P-type MOS transistors. To overcome the above problems, in the related art, a CMOS transistor may be manufactured using HKMG instead of a polysilicon gate.
In order to control the metal work function in the metal gate material, improve the mobility of carriers in the channel of the CMOS transistor, improve the performance of the CMOS transistor and reduce the power consumption, the main preparation process of HKMG is a back gate process at present. After the CMOS transistor including HKMG is fabricated using the existing back gate process, electrical connection between the CMOS transistor and an external circuit may be achieved through a gate contact structure to fabricate a high-integration CMOS device.
In the process of testing the CMOS device with high integration, research and development personnel find that part of performance indexes of the CMOS transistor are improved to a certain extent, for example, threshold voltage control capability is enhanced, leakage current is reduced, working frequency is accelerated, and the like. However, a reduction in some performance indexes of the CMOS transistor occurs, for example, a reduction in maximum output current, an increase in energy loss, an increase in signal transmission delay, a reduction in reliability, and the like.
Research and development personnel further test the high-integration CMOS device by adopting various technical means, and find that the contact resistance between the HKMG and the grid contact structure is larger, so that the on-resistance of the transistor is increased, the energy loss of a contact area is increased, hot spots are formed in a working state, and the performance index is reduced.
Further, it is known that, according to the existing post-gate process flow, after the HKMG is manufactured, a layer of interlayer dielectric layer (INTER LAYER DIELECTRIC, ILD) is formed on the HKMG, and the interlayer dielectric layer is dry etched to form a dielectric layer opening corresponding to the HKMG, through which the gate contact structure contacts the HKMG. Specifically, the material of the interlayer dielectric layer is usually oxide, and the etching gas used for dry etching the interlayer dielectric layer is a gas containing carbon (C) element and fluorine (F) element, such as carbon tetrafluoride (CF 4), hexafluoroethane (C 2F6), and the like. However, these gases cannot etch the HKMG, and therefore, only the bottom surface of the gate contact structure can contact the HKMG. Please refer to fig. 1. The contact area between HKMG and the gate contact structure is small, resulting in a large contact resistance.
Therefore, it is necessary to provide a semiconductor structure and a method for manufacturing the same, in which a groove having a bottom surface and a side surface is formed on a surface of a metal gate included in the semiconductor structure, and a gate contact structure is in contact with both the bottom surface and the side surface of the groove, so as to increase a contact area between the gate contact structure and the metal gate, thereby reducing a contact resistance between the gate contact structure and the metal gate, and improving performance of a CMOS device including the semiconductor structure.
Please refer to fig. 2. One embodiment of the present application provides a method of manufacturing a semiconductor structure. The method of manufacturing the semiconductor structure may include steps S110, S120, and S130.
And S110, providing a substrate.
Please refer to fig. 3. In the present embodiment, providing the substrate may include steps S111, S112, S113, S114, S115, and S116.
And S111, providing a substrate.
Please refer to fig. 4. In this embodiment, the substrate 100 may be the basis for CMOS transistor formation. In particular, the substrate 100 may comprise a substrate. The substrate may be formed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. For example, the substrate may be made of silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), or the like. The substrate may have a single-layer structure or a multilayer structure. In this embodiment, a silicon wafer is used as a substrate in combination with factors such as dielectric loss requirements, manufacturing process, manufacturing cost, and the like.
In this embodiment, the substrate 100 may include an NMOS region 101 and a PMOS region 102. Specifically, an N-well (NW) and a P-well (P-well, PW) may be defined in the substrate. After the N-well and P-well are formed, the location of the active region (ACTIVE AREA, AA) may be defined and a separation region 103 formed in the substrate. For example, the separation region 103 may be a shallow trench isolation (Shallow Trench Isolation, STI) structure for reducing leakage. Subsequently, different types of dopant ions may be implanted into regions of the substrate to form lightly doped Source Drain regions (Lightly Doped Drain, LDD), pocket doped regions (Pocket), and Source and Drain regions (S/D) in the substrate, resulting in a substrate 100 comprising NMOS region 101 and PMOS region 102. Wherein, NMOS region 101 corresponds to an N-well, and PMOS region 102 corresponds to a P-well.
And S112, forming a dielectric layer on the substrate.
In this embodiment, the dielectric layer 110 may include a dielectric material portion 111 and a sidewall portion 112. Specifically, a layer of insulating oxide may be deposited on the substrate 100 to obtain a layer of dielectric material. And etching the dielectric material layer to obtain two dielectric material layer openings corresponding to the NMOS region 101 and the PMOS region 102 respectively. The dielectric material layer remaining after etching is the dielectric material portion 111. Subsequently, a Gate Oxide (GOX) and a Gate sidewall (Spacer) may be prepared in the two dielectric material layer openings, respectively, to constitute the sidewall portion 112.
Since there are multiple planarization processes in the subsequent process flow, each planarization process may generate a recess (Dish) on the surface of the structure, and in order to reduce the residual impurities in the recess, a certain degree of over-treatment is required for each planarization process. However, the over-treatment may result in a reduced height of the metal gate. In addition, since it is necessary to prepare a metal gate having a groove on the surface, the height of the metal gate below the groove is also low with respect to the metal gate at other positions. The height of the metal gate has an important influence on the control capability of the metal gate on the channel current, and the reduction of the height of the metal gate leads to the weakening of the control capability of the metal gate on the channel current, thereby leading to the performance degradation of the CMOS transistor. Therefore, to solve the above-mentioned problem, an amount of redundancy for over-processing and forming grooves on the surface of the metal gate may be reserved in the process of preparing the dielectric layer 110 to increase the height of the planarized metal gate.
In the present embodiment, the distance between the surface of the dielectric layer 110 away from the substrate 100 and the substrate 100 is not less than a specified value. Specifically, the specified value may be a sum of a gate base height value and a recess depth value. The gate base height and recess depth may be determined by device design parameters. For example, the gate base height value is 500 a and the recess depth value is 200 a, then the specified value may be 700 a.
And S113, etching the dielectric layer, and forming an NMOS dielectric layer opening and a PMOS dielectric layer opening in the dielectric layer corresponding to the NMOS region and the PMOS region.
Please refer to fig. 5. In order to realize the subsequent preparation of the gate dielectric layer with high dielectric constant and the polysilicon dummy gate, in this embodiment, a portion of the gate oxide in the sidewall 112 of the dielectric layer 110 may be etched, and an NMOS dielectric opening 113 corresponding to the NMOS region 101 and a PMOS dielectric opening 114 corresponding to the PMOS region 102 are formed in the dielectric layer 110. Specifically, for process nodes of 40nm and below, the opening width D1 of the NMOS dielectric opening 113 and the opening width D2 of the PMOS dielectric opening 114 may both fall within the range of 38nm to 42nm. D1 and D2 may be equal, e.g. D1 and D2 may each be 38nm, 39nm, 40nm, 41nm, 42nm.
S114, forming an NMOS gate dielectric layer and an NMOS dummy gate in the NMOS dielectric layer opening, and forming a PMOS gate dielectric layer and a PMOS dummy gate in the PMOS dielectric layer opening.
Please refer to fig. 6. In this embodiment, the NMOS gate dielectric layer 120, the NMOS gate etch stop layer 130, and the NMOS dummy gate 140 may be sequentially deposited in the NMOS dielectric layer opening 113, and the PMOS gate dielectric layer 150, the PMOS gate etch stop layer 160, and the PMOS dummy gate 170 may be sequentially deposited in the PMOS dielectric layer opening 114. Specifically, the materials of the NMOS gate dielectric layer 120 and the PMOS gate dielectric layer 150 may be high dielectric constant materials, for example, hafnium oxide ((HfO 2), hafnium silicate (HfSiO), aluminum oxide (Al 2O3), etc., the materials of the NMOS gate etch stop layer 130 and the PMOS gate etch stop layer 160 may be titanium nitride (TiN), and the materials of the NMOS dummy gate 140 and the PMOS dummy gate 170 may be polysilicon.
To further enhance the performance of the CMOS transistor, in this embodiment, after the NMOS dummy gate 140 and the PMOS dummy gate 170 are formed, stress memorization techniques (Stress Memorization Technique, SMT), self-aligned double layer (Self-Aligned Bilayer, SAB), metal epitaxy, metal silicide formation, sigma (Sigma) trench formation, and the like may be further performed.
In this embodiment, after the above-mentioned process is completed, a Planarization process may be performed using a Chemical Mechanical Polishing (CMP) process, so that the distance between the surface of the NMOS dummy gate 140 and the PMOS dummy gate 170 away from the substrate 100 and the substrate 100 may be equal to the distance between the surface of the dielectric layer 110 away from the substrate 100 and the substrate 100.
And S115, removing the NMOS dummy gate and the PMOS dummy gate to obtain a transition substrate with a gate transition groove.
Please refer to fig. 7. To achieve the formation of the metal gate, in this embodiment, the NMOS dummy gate and the PMOS dummy gate may be removed by dry etching and wet etching, so that the NMOS gate etch stop layer 130 is exposed in the NMOS gate transition trench 181 and the PMOS gate etch stop layer 160 is exposed in the PMOS gate transition trench 182. Specifically, the dry etching gas may be chlorine (Cl 2) with an etching selectivity of 1:0 for polysilicon and for silicon nitride and silicon oxide, i.e., during dry etching with chlorine, only polysilicon is removed and silicon nitride and silicon oxide are not removed.
And S116, sequentially forming an etching stop layer and a metal work function layer on the surface of the transition substrate to obtain the substrate with the gate groove.
Please refer to fig. 8 to 11. To optimize the threshold voltage of the CMOS transistor, the materials and structures of the metal work function layer of the NMOS transistor and the metal work function layer of the PMOS transistor may be different. Specifically, the metal work function layer of the NMOS transistor is typically a single-layer structure formed of titanium aluminum nitride (TiAlN), while the metal work function layer of the PMOS transistor is typically a double-layer structure formed of titanium nitride and titanium aluminum nitride. Therefore, in this embodiment, the etching stop layer 210 and the first sub-work-function layer 220 may be sequentially deposited on the surface of the transition substrate 200, then the first sub-work-function layer 220 of the NMOS region 101 is removed, and then the second sub-work-function layer 240 is deposited, so as to obtain the substrate 300 with the gate trench 301.
Please refer to fig. 8. In this embodiment, the etch stop layer 210 may be deposited on the transition substrate surface using a PVD (Physical Vapor Deposition ) process. The material of the etch stop layer 210 may be tantalum nitride (TaN). The etch stop layer 210 may serve as an etch stop layer for the first sub-work function layer 220 and reduce metal penetration. Subsequently, a PVD process may be re-used to deposit a first sub-work function layer 220 on the surface of the etch stop layer 210. The material of the first sub-work function layer 220 may be titanium nitride.
Please refer to fig. 9 and 10. To remove the first sub-work-function layer 220 of the NMOS region 101, in this embodiment, a photolithographic functional layer 230 may be deposited on the surface of the first sub-work-function layer 220. The photoresist functional layer 230 includes a bottom anti-reflection coating 231 formed on the surface of the first sub-work function layer 220 and a photoresist layer 232 formed on the surface of the bottom anti-reflection coating 231. Subsequently, the photoresist layer 232 and the bottom anti-reflective coating 231 of the NMOS region 101 may be removed using an exposure development, and the first sub-work function layer 220 of the NMOS region 101 may be removed by etching, such that the etch stop layer 210 of the NMOS region 101 is exposed. Next, the photolithographic functional layer 230 of the PMOS region 102 may be removed using a similar process, such that the first sub-work function layer 220 of the PMOS region 102 is exposed.
Please refer to fig. 11. To form the metal work function layer of the PMOS transistor, in this embodiment, the second sub-work function layer 240 may be deposited using a PVD process, resulting in the substrate 300 having the gate trench 301. Specifically, the material of the second sub-work function layer 240 may be titanium aluminum nitride. It should be noted that, the thickness direction of the second sub-work-function layer 240 may be the growth direction of the second sub-work-function layer 240, and since the second sub-work-function layer 240 corresponding to the NMOS region 101 and the second sub-work-function layer 240 corresponding to the PMOS region 102 are formed in the same process, in the actual manufacturing process, the thickness of the second sub-work-function layer 240 corresponding to the NMOS region 101 in the thickness direction is greater than the thickness of the second sub-work-function layer 240 corresponding to the PMOS region 102 in the thickness direction.
In this embodiment, the gate trench 301 has a bottom surface and side surfaces. The normal direction of the bottom surface of the gate trench 301 is a first direction, and the normal direction of the side surface of the gate trench 301 is a second direction.
And S120, depositing a metal gate material on the substrate, and forming a metal gate with a groove on the surface in the gate groove.
In the related art, grooves can also be prepared on the surface of the metal gate by changing etching gas or changing etching process. For example, in the case where the material of the metal gate electrode is aluminum (Al), the metal gate electrode may be dry-etched using a gas containing a seventh main group element, such as chlorine, as an etching gas to prepare the recess. However, such etching gases may introduce impurity elements, resulting in degradation of CMOS transistor performance. The metal gate can also be subjected to dry etching by adopting a special dry etching process to prepare the groove, however, the special process needs to be finished in a special etching chamber, and the process cost is high. Accordingly, to avoid increasing process costs or introducing impurities, a metal gate having a groove on a surface thereof may be formed in the gate trench 301 of the substrate 300 by controlling deposition amounts of metal gate materials in different directions using a deposition process.
Please refer to fig. 11 and 12. In the present embodiment, forming a metal gate having a groove on a surface thereof in the gate trench may include steps S121, S122, and S123.
And S121, depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom surface and the side surface of the gate trench.
In this embodiment, the metal gate material may be aluminum. In some embodiments, the metal gate material may also be platinum (Pt), ruthenium (Ru), molybdenum (Mo), or the like. The metal gate material is not particularly limited in this specification.
In this embodiment, the shape of the metal gate material layer may match the shape of the surface of the substrate 300 and the shape of the gate trench 301. Specifically, the metal gate material layer may include a flat portion formed on the surface of the substrate 300, a trench bottom formed on the bottom surface of the gate trench 301, and a trench side portion formed on the side surface of the gate trench 301. Wherein a metal gate trench is formed between the flat portion, the trench bottom and the trench sides.
In this embodiment, the amount of deposition of the metal gate material in the first direction is greater than the amount of deposition in the second direction.
Please refer to fig. 13. To enhance the control over the shape of the metal gate material layer, in this embodiment, the metal gate material layer may be formed by two depositions. Specifically, the step of depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench may include performing a first deposition to obtain a first metal gate material layer 310 formed on the surface of the substrate and the bottom and side surfaces of the gate trench, and performing a second deposition to obtain a second metal gate material layer 320 formed on the surface of the first flat portion and the surface of the bottom of the first trench.
In this embodiment, the ratio of the rate of depositing the metal gate material in the first direction to the rate of depositing the metal gate material in the second direction may be 1:1 during the first deposition, i.e., the deposition rate of depositing the metal gate material in the first direction is equal to the deposition rate of depositing the metal gate material in the second direction during the first deposition.
Accordingly, in the present embodiment, the shape of the first metal gate material layer 310 may be matched to the shape of the substrate surface and the shape of the gate trench. Specifically, the first metal gate material layer 310 may include a first flat portion formed on the substrate surface, a first trench bottom formed on the bottom surface of the gate trench, and a first trench side portion formed on the side surface of the gate trench. In the first metal gate material layer 310, the thickness of the first flat portion and the first trench bottom in the first direction is equal to the thickness of the first trench side portion in the second direction. The thickness of the first flat portion and the first trench bottom along the first direction and the thickness of the first trench side portion along the second direction may both fall within the range of 10 a to 20 a. For example, the thickness of the first flat portion and the first trench bottom in the first direction and the thickness of the first trench side in the second direction may be 10 a, 12a, 15 a, 18 a, 20 a.
In this embodiment, during the second deposition, the ratio of the rate of depositing the metal gate material along the first direction to the rate of depositing the metal gate material along the second direction may fall within the range of 495:0-505:0. For example, the ratio of the rate of depositing the metal gate material in the first direction to the rate of depositing the metal gate material in the second direction may be 495:0, 497:0, 500:0, 502:0, 505:0, i.e., during the second deposition process, the metal gate material is deposited only in the first direction and not in the second direction.
Accordingly, in the present embodiment, the second metal gate material layer 320 may include a second flat portion formed on a surface of the first flat portion and a second trench bottom formed on the first trench bottom. In the second metal gate material layer 320, the thickness of the second flat portion along the first direction is equal to the thickness of the second trench bottom along the first direction. Specifically, the thickness of the second flat portion along the first direction and the thickness of the bottom of the second trench along the first direction may fall within the range of 495 a to 505 a. For example, the thickness of the second flat portion along the first direction and the thickness of the second trench bottom along the first direction may be 495 a, 497 a, 500 a, 502 a, 505 a.
In the case where the metal gate material layer is formed by two depositions, the metal gate trench may be formed between the second flat portion, the second trench bottom portion, and the first trench side portion.
Please refer to fig. 14. To simplify process parameters, reduce process difficulty, and reduce process costs, in some embodiments, the metal gate material layer may be formed by one deposition. Specifically, the step of depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench may include performing a third deposition to obtain a third metal gate material layer 330 formed on the surface of the substrate and the bottom and side surfaces of the gate trench.
In this embodiment, in the third deposition process, the ratio of the rate of depositing the metal gate material along the first direction to the rate of depositing the metal gate material along the second direction may fall within the range of 24:1 to 26:1. For example, the ratio of the rate of depositing metal gate material in the first direction to the rate of depositing metal gate material in the second direction may be 24:1, 25:1, 26:1, i.e., during the third deposition process, the deposition rate of depositing metal gate material in the first direction is greater than the deposition rate of depositing metal gate material in the second direction.
In this embodiment, the shape of the third metal gate material layer 330 may match the shape of the substrate surface and the shape of the gate trench. Specifically, the third metal gate material layer 330 may include a third flat portion formed on the substrate surface, a third trench bottom formed on the bottom surface of the gate trench, and a second trench side portion formed on the side surface of the gate trench. The thicknesses of the third flat portion and the third trench bottom along the first direction may fall within a range of 495 a to 505 a. The thickness of the second trench side along the second direction may fall within the range of 18 a to 22 a. For example, the thickness of the third flat portion and the third trench bottom along the first direction may be 495 a, 497 a, 500 a, 502 a, 505 a. The second trench side may have a thickness in the second direction of 18 a, 19 a, 20 a, 21 a, 22 a.
In the case where the metal gate material layer is formed by one deposition, the metal gate trench may be formed between the third flat portion, the third trench bottom, and the second trench side portion.
In embodiments of the present application, the first deposition, the second deposition, and the third deposition may all be performed using PVD processes. The deposition rate of the metal gate material in the first direction and the deposition rate in the second direction may be controlled, respectively.
And S122, filling the metal gate trench.
To protect the trench bottom and the trench sides formed in the gate trench from damage during a subsequent planarization process, the metal gate trench may be filled with a specified material.
In this embodiment, the fill material may be deposited in the metal gate trench using a chemical vapor deposition (Chemical Vapor Deposition, CVD) process or a Hot wire assisted rapid plasma deposition (Hot WIRE ASSISTED RAPID PLASMA, HARP) process. In particular, the filler material may include a first filler material and a second filler material. Wherein the first filler material may be an oxide. The second filling material may be a material that is easily decomposed by heat or shrunk by heat, or the second filling material may be a material that can be etched away using hydrogen chloride (HCl) gas.
And S123, performing planarization treatment, and forming a metal gate with a groove on the surface and a filling part in the gate groove.
Please refer to fig. 15 to 19. In this embodiment, the portions of the substrate surface etch stop layer 210 and beyond may be removed using a chemical mechanical polishing process, and the polishing head is stopped on the surface of the dielectric layer 110 using endpoint detection (Endpoint Detection, EPD) to preserve the structure formed inside the gate trench.
In the present embodiment, the recess 341 on the surface of the metal gate 340 extends along the surface of the metal gate 340 away from the substrate in a direction approaching the substrate. The recess 341 has a bottom surface and side surfaces.
In this embodiment, the filling portion 350 is in contact with both the bottom surface and the side surface of the recess 341.
In this embodiment, the recess 341 may include a contact portion 3411 and a gap portion 3412 contacting the gate contact structure.
In order to achieve electrical isolation between the metal gate 340 and other metal connection lines, reduce parasitic effects, and improve reliability and performance of the CMOS device, in this embodiment, before the step of forming the gate contact structure on the side of the metal gate 340 away from the substrate, the method for manufacturing the semiconductor structure may further include forming an interlayer dielectric layer 360 on the metal gate 340, and removing the interlayer dielectric layer 360 and the filling portion 350 corresponding to the contact portion 3411, so that the interlayer dielectric layer 360 forms a dielectric layer opening corresponding to the contact portion 3411.
In this embodiment, an interlayer dielectric layer 360, an amorphous carbon layer, a silicon oxynitride layer, an oxide layer, and a photolithography functional layer may be sequentially deposited on the metal gate 340, the photolithography functional layer is removed by exposure and development, and the oxide layer, the silicon oxynitride layer, the amorphous carbon layer, the interlayer dielectric layer 360, and the filling portion 350 corresponding to the contact portion 3411 are sequentially removed by multi-step etching, thereby forming a dielectric layer opening corresponding to the contact portion 3411 in the interlayer dielectric layer 360.
In this embodiment, the material of the interlayer dielectric layer 360 may be an insulating oxide. Specifically, the material of the interlayer dielectric layer 360 may be the same as or different from the material of the dielectric material portion 111 in the dielectric layer 110. In the case where the material of the interlayer dielectric layer 360 and the material of the dielectric material portion 111 are different, the material of the interlayer dielectric layer 360 may be insulating oxide having a porous property so as to reduce parasitic capacitance between the metal structures such as the metal gate 340 and the metal connection line isolated by the interlayer dielectric layer 360.
In this embodiment, after forming the dielectric layer opening corresponding to the contact portion 3411, the gate contact structure may contact the contact portion 3411 through the dielectric layer opening.
In this embodiment, the process of removing the interlayer dielectric layer 360 corresponding to the contact portion 3411 and the filling portion 350 is different for the filling portion 350 of different materials.
In order to shorten the overall processing time of the CMOS device, reduce the number of process steps and reduce the process cost, in this embodiment, in the case that the materials of the interlayer dielectric layer 360 and the filling portion 350 are the same, the step of removing the interlayer dielectric layer 360 and the filling portion 350 corresponding to the contact portion 3411 so that the interlayer dielectric layer 360 forms a dielectric layer opening corresponding to the contact portion 3411 may include etching to remove the interlayer dielectric layer 360 and the filling portion 350 corresponding to the contact portion based on specified etching process parameters so that the interlayer dielectric layer 360 forms a dielectric layer opening corresponding to the contact portion 3411. Specifically, the interlayer dielectric layer 360 and the filling portion 350 corresponding to the contact portion 3411 may be removed in the same process step. Note that, in this case, the interlayer dielectric layer 360 and the filling portion 350 corresponding to the gap portion 3412 are not removed. The specified etching process parameters may be etching parameters used for removing the interlayer dielectric layer 360 in the related art, and will not be described herein.
In the case that materials of the interlayer dielectric layer 360 and the filling part 350 are different, the step of removing a portion of the interlayer dielectric layer 360 and the filling part 350 such that the interlayer dielectric layer 360 forms a dielectric layer opening corresponding to the contact part 3411 may include etching and removing a portion of the interlayer dielectric layer 360 based on a specified etching process parameter, removing the filling part 350 such that the interlayer dielectric layer 360 forms a dielectric layer opening corresponding to the contact part 3411, and forming an air gap 380 between the gap part 3412 and the interlayer dielectric layer 360. Note that in this case, the interlayer dielectric layer 360 corresponding to the gap portion 3412 is not removed, and the filling portion 350 corresponding to the gap portion 3412 has been removed.
In this embodiment, the dry etching removal filling portion 350 may be performed using a specified etching gas. Specifically, the specified etching gas may be hydrogen chloride.
In some embodiments, the filling portion 350 may also be removed by heating. In particular, the temperature to which heating is required may be determined according to the decomposition temperature or the shrinkage temperature of the material of the filling part 350.
In this embodiment, the air gap 380 formed between the gap portion 3412 and the interlayer dielectric layer 360 can reduce the parasitic capacitance of the CMOS device, thereby reducing the signal delay caused by the signal network composed of the resistor (R) and the capacitor (C) in the CMOS device, and improving the performance of the CMOS device.
And S130, forming a gate contact structure on one side of the metal gate away from the substrate.
Please refer to fig. 20. After forming the metal gate 340 having the groove on the surface, the gate contact structure 370 may be formed in the groove on the side of the metal gate 340 away from the substrate, thereby increasing the contact area between the gate contact structure 370 and the metal gate 340 and reducing the contact resistance between them.
In this embodiment, the gate contact structure 370 contacts both the bottom and side surfaces of the recess 341.
In this embodiment, the step of forming the gate contact structure 370 on the side of the metal gate 340 remote from the substrate may include forming a contact spacer 371 in the contact portion and forming a contact metal 372 in the contact metal trench.
In this embodiment, the material of the contact metal 372 may be tungsten (W).
In the related art, tungsten deposition is typically performed using tungsten fluoride (WF 6) to form the contact metal 372. Tungsten fluoride has a strong oxidizing property and may damage the metal gate 340 if it is directly contacted with the metal gate 340. To avoid damage to the metal gate 340 during formation of the contact metal 372, in this embodiment, a contact isolation layer 371 may be formed in the contact portion of the recess to isolate the contact metal 372 from the metal gate 340.
In this embodiment, the shape of the contact spacer 371 matches the shape of the groove. In particular, the contact spacer 371 may include a bottom contact spacer and a sidewall contact spacer. Wherein, the bottom contact isolation layer is contacted with the bottom surface of the contact part. The sidewall contact spacer contacts a side of the contact portion. The bottom contact isolation layer and the sidewall contact isolation layer may form a contact metal trench.
In the related art, the contact spacer 371 is generally prepared using a substance containing titanium (Ti) element, for example, titanium metal or titanium nitride. However, the titanium metal is susceptible to reaction with the tungsten fluoride, which if brought into direct contact with the tungsten fluoride may cause defects in the contact metal 372 or cause the gate contact structure 370 to peel off from the metal gate 340, reducing the yield of CMOS devices. The titanium nitride has a larger stress, and if the titanium nitride is in direct contact with the metal gate 340, the gate contact structure 370 may be peeled off from the metal gate 340, so that the titanium nitride may be used to isolate the titanium metal from the tungsten fluoride to avoid contact and diffusion between the titanium metal and the tungsten fluoride, and at the same time, the titanium metal may be used as a buffer layer between the titanium nitride and the metal gate 340 to improve the bonding force between the gate contact structure 370 and the metal gate 340.
In this embodiment, the contact spacer 371 may include a first sub-spacer and a second sub-spacer. Specifically, the first sub-spacer layer is in contact with the bottom surface and the side surface of the contact portion. The material of the first sub-isolation layer may be titanium. The second sub-isolation layer is formed on the surface of the first sub-isolation layer. The material of the second sub-isolation layer may be titanium nitride.
In this embodiment, the contact spacer 371 may be prepared using a PVD process.
In this embodiment, after the contact metal trench is formed, the contact metal 372 may be deposited in the contact metal trench so that the contact isolation layer 371 may cover the contact metal 372.
Please refer to fig. 17 to 20. One embodiment of the present application provides a semiconductor structure that may include a substrate, a metal gate 340 formed on the substrate, and a gate contact structure 370 formed on a side of the metal gate 340 remote from the substrate.
To increase the contact area between the metal gate 340 and the gate contact structure 370, in the present embodiment, the surface of the metal gate 340 may have a recess 341. Specifically, the recess 341 may extend along the surface of the metal gate 340 away from the substrate toward the substrate.
In order to reduce the contact resistance between the metal gate 340 and the gate contact structure 370 without affecting the performance of the metal gate 340, in this embodiment, the extending direction of the recess 341 may be taken as the depth direction of the recess 341 and the height direction of the metal gate 340, and the ratio of the depth of the recess 341 to the height of the metal gate 340 may fall within the range of 1:4 to 2:5 along the extending direction of the recess 341. Specifically, the depth of the recess 341 may fall within the range of 190 a to 210 a, and the height of the metal gate 340 may fall within the range of 500 a to 800 a. For example, the depth of recess 341 may be 190 a, 200 a, 210 a, and the height of metal gate 340 may be 500 a, 600 a, 700 a, 800 a.
In this embodiment, the recess 341 may have a bottom surface and side surfaces.
In this embodiment, the recess 341 may include a contact portion 3411 contacting the gate contact structure 370. Accordingly, the semiconductor structure may further include an interlayer dielectric layer 360 formed on the metal gate 340. Specifically, the interlayer dielectric layer 360 has a dielectric layer opening corresponding to the contact portion 3411. The gate contact structure 370 may contact the contact 3411 through the dielectric layer opening.
To reduce signal delays caused by a signal network consisting of resistance (R) and capacitance (C) in the CMOS device, and to improve performance of the CMOS device, recess 341 may further include a gap portion 3412 in some embodiments. An air gap 380 may be formed between gap portion 3412 and interlayer dielectric layer 360.
In this embodiment, the gate contact structure 370 may contact both the bottom and side surfaces of the recess 341. Specifically, the gate contact structure 370 may include a contact spacer 371 and a contact metal 372. Wherein the contact spacer 371 is in contact with both the bottom and side surfaces of the recess 341. The contact spacer 371 may include a first sub-spacer and a second sub-spacer. The first sub-spacer contacts both the bottom and side surfaces of the recess 341. The material of the first sub-isolation layer may be titanium. The second sub-isolation layer may be formed on the first sub-isolation layer. The material of the second sub-isolation layer may be titanium nitride.
In this embodiment, the contact spacer 371 may encapsulate the contact metal 372.
In the embodiment of the application, a metal gate is prepared by depositing a metal gate material on a substrate with a gate trench, wherein the gate trench is provided with a bottom surface and a side surface, the normal direction of the bottom surface of the gate trench is a first direction, the normal direction of the side surface of the gate trench is a second direction, during the process of depositing the metal gate material, the deposition amount of the metal gate material along the first direction is controlled to be larger than the deposition amount along the second direction, so that the surface of the metal gate prepared by using the deposition process is provided with a groove, the groove is also provided with the bottom surface and the side surface, and then a gate contact structure is prepared on one side of the metal gate far from the substrate, so that the contact surface between the gate contact structure and the metal gate is increased from the bottom surface of the gate contact structure to the bottom surface and the side surface of the groove of the metal gate surface.
It will be appreciated that the specific examples of the application are intended to aid those skilled in the art in better understanding the embodiments of the application and are not intended to limit the scope of the application.
It should be understood that, in various embodiments of the present application, the sequence number of each process does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
It will be appreciated that the various embodiments described in the present application may be implemented either alone or in combination, and that the embodiments of the present application are not limited in this regard.
Unless defined otherwise, all technical and scientific terms used in the embodiments of the application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In the several embodiments provided by the present application, it should be understood that the disclosed semiconductor structure and CMOS device may be implemented in other ways. For example, the embodiments of semiconductor structures and CMOS devices described above are merely illustrative.
The foregoing is merely illustrative of embodiments of the present application, and the present application is not limited thereto, and any person skilled in the art will readily appreciate variations and substitutions within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (12)
1. A semiconductor structure, comprising:
A substrate;
The metal grid electrode is formed on the substrate, wherein the surface of the metal grid electrode is provided with a groove, and the groove extends along the surface of the metal grid electrode away from the substrate and towards the direction close to the substrate;
And the grid contact structure is formed on one side of the metal grid far away from the substrate, wherein the grid contact structure is contacted with the bottom surface and the side surface of the groove.
2. The semiconductor structure of claim 1, wherein the extending direction of the groove is a depth of the groove and a height direction of the metal gate, and a ratio of the depth of the groove to the height of the metal gate falls within a range of 1:4-2:5 along the extending direction of the groove.
3. The semiconductor structure of claim 1, wherein the recess includes a gap portion and a contact portion in contact with the gate contact structure, the semiconductor structure further comprising:
the gate contact structure is in contact with the contact part through the dielectric layer opening, and an air gap is formed between the gap part and the interlayer dielectric layer.
4. A method of manufacturing a semiconductor structure, the method comprising:
Providing a substrate, wherein the substrate is provided with a gate groove, the gate groove is provided with a bottom surface and a side surface, the normal direction of the bottom surface of the gate groove is a first direction, and the normal direction of the side surface of the gate groove is a second direction;
Depositing a metal gate material on the substrate, and forming a metal gate with a groove on the surface in the gate trench, wherein the deposition amount of the metal gate material along the first direction is larger than the deposition amount along the second direction;
And forming a gate contact structure on one side of the metal gate away from the substrate, wherein the gate contact structure is contacted with the bottom surface and the side surface of the groove.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein the recess has a recess depth along an extension direction of the recess, the step of providing a substrate comprising:
Providing a substrate, wherein the substrate comprises an NMOS region and a PMOS region;
Forming a dielectric layer on the substrate, wherein the distance between the surface of the dielectric layer away from the substrate and the substrate is not smaller than a specified value, and the specified value is the sum of a gate base height value and a groove depth value;
etching the dielectric layer, and forming an NMOS dielectric layer opening and a PMOS dielectric layer opening in the dielectric layer corresponding to the NMOS region and the PMOS region;
forming an NMOS gate dielectric layer and an NMOS dummy gate in the NMOS dielectric layer opening, and forming a PMOS gate dielectric layer and a PMOS dummy gate in the PMOS dielectric layer opening, wherein the distance between the surface of the NMOS dummy gate and the surface of the PMOS dummy gate, which are far away from the substrate, and the substrate is equal to the distance between the surface of the dielectric layer, which is far away from the substrate, and the substrate;
removing the NMOS dummy gate and the PMOS dummy gate to obtain a transition substrate with a gate transition groove;
And sequentially forming an etching stop layer and a metal work function layer on the surface of the transition substrate to obtain the substrate with the grid groove.
6. The method of claim 4, wherein depositing a metal gate material on the substrate, forming a metal gate having a recess on a surface in the gate trench, comprises:
depositing a metal gate material on the substrate to obtain a metal gate material layer formed on the surface of the substrate and the bottom and side surfaces of the gate trench, wherein the metal gate material layer comprises a flat part formed on the surface of the substrate, a trench bottom formed on the bottom surface of the gate trench and a trench side part formed on the side surface of the gate trench;
Filling the metal gate trench;
And carrying out planarization treatment, and forming a metal gate with a groove on the surface and a filling part in the gate groove, wherein the filling part is contacted with the bottom surface and the side surface of the groove.
7. The method of claim 6, wherein depositing a metal gate material on the substrate results in a metal gate material layer formed on a surface of the substrate and on bottom and sides of the gate trench, comprising:
Performing first deposition to obtain a first metal gate material layer formed on the surface of the substrate and the bottom surface and the side surface of the gate trench, wherein the first metal gate material layer comprises a first flat part formed on the surface of the substrate, a first trench bottom formed on the bottom surface of the gate trench and a first trench side part formed on the side surface of the gate trench;
And performing second deposition to obtain a second metal gate material layer formed on the surface of the first flat part and the surface of the bottom of the first groove, wherein the second metal gate material layer comprises a second flat part formed on the surface of the first flat part and a second groove bottom formed on the bottom of the first groove, the thickness of the second flat part along the first direction is equal to the thickness of the bottom of the second groove along the first direction, and the metal gate groove is formed among the second flat part, the second groove bottom and the side part of the first groove.
8. The method of claim 6, wherein depositing a metal gate material on the substrate results in a metal gate material layer formed on a surface of the substrate and on bottom and sides of the gate trench, comprising:
and performing third deposition to obtain a third metal gate material layer formed on the surface of the substrate and the bottom surface and the side surface of the gate trench, wherein the third metal gate material layer comprises a third flat part formed on the surface of the substrate, a third trench bottom formed on the bottom surface of the gate trench and a second trench side part formed on the side surface of the gate trench, the thickness of the third flat part along the first direction is equal to the thickness of the third trench bottom along the first direction, the thickness of the third flat part along the first direction is larger than the thickness of the second trench side part along the second direction, the metal gate trench is formed among the third flat part, the third trench bottom and the second trench side part, and the ratio of the rate of depositing the metal gate material along the first direction to the rate of depositing the metal gate material along the second direction falls into the range of 24:1-26:1 in the third deposition process.
9. The method of manufacturing a semiconductor structure according to any one of claims 6 to 8, wherein the recess includes a contact portion that contacts the gate contact structure, the method further comprising, prior to the step of forming the gate contact structure on a side of the metal gate that is remote from the substrate:
forming an interlayer dielectric layer on the metal gate;
And removing the interlayer dielectric layer and the filling part corresponding to the contact part, so that a dielectric layer opening corresponding to the contact part is formed in the interlayer dielectric layer, and the grid contact structure is contacted with the contact part through the dielectric layer opening.
10. The method according to claim 9, wherein the step of removing the interlayer dielectric layer and the filling portion corresponding to the contact portion so that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion, in the case where materials of the interlayer dielectric layer and the filling portion are the same, comprises:
And etching and removing the interlayer dielectric layer and the filling part corresponding to the contact part based on specified etching process parameters, so that a dielectric layer opening corresponding to the contact part is formed on the interlayer dielectric layer, wherein the interlayer dielectric layer and the filling part corresponding to the contact part are removed in the same process step.
11. The method according to claim 9, wherein the recess further includes a gap portion, and wherein the step of removing the interlayer dielectric layer and the filling portion corresponding to the contact portion such that the interlayer dielectric layer forms a dielectric layer opening corresponding to the contact portion, comprises:
Etching and removing the interlayer dielectric layer corresponding to the contact part based on the appointed etching process parameters;
And removing the filling part, so that a dielectric layer opening corresponding to the contact part is formed in the interlayer dielectric layer, and an air gap is formed between the gap part and the interlayer dielectric layer.
12. A CMOS device comprising a semiconductor structure according to any one of claims 1 to 3 or a semiconductor structure manufactured according to the method of manufacturing a semiconductor structure according to any one of claims 4 to 11.
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| CN105428237A (en) * | 2014-08-28 | 2016-03-23 | 中芯国际集成电路制造(上海)有限公司 | Negative metal oxide transistor (NMOS) transistor and forming method thereof |
| US20160141417A1 (en) * | 2014-11-19 | 2016-05-19 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN108074820A (en) * | 2016-11-10 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN114551597A (en) * | 2020-11-26 | 2022-05-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105428237A (en) * | 2014-08-28 | 2016-03-23 | 中芯国际集成电路制造(上海)有限公司 | Negative metal oxide transistor (NMOS) transistor and forming method thereof |
| US20160141417A1 (en) * | 2014-11-19 | 2016-05-19 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
| CN108074820A (en) * | 2016-11-10 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN114551597A (en) * | 2020-11-26 | 2022-05-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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