CN119357107B - Channel synchronous switching method in large-scale matrix switch based on asynchronous bus - Google Patents
Channel synchronous switching method in large-scale matrix switch based on asynchronous busInfo
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- CN119357107B CN119357107B CN202411373573.9A CN202411373573A CN119357107B CN 119357107 B CN119357107 B CN 119357107B CN 202411373573 A CN202411373573 A CN 202411373573A CN 119357107 B CN119357107 B CN 119357107B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The invention relates to a channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus, which is characterized in that a NOR gate is added in a control circuit of a matrix board card to construct an RS422 bus and SPI hardware bus circuit containing synchronous switching control enabling, matrix equipment sends I/O data to the matrix board card through the RS422 bus, the matrix board card receives the I/O data, and the matrix equipment sends a switching preparation/synchronous switching command through the RS422 bus, and the matrix board card opens synchronous switching control enabling or closes synchronous switching control enabling. By adding special logic control, the synchronous switching of the switches of a plurality of matrix boards under a plurality of asynchronous microprocessors is realized by utilizing the rising edge of the data start bit of the serial RS422 bus and synchronous switching control enabling cooperative control, the routing switching time of a large-scale matrix is improved from us level to ns level, and the signal receiving demodulation is not influenced when the large-scale matrix switch is switched in channel routing, so that the channel is lossless and noninductive.
Description
Technical Field
The invention belongs to the technical field of large-scale radio frequency signal shunt switching and synchronous control of microwave switching circuits, and particularly relates to a channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus.
Background
The large-scale radio frequency switch matrix consists of dozens of medium-and small-scale matrix boards, each matrix board comprises a plurality of switches and power dividing units capable of absorbing and switching off, a large number of switch circuits are contained, each switch needs 1 or more I/O controls, for an M multiplied by N matrix board, at least 2*M multiplied by N I/O controls are needed, if the matrix is constructed by adopting 16 multiplied by 16 boards, the number of boards and the number of I/O are as follows:
| Sequence number | Matrix size | Number of boards | I/O quantity |
| 1 | 64×64 | 12 | 3072 |
| 2 | 128×128 | 24 | 6144 |
| 3 | 256×256 | 48 | 9216 |
Because the I/O of the singlechip is limited, serial-to-parallel chips are adopted in the prior art to be required to be expanded, SPI serial control is carried out, and only 3 control lines, namely DATA DATA, a clock CLK and an enable EN are needed, and after the DATA input is finished, the DATA can be simultaneously turned over and latched by one time through serial DATA input.
In the matrix board, I/O DATA are sequentially shifted into memories of all serial-parallel chips through serial DATA DATA and clock CLK, enable EN high level is controlled, and meanwhile the I/O DATA in the memories are turned over and output, so that synchronous switching of all switches is realized. For large-scale matrices, multiple matrix cards are required, the control of which employs an RS422 bus. The integrated machine microprocessor respectively sends the I/O data of all the boards to each board through the RS422 bus, the board microprocessor sequentially sends the I/O data of the boards to the serial-parallel memory through the SPI, but does not turn over immediately, and after receiving a synchronous switching instruction sent by the matrix main control microprocessor, the integrated machine microprocessor controls enabling EN to turn over to realize synchronous switching of all switches of the integrated machine.
In the synchronous switching mode, the clocks of the microprocessors of the boards are not synchronous, so that the interrupt of the received serial port RX and the execution interrupt are different in time sequence, and the synchronous error is about 5 us～10us. When the route is changed, the complete channel of the card-inserted radio frequency matrix relates to a plurality of boards, and the switching synchronization time error causes 5 us～10us signal interruption, which can cause 1 or more code elements to be lost even signal lock loss when the channel receives high-speed modulation signals.
Therefore, how to improve the synchronous switching method of the large-scale radio frequency signal shunt switching and the microwave switching circuit in the prior art, to realize the synchronous switching of the switches of a plurality of matrix boards under a plurality of asynchronous microprocessors, and to improve the routing switching time of a large-scale matrix from us level to ns level, thereby realizing the routing switching of the established channel, and the signal receiving demodulation channel is lossless and noninductive, which is the technical problem to be solved at present.
Disclosure of Invention
The invention aims to provide a channel synchronous switching method based on an asynchronous bus in a large-scale matrix switch, which improves the synchronous switching method of a large-scale radio frequency signal shunt switch and a microwave switch circuit in the prior art, realizes the switch synchronous switching of a plurality of matrix boards under a plurality of asynchronous microprocessors, and improves the routing switching time of a large-scale matrix from us level to ns level, thereby realizing the routing switching of an established channel, and ensuring that a signal receiving demodulation channel is lossless and noninductive.
In order to solve the technical problems, the invention adopts the following technical scheme:
A channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus comprises the following steps:
S1, adding a NOR gate logic control unit in a control circuit of a matrix board card to construct an RS422 bus and SPI hardware bus circuit containing synchronous switching control enabling;
s2, the matrix device sends I/O data to the matrix board card through the RS422 bus, and the matrix board card receives the I/O data and forwards the I/O data to the serial-parallel chip through the SPI for storage;
s3, the matrix equipment sends a switching preparation instruction through an RS422 bus, and after receiving the instruction, the matrix board card opens a synchronous switching control enabling switch;
And S4, the matrix equipment sends a synchronous switching instruction through the RS422 bus, and the synchronous switching control enabling switch is turned off after the matrix board card receives the command by utilizing the rising edge of the start bit of the serial RS422 bus data to realize the synchronous I/O turning of all HC595 chips of all board cards.
Preferably, the control circuit of the matrix board with a nor gate in step S1 includes a board microprocessor, a serial-parallel chip, a serial-port chip and an RS422 bus, where the serial-parallel chip is provided with a plurality of serial-parallel chips, the board microprocessor is connected with the serial-parallel chips, the board microprocessor is also connected with the serial-port chip, the nor gate is respectively connected with the board microprocessor, the serial-parallel chip and the serial-port chip, the RS422 bus is connected with the serial-port chip, and the serial-parallel chip is HC595.
Preferably, in the control circuit of the matrix board, when EN '=1 is enabled, RX generated by the RS422 bus data is changed, enabling EN is always 0, so that the stored data of the HC595 chip cannot be inverted to output, and when EN' =0 is enabled, RX generated by the RS422 bus data is enabled, and only if rx=0, en=1 is enabled, and the stored data of the serial-parallel chip HC595 chip is inverted to output.
Preferably, when the matrix is a large-scale matrix, the card-inserting matrix bus control circuit comprises a matrix board card, a serial port chip, a whole machine microprocessor and a network port chip, wherein the network port chip is connected with the whole machine microprocessor, the whole machine microprocessor is connected with the serial port chip, a plurality of matrix board cards are arranged, and the serial port chip is connected with a plurality of matrix board cards through RS422 buses respectively.
Preferably, the specific procedure of step S2 is as follows:
S21, when the matrix needs route switching, screening and searching matrix boards needing I/O change, sequentially sending I/O control data to the matrix boards needing I/O change through an RS422 bus, judging whether to send the I/O control data to all the matrix boards, if so, executing a step S22, and if not, continuously sending the I/O control data to the matrix boards needing I/O change through the RS422 bus;
s22, sending a switching preparation instruction to all matrix boards, and after time delay is designated, sending a synchronous switching instruction to all matrix boards again.
Preferably, step S3 includes the following specific procedures:
s31, starting a matrix board program, setting enable EN' =1, circularly receiving instructions of an RS422 bus, judging the type of the instructions received by the matrix board, executing step S32 if the type of the instructions received by the matrix board is an I/O data instruction, and executing step S33 if the type of the instructions received by the matrix board is a switching preparation instruction;
s32, transmitting I/O data to the serial-parallel conversion chip through the SPI;
s33, setting enable EN' to 0;
and S34, setting the enable EN' to be 1.
Preferably, during the period that the enable EN' of the matrix board is 0, when the first 0 of RX appears, namely the initial bit in the serial protocol, the stored I/O data of the serial-parallel chip HC595 is immediately turned over and output, and when the I/O data is not changed, the switch is not switched, and the signal is not interrupted;
when the I/O data are changed, the switch has a switching action, all the matrix boards need to switch the switch to synchronously act, the channel signal is gradually disappeared and then gradually reappears, and the time of the process depends on the switching time of the radio frequency switch chip and is 50-150 ns.
Preferably, the nor gate logic control unit is a multiple-input nor gate logic control unit, and includes a plurality of input ends and 1 output end.
Preferably, the output terminal outputs a high level 1 when all inputs of the plurality of input terminals are low, and outputs a low level 0 when an input of one of the plurality of input terminals is high.
The beneficial effects of the invention include:
the channel synchronous switching method based on the asynchronous bus in the large-scale matrix switch comprises the steps of firstly adding a NOR gate logic control unit in a control circuit of a matrix board card to construct an RS422 bus and SPI hardware bus circuit containing synchronous switching control enabling, sending I/O data to the matrix board card by matrix equipment through the RS422 bus, forwarding the I/O data to a serial-to-parallel chip for storage through SPI, sending a switching preparation command by the matrix board card through the RS422 bus, opening the synchronous switching control enabling switch after the matrix board card receives the command, sending the synchronous switching command by the matrix equipment through the RS422 bus, utilizing the rising edge of the start bit of serial RS422 bus data to realize synchronous switching of all HC595 chips of all board cards, and closing the synchronous switching control enabling switch after the matrix board card receives the command.
By adding special logic control, the synchronous control is enabled by utilizing the rising edge of the start bit of serial RS422 bus data and a synchronous switching instruction, so that the synchronous switching of the switches of a plurality of matrix boards under a plurality of asynchronous microprocessors is realized, the routing switching time of a large-scale matrix is increased from us level to ns level, the routing switching of an established channel is further realized, and the signal receiving demodulation channel is lossless and noninductive.
Drawings
FIG. 1 is a schematic diagram showing the components of an I/O expansion control circuit in a matrix board card according to the prior art of the present invention.
Fig. 2 is a schematic diagram of a prior art card matrix bus control circuit according to the present invention.
FIG. 3 is a schematic diagram of the internal I/O expansion control circuit of the matrix board with the added NOR gate logic control of the present invention.
Fig. 4 is a schematic diagram of a synchronous switching flow of a card matrix according to the present invention.
Fig. 5 is a schematic diagram of a synchronous switching flow of a matrix board card according to the present invention.
Detailed Description
The invention is further described in detail below with reference to fig. 1 to 5:
Example 1
A channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus is characterized by comprising the following steps:
S1, adding a NOR gate logic control unit in a control circuit of a matrix board card, namely adding special logic control in the control circuit of the matrix board card, constructing a serial RS422 bus and SPI hardware bus circuit containing synchronous switching control enabling, and enabling cooperative control by utilizing the rising edge of the start bit of serial RS422 bus data and a synchronous switching instruction;
S2, when the matrix equipment needs to carry out route switching, screening and searching matrix board cards needing to change I/O data, sequentially sending the I/O data to all the matrix board cards by the matrix equipment through an RS422 bus, receiving the I/O data by the matrix board cards, and forwarding the I/O data to a serial-to-parallel chip through an SPI (serial peripheral interface) for storage;
s3, after the I/O data is sent, the matrix device sends a switching preparation instruction through an RS422 bus, and after receiving the instruction, the matrix board card opens a synchronous switching control enabling switch;
And S4, the matrix equipment sends a synchronous switching instruction through an RS422 bus, realizes the synchronous I/O turning of all HC595 chips of all boards by utilizing the rising edge of the start bit of serial RS422 bus data, realizes the synchronous switching of the switches of a plurality of matrix boards under a plurality of asynchronous microprocessors, and improves the routing switching time of a large-scale matrix from us level to ns level, thereby realizing the routing switching of the established channel, and ensuring that the signal receiving demodulation channel is lossless and noninductive. And after receiving the command, the matrix board card turns off the synchronous switching control enabling switch.
In the prior art, referring to fig. 1, in the matrix board, I/O DATA is sequentially shifted into memories of all serial-parallel chips through serial DATA and a clock CLK, and enable EN is controlled to be high level, and at the same time, the I/O DATA in the memories is turned over and output, so that synchronous switching of each switch is realized. The integrated machine microprocessor respectively sends the I/O data of all the boards to each board through the RS422 bus, the board microprocessor sequentially sends the I/O data of the boards to the serial-parallel memory through the SPI, but does not turn over immediately, and after receiving a synchronous switching instruction sent by the matrix main control microprocessor, the integrated machine microprocessor controls enabling EN to turn over to realize synchronous switching of all switches of the integrated machine. In the synchronous switching mode, the clocks of the microprocessors of the boards are not synchronous, the interrupt of the received serial port RX and the execution interrupt are different in time sequence, and the synchronous error is about 5 us-10 us. When the route is changed, the complete channel of the card-inserted radio frequency matrix relates to a plurality of boards, and the signal is interrupted by 5 us-10 us due to the switching synchronization time error, so that 1 or more code elements are lost when the channel receives a high-speed modulation signal, and even the signal is out of lock. For example, when the signal modulation rate is R (Bd), the symbol time T(s) is:
Symbol times for different modulation rates are as follows:
| Modulation rate (MBd) | 0.1 | 1 | 10 | 20 |
| Symbol time T (ns) | 10000 | 1000 | 100 | 50 |
| Symbol time T (us) | 10 | 1 | 0.1 | 0.05 |
The signal interruption time results in the following table of the number of lost symbols for different modulation rates:
As can be seen from the above table, for signals above 1MBd, the missing symbols reach hundreds, even resulting in demodulation loss of lock.
Therefore, in this embodiment, by adding special nor gate logic control in the control circuit of the matrix board, the rising edge of the start bit of the serial RS422 bus data and the synchronous switching instruction enable cooperative control, so as to realize the synchronous switching of the switches of a plurality of matrix boards under a plurality of asynchronous microprocessors, increase the routing switching time of a large-scale matrix from us level to ns level, and when the routing switching of the large-scale matrix is realized, the signal interruption time is about 50 ns-150 ns, the specific time depends on the switching time of the radio frequency switch chip, and the signal interruption time is increased by about 100 times, thereby realizing the loss of 0 code element of the modulation signal under 10 mbps for receiving and demodulating by the routing switching, and realizing the lossless switching, the noninductive signal receiving and demodulating channel and the noninductive signal receiving and demodulating channel of the established channel.
The NOR gate logic control unit is a multi-input NOR gate logic control unit and comprises a plurality of input ends and 1 output end. When the input of one of the plurality of input ends is high level, the output end outputs low level 0.
Example 2
Referring to fig. 3, based on embodiment 1, the control circuit of the matrix board in step S1, which is added with a nor gate logic control, includes a board microprocessor, serial-parallel chips, serial-port chips and an RS422 bus, where the serial-parallel chips are provided with a plurality of serial-parallel chips, and the serial-parallel chips are of the model HC595. The board card microprocessor is connected with a plurality of serial-to-parallel chips through serial DATA DATA and CLK all the time, the signal input end of the board card microprocessor is connected with the signal output end of the serial-to-parallel chip, the logic control unit of the NOR gate is respectively connected with the board card microprocessor, the serial-to-parallel chip and the serial-to-parallel chip, and the RS422 bus is connected with the serial-to-parallel chip. In the matrix board, I/O DATA are sequentially shifted into memories of all serial-parallel chips through serial DATA DATA and clock CLK, EN high level is controlled and enabled, meanwhile, the I/O DATA in the memories are overturned and output, special logic control is added in a control circuit of the matrix board, and synchronous switching of a plurality of matrix boards under a plurality of asynchronous microprocessors is realized by utilizing the rising edge of the starting bit of serial RS422 bus DATA and synchronous switching instruction enabling cooperative control.
In the control circuit of the matrix board, when EN '=1 is enabled, RX generated by the RS422 bus data changes, enabling EN is always 0, and the stored data of the HC595 chip cannot be turned over to output, and when EN' =0 is enabled, RX generated by the RS422 bus data is enabled, and only if rx=0, en=1 is enabled, and the stored data of the serial-parallel chip HC595 chip is turned over to output.
The logic relationship of the control circuit of the matrix board is shown in the following table:
| Sequence number | EN’ | RX | EN |
| 1 | 1 | x | 0 |
| 2 | 0 | 1 | 0 |
| 3 | 0 | 0 | 1 |
As can be seen from the above table, when EN ' =1, no matter RX is 0 or 1, EN ' is 0, and EN ' =0, the control circuit of the matrix board realizes the function of en=/RX that when EN ' =1, RX generated by RS422 bus data changes, EN is always 0, and the stored data of HC595 chip is not inverted to output, and when EN ' =0, RX generated by RS422 bus data is inverted to output, and when rx=0, en=1, and stored data of hc595 chip are inverted to output.
When the matrix is a large-scale matrix, referring to fig. 2, the card-inserting matrix bus control circuit comprises a matrix board card, a serial port chip, a whole machine microprocessor and a network port chip, wherein the network port chip is connected with the whole machine microprocessor, the whole machine microprocessor is connected with the serial port chip, a plurality of matrix board cards are arranged, and the serial port chip is connected with a plurality of matrix board cards through an RS422 bus respectively.
Example 3
Referring to fig. 4, on the basis of example 1, the specific procedure of step S2 is as follows:
S21, when the matrix needs route switching, screening and searching matrix boards needing I/O change, sequentially sending I/O control data to the matrix boards needing I/O change through an RS422 bus, judging whether to send the I/O control data to all the matrix boards, if so, executing a step S22, and if not, continuously sending the I/O control data to the matrix boards needing I/O change through the RS422 bus;
S22, sending a switching preparation instruction to all matrix boards, and then further sending a synchronous switching preparation instruction to all matrix boards at a time designated by time delay.
Example 4
Referring to fig. 5, on the basis of embodiment 1, step S3 includes the following specific procedures:
s31, starting a matrix board program, setting enable EN' =1, circularly receiving instructions of an RS422 bus, judging the type of the instructions received by the matrix board, executing step S32 if the type of the instructions received by the matrix board is an I/O data instruction, and executing step S33 if the type of the instructions received by the matrix board is a switching preparation instruction;
s32, transmitting I/O data to the serial-parallel conversion chip through the SPI;
s33, setting enable EN' to 0;
and S34, setting the enable EN' to be 1.
In the above scheme, after the matrix board program is started, enable EN ' is set to 1, the instruction of the bus is circularly received, the instruction type received by the board is judged, if the instruction is an "I/O data" instruction, the I/O data is sent to the serial-parallel conversion chip through the SPI, if the instruction is a "switch preparation" instruction, enable EN ' is set to 0, and if the instruction is a "synchronous switch" instruction, enable EN ' is set to 1.
During the period that the enable EN' of the matrix board is 0, when the first 0 of RX appears, namely the initial bit in the serial protocol, the stored I/O data of the serial-parallel chip HC595 is immediately turned over and output, and when the I/O data is not changed, the switch is not switched, and the signal is not interrupted. When the I/O data are changed, the switch has a switching action, all the matrix boards need to switch the switch to synchronously act, the channel signal is gradually disappeared and then gradually reappears, and the time of the process depends on the switching time of the radio frequency switch chip and is 50-150 ns.
The number of lost symbols for signals at different modulation rates caused by signal interruption times in this embodiment is as follows:
From the table above, it can be seen that for the signals with the rate below 1MBd, the number of lost symbols is less than 1, for the signals with the rate below 20MBd, the number of lost symbols is at most 3, the signals are not out of lock yet, and the lost symbols can be recovered through the error recovery mechanism of the signals, so that the technical problems that for the signals with the rate above 1MBd, the number of lost symbols reaches hundreds, and even demodulation out of lock is caused in the prior art are solved. By adding special logic control, the synchronous control is enabled by utilizing the rising edge of the start bit of serial RS422 bus data and a synchronous switching instruction, so that the synchronous switching of the switches of a plurality of matrix boards under a plurality of asynchronous microprocessors is realized, the routing switching time of a large-scale matrix is increased from us level to ns level, the routing switching of an established channel is further realized, and the signal receiving demodulation channel is lossless and noninductive.
In summary, the channel synchronous switching method based on the asynchronous bus in the large-scale matrix switch provided by the invention comprises the steps of adding a NOR gate logic control unit in a control circuit of a matrix board card to construct an RS422 bus and SPI hardware bus circuit containing synchronous switching control enabling, sending I/O data to the matrix board card by matrix equipment through the RS422 bus, receiving the I/O data by the matrix board card, forwarding the I/O data to a serial-parallel chip through SPI for storage, sending a synchronous switching preparation instruction by the matrix equipment through the RS422 bus, opening the synchronous switching control enabling switch by the matrix board card, and sending a synchronous switching instruction by the matrix equipment through the RS422 bus, and closing the synchronous switching control enabling switch by the matrix board card. By adding special logic control, the synchronous control is enabled by utilizing the rising edge of the start bit of serial RS422 bus data and a synchronous switching instruction, so that the synchronous switching of the switches of a plurality of matrix boards under a plurality of asynchronous microprocessors is realized, the routing switching time of a large-scale matrix is increased from us level to ns level, the routing switching of an established channel is further realized, and the signal receiving demodulation channel is lossless and noninductive.
The above examples merely illustrate specific embodiments of the application, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that it is possible for a person skilled in the art to make several variants and modifications without departing from the technical idea of the application, which fall within the scope of protection of the application.
Claims (9)
1. A channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus is characterized by comprising the following steps:
S1, adding a NOR gate logic control unit in a control circuit of a matrix board card to construct an RS422 bus and SPI hardware bus circuit containing synchronous switching control enabling;
s2, when the matrix equipment needs route switching, the matrix equipment sends I/O data to a matrix board card through an RS422 bus, and the matrix board card receives the I/O data and forwards the I/O data to a serial-parallel chip through an SPI (serial peripheral interface) for storage;
S3, the matrix equipment sends a switching preparation instruction through an RS422 bus, and the matrix board card receives the instruction and opens a synchronous switching control enabling switch;
And S4, the matrix equipment sends a synchronous switching command through the RS422 bus, and utilizes the rising edge of the start bit of serial RS422 bus data to realize the I/O synchronous turning of all 595 chips of all boards, and the matrix board receives a command and turns off a synchronous switching control enabling switch.
2. The method for synchronously switching channels in a large-scale matrix switch based on an asynchronous bus according to claim 1, wherein the control circuit of the matrix board added with a nor gate in step S1 comprises a board microprocessor, serial-parallel chips, serial-port chips and an RS422 bus, wherein the serial-parallel chips are provided with a plurality of serial-parallel chips, the board microprocessor is connected with the serial-port chips, the nor gate is respectively connected with the board microprocessor, the serial-parallel chips and the serial-port chips, the RS422 bus is connected with the serial-port chips, and the serial-parallel chips are HC595.
3. The method for channel synchronous switching in a large-scale matrix switch according to claim 2, wherein in the control circuit of the matrix board, when EN '=1 is enabled, RX generated by RS422 bus data is changed, EN is enabled to be 0 all the time, the stored data of HC595 chip is not turned over to output, when EN' =0 is enabled, RX generated by RS422 bus data is enabled, en=1 is enabled as long as rx=0, and the stored data of the serial-parallel chip HC595 chip is turned over to output.
4. The method for synchronously switching channels in a large-scale matrix switch based on an asynchronous bus according to claim 2, wherein when the matrix is a large-scale matrix, the card-inserting matrix bus control circuit comprises a matrix board card, a serial port chip, a whole machine microprocessor and a network port chip, wherein the network port chip is connected with the whole machine microprocessor, the whole machine microprocessor is connected with the serial port chip, a plurality of matrix board cards are arranged, and the serial port chip is connected with a plurality of matrix board cards through an RS422 bus respectively.
5. The method for channel synchronous switching in a large-scale matrix switch based on an asynchronous bus according to claim 1, wherein the specific process of step S2 is as follows:
S21, when the matrix needs route switching, screening and searching matrix boards needing I/O change, sequentially sending I/O control data to the matrix boards needing I/O change through an RS422 bus, judging whether to send the I/O control data to all the matrix boards, if so, executing a step S22, and if not, continuously sending the I/O control data to the matrix boards needing I/O change through the RS422 bus;
S22, sending a switching preparation instruction to all matrix boards, and after time delay is designated, sending a synchronous switching instruction to all matrix boards again;
s23, forwarding the serial-parallel conversion data to a serial-parallel conversion chip through the SPI for storage.
6. The method for channel synchronous switching in a large-scale matrix switch based on an asynchronous bus according to claim 5, wherein step S3 comprises the following specific procedures:
s31, starting a matrix board program, setting enable EN' =1, circularly receiving instructions of an RS422 bus, judging the type of the instructions received by the matrix board, executing step S32 if the type of the instructions received by the matrix board is an I/O data instruction, and executing step S33 if the type of the instructions received by the matrix board is a switching preparation instruction;
s32, transmitting I/O data to the serial-parallel conversion chip through the SPI;
s33, setting enable EN' to 0;
and S34, setting the enable EN' to be 1.
7. The method for channel synchronous switching in a large-scale matrix switch based on an asynchronous bus according to claim 1, wherein during the period when enable EN' of a matrix board is 0, when the first 0 of RX occurs, namely, the start bit in a serial protocol, the stored I/O data of the serial-parallel chip HC595 is immediately flipped and outputted, and when the I/O data is not transformed, the switch is not switched, and the signal is not interrupted;
when the I/O data are changed, the switch has a switching action, all the matrix boards need to switch the switch to synchronously act, the channel signal is gradually disappeared and then gradually reappears, and the time of the process depends on the switching time of the radio frequency switch chip and is 50-150 ns.
8. The method for channel synchronous switching in a large-scale matrix switch based on an asynchronous bus according to claim 1, wherein the nor gate logic control unit is a multiple-input nor gate logic control unit, and comprises a plurality of input terminals and 1 output terminal.
9. The method of claim 8, wherein the output outputs a high level 1 when all inputs of the plurality of inputs are low, and outputs a low level 0 when one of the plurality of inputs is high.
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| CN202111685U (en) * | 2011-05-23 | 2012-01-11 | 博世汽车部件(苏州)有限公司 | Extensible switch matrix plate |
| CN102664622A (en) * | 2012-02-29 | 2012-09-12 | 哈尔滨工业大学 | Control system and method of matrix switch supportive of four working modes |
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| KR19990002727A (en) * | 1997-06-23 | 1999-01-15 | 유기범 | Space switch and link part test method in electronic exchange |
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| CN202111685U (en) * | 2011-05-23 | 2012-01-11 | 博世汽车部件(苏州)有限公司 | Extensible switch matrix plate |
| CN102664622A (en) * | 2012-02-29 | 2012-09-12 | 哈尔滨工业大学 | Control system and method of matrix switch supportive of four working modes |
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