CN119356060A

CN119356060A - A time measurement device based on pulse modulation and fine and rough timing

Info

Publication number: CN119356060A
Application number: CN202411806665.1A
Authority: CN
Inventors: 付在明; 邓禹杰
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2024-12-10
Filing date: 2024-12-10
Publication date: 2025-01-24

Abstract

The present invention belongs to the field of time measurement, and provides a time measurement device based on pulse modulation and fine and rough timing, which is used to solve the problem that the existing time measurement device cannot meet the application requirements such as large measurement range, good nonlinear error and low resource consumption. The present invention outputs the same frequency modulated pulse and clock signal to FPGA through an external modulation pulse generation module; FPGA receives START signal and STOP signal, and the START signal and STOP signal are input to the delay chain module as triggers, and the information of the modulated pulse signal on the delay chain is intercepted as fine timing data, and the START signal and STOP signal are input to the counter module as switch signals to count the rising edge of the clock signal as rough timing data, and finally the fine timing data and the rough timing data are decoded and calculated by the decoding module to obtain the time measurement result; in summary, the present invention adopts a structure of multiple measurements of a single time, improves the nonlinear error performance, and achieves the measurement effect of multiple measurements based on a single delay chain.

Description

Time measuring device based on pulse modulation and fine rough timing

Technical Field

The invention relates to a time measuring device, in particular to a time measuring device based on pulse modulation and fine rough timing, which is suitable for various application fields such as sensor signal processing, measuring instruments, automatic control systems and the like.

Background

Time measurement devices are key components of many electronic systems and industrial products, such as all-digital phase locked loops, time-of-flight mass spectrometers, and lidar or 3D ranging devices for robotic, autopilot, and solar photovoltaic deployment optimization, modern time measurement designs and implementations are heterogeneous, multidirectional, driven by CMOS (semiconductor) process degradation and application requirements, a great deal of research effort focused on denser digital implementations, high resolution technology optimization, increased input range and linearity, reduced conversion time, power consumption, and silicon area, and design technologies for thermal and mismatch resistance, and PVT (process voltage temperature) variation resistance and migration resistance are becoming increasingly important in order to alleviate the shortcomings of nanoscale CMOS technology.

Currently, the time measurement device mainly adopts a direct counting structure and a delay chain architecture. Under the direct counting structure, the simplest time interval measurement scheme in the time measurement device is realized by a counter, the counter is directly triggered or sampled by a signal to be measured, if the direct counting structure is required to realize high-resolution measurement, a stable high-frequency clock must be provided for a subdivision module, however, the current ultrahigh-frequency clock cannot be stably realized in a full-digital circuit, and the existing manufacturing process and technology also cannot support the development of the counter with such high turnover speed, so that the counter is generally used in a time measurement system to finish rough time measurement and can be used for expanding the dynamic range of measurement. Under the delay chain architecture, physical propagation delay units of predefined logic resources in FPGA equipment are adopted as basic components for realizing fine time measurement, the number of fixed delay units which are passed by an input signal in the propagation process can be determined according to sampling results, so that the measurement interval between a START edge and a STOP edge is obtained, however, the propagation delay of each logic unit in the FPGA is inconsistent due to the influences of technology, voltage and temperature, so that the size distribution of the delay units is uneven, and therefore, in order to meet the specific requirements of different applications on the time resolution, precision and linearity of the delay chain architecture, the architecture of a traditional delay chain must be improved, so that the measurement range is enlarged and nonlinear errors are compensated.

In summary, since the two architectures have advantages, even if the direct counting structure and the delay chain architecture are combined to obtain a higher measurement range and measurement accuracy, the delay chain architecture still has the problem of uneven size distribution of the delay units, so that nonlinear errors still exist, and in addition, the method of taking the average value by measuring a plurality of times by adopting a plurality of delay chain architectures can solve the problem, but the method can cause great burden on the resource occupation caused by the FPGA, so that a time measurement device with large measurement range, high resolution, good nonlinear errors and less consumption of resources is needed.

Disclosure of Invention

The invention aims to provide a time measuring device based on pulse modulation and fine rough timing, which is used for solving the problems that the existing time measuring device cannot meet the application requirements of large measuring range, good nonlinear error, less consumed resources and the like.

In order to achieve the above purpose, the invention adopts the following technical scheme:

a time measuring device based on pulse modulation and fine rough timing comprises a pulse modulation generation module, a delay chain module, a counter module and a decoding module, and is characterized in that:

the pulse modulation generation module is used for generating modulation pulses and clock signals and inputting the modulation pulses and the clock signals into the delay chain module and the counter module, wherein the multi-pulse period of the modulation pulses is consistent with the clock period of the clock signals;

The delay chain module is used for receiving the modulation pulse, taking the START signal and the STOP signal as triggers, respectively intercepting waveform data of the modulation pulse on the delay chain as fine timing data, and outputting the fine timing data to the decoding module;

the counter module is used for receiving the clock signal, counting the rising edge of the clock by taking the START signal and the STOP signal as switching signals, taking the counting result as rough timing data and outputting the rough timing data to the decoding module;

and the decoding module is used for receiving and decoding the fine timing data and the coarse timing data, and calculating to obtain the measurement time information.

Further, in the pulse modulation generating module, the modulation pulse is a multi-pulse periodic signal, and the widths of each positive pulse and each negative pulse in the multi-pulse period are different.

Further, in the delay chain module, the START signal and the STOP signal are used as triggers, and the clock period before the trigger time is used as a interception period, so that waveform data of the modulation pulse on the delay chain in the interception period is obtained and used as fine timing data.

Further, in the counter block, the clock rising edge is counted until the first clock rising edge after the STOP signal.

Further, in the decoding module, the decoding process of the coarse timing data is as follows:

TC=N×T,

Where TC represents the coarse timing time length, T represents the clock period, and N represents the count result of the rising edge of the clock.

Further, in the decoding module, the decoding process of the fine timing data is as follows:

For START signal triggering or STOP signal triggering, arbitrarily selecting a single pulse as a characteristic pulse in a multi-pulse period of the modulation pulse, taking a rising edge or a falling edge of any modulation pulse in a interception period as a measurement edge, and for a jth measurement edge:

wherein TA represents the time length from the START signal trigger time to the first clock rising edge thereafter, TA ^j represents the time length from the START signal trigger time to the first clock rising edge thereafter based on the jth measurement edge, TB represents the time length from the STOP signal trigger time to the first clock rising edge thereafter, TB ^j represents the time length from the STOP signal trigger time to the first clock rising edge thereafter based on the jth measurement edge, M _A and M _B represent the number of measurement edges in the corresponding cut-out period, TE _A and TE _B represent the delay time length of the clock rising edge relative to the characteristic pulse in the corresponding cut-out period, And (3) withRepresenting the length of delay time of the jth measured edge relative to the characteristic pulse in the corresponding clipping period,And (3) withThe number of delay units transmitted by the jth measuring edge on the delay chain in the corresponding intercepting period is represented, T represents the clock period, and Tr represents the time length of the delay units on the delay chain.

Further, in the decoding module, the calculation process of the measurement time information is as follows:

TIME=TA+TC-TB,

wherein TIME represents measurement TIME information, TC represents a rough timing TIME length, TA represents a TIME length from a START signal trigger TIME to a first clock rising edge thereafter, and TB represents a TIME length from a STOP signal trigger TIME to a first clock rising edge thereafter.

Based on the technical scheme, the invention has the beneficial effects that:

the invention provides a time measuring device based on pulse modulation and fine rough timing, which outputs the same-frequency modulation pulse and clock signal to an FPGA through an external modulation pulse generation module, wherein the FPGA receives a START signal and a STOP signal, inputs the START signal and the STOP signal to a delay chain module as trigger, intercepts the information of the modulation pulse signal on the delay chain as fine timing data, inputs the START signal and the STOP signal to a counter module as a switch signal to count the rising edge of the clock signal as rough timing data, and finally decodes and calculates the fine timing data and the rough timing data through a decoding module to obtain a measuring result, namely time information;

In summary, the invention realizes coarse timing through the counter module to provide time measurement with wide measurement range, realizes fine timing through the delay chain to improve the resolution of time measurement, adopts a structure of single time and multiple times of measurement in the fine timing process, improves the nonlinear error performance of measurement, achieves the measurement effect of multiple times of measurement based on the single delay chain, saves a large amount of FPGA resources, and can realize multichannel time measurement.

Drawings

FIG. 1 is a schematic block diagram of a time measuring device based on pulse modulation and fine rough timing in the present invention.

Fig. 2 is a schematic diagram of a fine timing data calculation principle of a time measurement device based on pulse modulation and fine coarse timing in the present invention.

Fig. 3 is a signal diagram generated by a modulation pulse generating module of the time measuring device according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of time measurement of a time measurement device based on pulse modulation and fine rough timing according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantageous effects of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and examples, and it should be noted that the described examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without making any inventive effort based on the examples of the present invention are included in the scope of the present invention.

The embodiment provides a time measuring device based on pulse modulation and fine rough timing, the principle framework of which is shown in fig. 1, and the time measuring device specifically comprises a pulse modulation generating module, a delay chain module, a counter module and a decoding module, wherein the following detailed description of each module is provided:

The pulse modulation generation module is used for generating modulation pulses and clock signals and inputting the modulation pulses and the clock signals into the FPGA, and respectively taking the modulation pulses and the clock signals as references for the delay chain module and the counter module, wherein the multi-pulse period of the modulation pulses is consistent with the clock period of the clock signals, and the modulation pulses modulate time and output pulse strings with pulse widths related to the time;

the delay chain module adopts an FPGA internal resource CARRY4 to form a delay chain, and is used for receiving the modulation pulse generated by the pulse modulation generating module, taking a START signal and a STOP signal as triggers, intercepting waveform DATA of the modulation pulse on the delay chain as fine timing DATA DATA _TF, and outputting the fine timing DATA to the decoding module;

The counter module is used for receiving the START signal and the STOP signal as gate signals, counting rising edges of the clock signals, and outputting a counting result to the decoding module as rough timing DATA DATA _TC;

The decoding module receives the fine timing DATA _TF and the coarse timing DATA _TC, decodes the two DATA, and calculates the measurement TIME information TIME.

In terms of working principle:

The invention adopts a counter module to realize rough timing to obtain rough timing DATA, takes a START signal and a STOP signal as gate signals when coming, counts rising edges of the clock signals, counts the first rising edge of the clock signals after the STOP signal, and thus obtains the number N of the rising edges, namely the rough timing DATA DATA _TC;

On this basis, in order to realize accurate TIME measurement, the TIME length from the START signal trigger TIME (TIME measurement START TIME) to the first clock rising edge thereafter (denoted as TA) and the TIME length from the STOP signal trigger TIME (TIME measurement end TIME) to the first clock rising edge thereafter (denoted as TB) need to be calculated, thereby obtaining a TIME measurement result TIME, time=ta+tc-TB;

Therefore, the invention intercepts the fine timing DATA DATA _TF through the pulse modulation generating module and the delay chain module, and then calculates the time length TA and the time length TB through the decoding module; specifically, the START signal and STOP signal are used as triggers, and the clock period before the trigger time is used as a interception period to obtain waveform DATA of a modulation pulse on a delay chain in the interception period as fine timing DATA _TF;

Taking a START signal as an example, arbitrarily selecting a single pulse as a characteristic pulse in a multi-pulse period of a modulation pulse, and taking a minimum pulse MIN as the characteristic pulse in order to facilitate the calculation process of the fine timing data; any one of the rising edge or the falling edge of the modulation pulse in the interception period is taken as a measurement edge, as shown in fig. 2, wherein TE represents the delay time length of the rising edge of the clock relative to the characteristic pulse in the interception period, TI represents the delay time length of the measurement edge relative to the characteristic pulse, and Tr represents the time length of a delay unit on a delay chain;

the time length TA from the START signal trigger time (time measurement START time) to the first clock rising edge thereafter is specifically:

Wherein TA ^j represents the time length from the START signal trigger time to the first clock rising edge after the j-th measurement edge, TE _A represents the delay time length of the clock rising edge relative to the characteristic pulse in the interception period, Indicating the length of delay time of the measured edge relative to the characteristic pulse with reference to the jth measured edge,Representing the number of delay units transmitted by the measuring edge on the delay chain by taking the jth measuring edge as a reference;

In addition, the delay time length TE of the clock rising edge relative to the characteristic pulse in the intercepting period is negative when different monopulses are selected by the characteristic pulse, and the delay time length TE is brought into the formula to calculate the time length TA;

Similarly, the calculation principle of the time length TB from the STOP signal trigger time (time measurement end time) to the first clock rising edge thereafter is exactly the same as the calculation principle of the time length TA described above, and is specifically shown as follows in fig. 2:

Where TB ^j represents the length of time from the STOP signal trigger time at the jth measurement edge to the first clock rising edge thereafter, TE _B represents the length of delay time of the clock rising edge relative to the characteristic pulse in the capture period, Indicating the length of delay time of the measured edge relative to the characteristic pulse with reference to the jth measured edge,Representing the number of delay units transmitted by the measuring edge on the delay chain by taking the jth measuring edge as a reference;

In order to overcome the problem that nonlinear errors and low precision are caused by inconsistent delay time of the delay unit, in the calculation process of the time length TB and the time length TA, a plurality of measurement results are obtained through selection of measurement edges, and the nonlinear errors can be reduced by taking an average value, so that the effect is almost the same as that achieved by using multi-chain measurement.

More precisely, in this embodiment, as shown in fig. 3, the multi-pulse period of the modulation pulse is consistent with the clock period of the clock signal, specifically, T, the number of pulses of the modulation pulse is set to 4, the positive pulse width gradually decreases with time, the generated positive pulse widths are Ta, tb, tc, td, and the negative pulse width Ti is unchanged, taking the START signal as an example, the information on the delay chain is intercepted, the total length of the delay chain is consistent with the clock period to be T, the minimum pulse is taken as a characteristic pulse, as shown in fig. 4, the characteristic pulse position and the information on the delay chain are taken as fine timing DATA _TF, and the decoding module calculates TA as:

TA¹=T-Ta-Ti-3×Tr;

TA²=T-Ta-5×Tr;

TA³=T-11×Tr;

TA⁴=T+Ti-13×Tr;

TA⁵=T+Td+Ti-16×Tr;

TA⁶=T+Td+2×Ti-18×Tr;

TA⁷=T+Tc+Td+2×Ti-22×Tr;

TA⁸=T+Tc+Td+3×Ti-24×Tr;

In order to simplify the explanation, the embodiment shortens the length of the delay chain greatly, and the delay unit is also set to be ideal delay time, so that nonlinear errors and low precision are actually caused by inconsistent delay time of the delay unit;

In the rough timing, when the START signal and the STOP signal arrive, the rising edges of the arriving clock signal are counted as gate signals, 7 rising edges are counted to obtain total, N is recorded as rough timing DATA DATA _TC, TC is expressed as TC=7×T, and time information of the rough timing DATA DATA _TC is decoded;

And finally, fusing the fine timing data and the coarse timing data to obtain the final measured TIME, wherein time=TA+TC-TB.

In the foregoing description, only the specific embodiments of the invention have been described, and any features disclosed in this specification may be substituted for other equivalent or alternative features serving a similar purpose, and all the features disclosed, or all the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.

Claims

1. A time measuring device based on pulse modulation and fine rough timing comprises a pulse modulation generation module, a delay chain module, a counter module and a decoding module, and is characterized in that:

2. The time measuring device based on pulse modulation and fine and coarse timing according to claim 1, wherein the pulse modulation generating module modulates the pulse into a multi-pulse periodic signal, and the width of each positive pulse in the multi-pulse period is different and the width of each negative pulse is the same.

3. The time measuring device based on pulse modulation and fine rough timing according to claim 1, wherein in the delay chain module, the START signal and STOP signal are used as triggers, and a clock period before the trigger time is used as a clipping period, respectively, to obtain waveform data of the modulated pulse on the delay chain in the clipping period as fine timing data.

4. The pulse modulation and fine coarse timing based time measurement device of claim 1, wherein the counter module counts clock rising edges until a first clock rising edge after the STOP signal.

5. The time measurement device based on pulse modulation and fine rough timing according to claim 1, wherein in the decoding module, the decoding process of the rough timing data is:

TC=N×T,

6. The apparatus of claim 1, wherein the decoding module decodes the fine timing data by:

7. The time measurement device based on pulse modulation and fine rough timing according to claim 1, wherein the calculation process of the measurement time information in the decoding module is:

TIME=TA+TC-TB,