CN119355570A - A floating power supply voltage detection circuit and detection method thereof - Google Patents
A floating power supply voltage detection circuit and detection method thereof Download PDFInfo
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- 238000007667 floating Methods 0.000 title claims abstract description 49
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R15/14—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a floating power supply voltage detection circuit and a detection method thereof, wherein the circuit comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3 and a zener diode Z1. The detection voltage obtained by the invention is irrelevant to the gate-source voltage VGS of the MOS tube, meanwhile, the noise coupling problem of BST and SW to the detection voltage is eliminated, and the detection precision of the floating power supply voltage is improved.
Description
Technical Field
The invention relates to a voltage detection circuit and a detection method thereof, in particular to a floating power supply voltage detection circuit and a detection method thereof, belonging to the technical field of semiconductor integrated circuits.
Background
The DC-DC converter needs to be driven to detect the bootstrap voltage domain, i.e., the voltage difference between the high-side floating voltage BST and the floating ground SW, and further control the high-side driving circuit. The conventional technology converts the floating voltage difference, namely VBST-VSW, into the voltage related to the gate-source voltage VGS of the MOS transistor for detection. However, the gate-source voltage VGS of the MOS transistor is greatly affected by temperature and process deviation, resulting in floating detection voltage. In addition, since the rising and falling slopes of the high-side floating voltage BST and the floating ground SW are large, coupling interference is performed on the detection voltage.
Disclosure of Invention
The invention aims to provide a floating power supply voltage detection circuit and a detection method thereof, which can improve the detection precision of detection voltage.
In order to solve the technical problems, the invention adopts the following technical scheme:
A floating power supply voltage detection circuit comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3 and a zener diode Z1, wherein the source electrode of the PMOS tube MP1 and the source electrode of the PMOS tube MP3 are connected with a high-side floating voltage BST, the grid electrode of the PMOS tube MP1 is connected with the grid electrode of the PMOS tube MP3, the drain electrode of the PMOS tube MP1 and the source electrode of the PMOS tube MP2, the drain electrode of the PMOS tube MP3 is connected with the source electrode of the PMOS tube MP4, the grid electrode of the PMOS tube MP2 is connected with one end of the PMOS tube MP4, the other end of the resistor R1 is connected with a floating ground SW, the drain electrode of the PMOS tube MP4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the cathode of the zener diode Z1, the drain of the NMOS tube MN1, the grid of the NMOS tube MN2, one end of the capacitor C1 and one end of the resistor R3, the source of the NMOS tube MN1 is connected with the drain of the NMOS tube MN2, the other end of the resistor R3 is connected with one end of the capacitor C2, the grid of the NMOS tube NM4 and the grid of the NMOS tube MN3, the drain of the NMOS tube MN4 is connected with the source of the NMOS tube MN3, the drain of the PMOS tube MP6 and the grid of the PMOS tube MP8, the drain of the PMOS tube MP8 is connected with the source of the PMOS tube MP9 and outputs a detection voltage ns, the grid of the PMOS tube MP9 is connected with the drain of the PMOS tube MP9 and one end of the resistor R4, the other end of the resistor R5 is connected with the drain of the PMOS tube MP5, one end of the capacitor C3 and the grid of the PMOS tube MP7, the drain of the PMOS tube MP8 is connected with the drain of the PMOS tube MP7, the source of the PMOS tube MP7 is connected with the source of the PMOS tube MP7 and the source of the PMOS tube MP7 is connected with the drain of the PMOS tube MP7, the anode of the zener diode Z1, the source of the NMOS tube MN2, the other end of the capacitor C1, the other end of the capacitor C2, the source of the NMOS tube MN4 and the other end of the resistor R4 are grounded.
Further, the PMOS transistors MP1, MP2 and MP3 are low voltage transistors, and the PMOS transistor MP4 is a high voltage transistor.
Further, the ratio of the width to length ratios of the PMOS transistor MP3 and the PMOS transistor MP1 is k1, and the width to length ratios of the PMOS transistor MP1 and the PMOS transistor MP2 are equal.
Further, the ratio of the width to length ratios of the NMOS transistor MN1 and the NMOS transistor MN3 is k2, and the ratio of the width to length ratios of the NMOS transistor MN2 and the NMOS transistor MN4 is k2.
Further, the ratio of the width to length ratios of the PMOS transistors MP5 and MP7 is k3, and the ratio of the width to length ratios of the PMOS transistors MP6 and MP8 is k3.
Further, the resistor R4 and the resistor R1 are the same type of resistor, and the ratio of the resistance value of the resistor R4 to the resistance value of the resistor R1 is k4.
Further, the back gates of the PMOS transistors MP1, MP2 and MP9 are connected to the source.
Further, the resistor R2 and the capacitor C1 form a first-stage filtering, the resistor R3 and the capacitor C2 form a second-stage filtering, and the resistor R5 and the capacitor C3 form a third-stage filtering.
A detection method of a floating power supply voltage detection circuit comprises the following steps:
the current i1= (VBST-VSW-VGS 1-VGS 2)/R1 flowing through the resistor R1, wherein VBST is the voltage of the high-side floating voltage BST, VSW is the voltage of the floating ground SW, VGS1 is the gate-source voltage of the PMOS transistor MP1, VGS2 is the gate-source voltage of the PMOS transistor MP 2;
The current flowing through the PMOS transistor MP1 is equal to the current I1, the PMOS transistors MP1 and MP3 form a current mirror, and the ratio of the width to length ratios of the PMOS transistors MP3 and MP1 is k1, the current flowing through the PMOS transistor MP3 is k1×i1, the current I2 flowing through the resistor R2 is equal to the current flowing through the PMOS transistor MP3, and i2=k1×i1;
The current flowing through the NMOS tube MN1 and the NMOS tube MN2 is equal to the current I2, and since the ratio of the width to length ratios of the NMOS tube MN1 and the NMOS tube MN3 is k2, the ratio of the width to length ratios of the NMOS tube MN2 and the NMOS tube MN4 is k2, the current flowing through the NMOS tube MN3 and the NMOS tube MN4 is k2×i2, the current flowing through the PMOS tube MP5 and the PMOS tube MP6 is equal to the current flowing through the NMOS tube MN3 and the NMOS tube MN4, and since the ratio of the width to length ratios of the PMOS tube MP5 and the PMOS tube MP7 is k3, the ratio of the width to length ratios of the PMOS tube MP6 and the PMOS tube MP8 is k3, the current flowing through the PMOS tube MP7 and the PMOS tube MP8 is k3×k2×i2, the current I4 flowing through the resistor R4 is equal to the current flowing through the PMOS tube MP7 and the PMOS tube MP8, i.e. i4=k3×i2;
Detection voltage Vsns =i4×r4+vgs 9=k3 k2. 2R 4+vgs9
=k3*k2*k1*I1*R4+VGS9
=k3*k2*k1*(VBST-VSW-VGS1-VGS2)*R4/R1+VGS9,
Wherein VGS9 is the gate-source voltage of the PMOS tube MP 9;
because the width-to-length ratio of the PMOS tube MP1 and the PMOS tube MP2 is equal, VGS 1=vgs 2;
Vsns=k3×k2 x k1 (VBST-VSW-2 VGS 1) R4/R1+VGS9;
The width-to-length ratio of the PMOS tube MP9 is equal to that of the PMOS tube MP1, so that VGS1=VGS9;
Taking k1 x k 2x k3=1, k4=1/2,
Vsns= (VBST-VSW-2 vgs1)/2+vgs9 can be obtained
=(VBST-VSW)/2-VGS1+VGS9=(VBST-VSW)/2;
The detection voltage Vsns is irrelevant to the gate-source voltage VGS of the MOS transistor;
by adjusting the resistance values of the resistor R2, the resistor R3 and the resistor R4 and the capacitance values of the capacitor C1, the capacitor C2 and the capacitor C3, the coupling interference of the high-side floating voltage BST and the floating ground SW to the sampling voltage Vsns is eliminated.
Compared with the prior art, the floating power supply voltage detection circuit and the floating power supply voltage detection method have the advantages that the obtained detection voltage is irrelevant to the gate-source voltage VGS of the MOS tube, meanwhile, the noise coupling problem of BST and SW to the detection voltage is eliminated, and the precision of floating power supply voltage detection is improved.
Drawings
Fig. 1 is a schematic diagram of a floating supply voltage detection circuit of the present invention.
Detailed Description
In order to explain in detail the technical solutions adopted by the present invention to achieve the predetermined technical purposes, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and that technical means or technical features in the embodiments of the present invention may be replaced without inventive effort, and the present invention will be described in detail below with reference to the accompanying drawings in combination with the embodiments.
As shown in FIG. 1, the floating power supply voltage detection circuit of the present invention comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3 and a zener diode Z1, wherein the source electrode of the PMOS tube MP1 and the source electrode of the PMOS tube MP3 are connected with a high-side floating voltage BST, the gate electrode of the PMOS tube MP1 is connected with the gate electrode of the PMOS tube MP3, the drain electrode of the PMOS tube MP1 and the source electrode of the PMOS tube MP2, the drain electrode of the PMOS tube MP3 is connected with the source electrode of the PMOS tube MP4, the gate electrode of the PMOS tube MP2 is connected with the gate electrode of the PMOS tube MP4, the drain electrode of the PMOS tube MP2 and one end of the resistor R1, the other end of the resistor R1 is connected with a floating ground SW, one end of the drain electrode of the PMOS tube MP4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the cathode of the zener diode Z1, the drain of the NMOS tube MN1, the grid of the NMOS tube MN2, one end of the capacitor C1 and one end of the resistor R3, the source of the NMOS tube MN1 is connected with the drain of the NMOS tube MN2, the other end of the resistor R3 is connected with one end of the capacitor C2, the grid of the NMOS tube NM4 and the grid of the NMOS tube MN3, the drain of the NMOS tube MN4 is connected with the source of the NMOS tube MN3, the drain of the NMOS tube MN3 is connected with the drain of the PMOS tube MP6, the grid of the PMOS tube MP6 and the grid of the PMOS tube MP8, the drain of the PMOS tube MP8 is connected with the source of the PMOS tube MP9 and outputs a detection voltage ns, the grid of the PMOS tube MP9 is connected with the drain of the PMOS tube MP9 and one end of the resistor R4, the source of the PMOS tube MP6 is connected with the drain of the PMOS tube MP5, the grid of the PMOS tube MP5 and one end of the resistor R5 is connected with the one end of the capacitor C3 and the grid of the PMOS tube MP7, the drain of the PMOS tube MP8 is connected with the drain of the PMOS tube MP7, the drain of the PMOS tube MP7 is connected with the drain of the PMOS tube MP5, the other end of the capacitor C3 and the source electrode of the PMOS tube MP7 are connected with a power supply VCC, and the anode of the zener diode Z1, the source electrode of the NMOS tube MN2, the other end of the capacitor C1, the other end of the capacitor C2, the source electrode of the NMOS tube MN4 and the other end of the resistor R4 are grounded.
The PMOS tube MP1, the PMOS tube MP2 and the PMOS tube MP3 are low-voltage tubes, and the PMOS tube MP4 is a high-voltage tube.
The ratio of the width to length ratios of the PMOS tube MP3 and the PMOS tube MP1 is k1, and the width to length ratios of the PMOS tube MP1 and the PMOS tube MP2 are equal.
The ratio of the width to length ratios of the NMOS transistor MN1 and the NMOS transistor MN3 is k2, and the ratio of the width to length ratios of the NMOS transistor MN2 and the NMOS transistor MN4 is k2.
The ratio of the width-length ratios of the PMOS tube MP5 and the PMOS tube MP7 is k3, and the ratio of the width-length ratios of the PMOS tube MP6 and the PMOS tube MP8 is k3.
The resistor R4 and the resistor R1 are the same type of resistor, and the ratio of the resistance value of the resistor R4 to the resistance value of the resistor R1 is k4.
The back gates of the PMOS tube MP1, the PMOS tube MP2 and the PMOS tube MP9 are connected with the source electrode.
The resistor R2 and the capacitor C1 form first-stage filtering, the resistor R3 and the capacitor C2 form second-stage filtering, and the resistor R5 and the capacitor C3 form third-stage filtering.
A detection method of a floating power supply voltage detection circuit comprises the following steps:
The current i1= (VBST-VSW-VGS 1-VGS 2)/R1 flowing through the resistor R1, wherein VBST is the voltage of the high-side floating voltage BST, VSW is the voltage of the floating ground SW, VGS1 is the gate-source voltage of the PMOS transistor MP1, and VGS2 is the gate-source voltage of the PMOS transistor MP 2.
The current flowing through the PMOS transistor MP1 is equal to the current I1, the PMOS transistors MP1 and MP3 form a current mirror, and the ratio of the width to length ratios of the PMOS transistors MP3 and MP1 is k1, then the current flowing through the PMOS transistor MP3 is k1×i1, the current I2 flowing through the resistor R2 is equal to the current flowing through the PMOS transistor MP3, and i2=k1×i1.
The current flowing through the NMOS tube MN1 and the NMOS tube MN2 is equal to the current I2, and since the ratio of the width to length ratios of the NMOS tube MN1 and the NMOS tube MN3 is k2, the ratio of the width to length ratios of the NMOS tube MN2 and the NMOS tube MN4 is k2, the current flowing through the NMOS tube MN3 and the NMOS tube MN4 is k2×i2, the current flowing through the PMOS tube MP5 and the PMOS tube MP6 is equal to the current flowing through the NMOS tube MN3 and the NMOS tube MN4, and since the ratio of the width to length ratios of the PMOS tube MP5 and the PMOS tube MP7 is k3, the ratio of the width to length ratios of the PMOS tube MP6 and the PMOS tube MP8 is k3, the current flowing through the PMOS tube MP7 and the PMOS tube MP8 is k3×k2×i2, the current I4 flowing through the resistor R4 is equal to the current flowing through the PMOS tube MP7 and the PMOS tube MP8, i.e. i4=k3×i2.
Detection voltage Vsns =i4×r4+vgs 9=k3 k2. 2R 4+vgs9
=k3*k2*k1*I1*R4+VGS9
=k3*k2*k1*(VBST-VSW-VGS1-VGS2)*R4/R1+VGS9,
Wherein VGS9 is the gate-source voltage of PMOS tube MP 9.
Because the aspect ratio of the PMOS tube MP1 and the PMOS tube MP2 is equal, VGS 1=vgs 2.
Vsns=k3×k2 x k1 (VBST-VSW-2 VGS 1) R4/R1+VGS9.
Let the width-to-length ratio of the PMOS tube MP9 be equal to the width-to-length ratio of the PMOS tube MP1, vgs1=vgs9.
Taking k1 x k 2x k3=1, k4=1/2,
Vsns= (VBST-VSW-2 vgs1)/2+vgs9 can be obtained
=(VBST-VSW)/2-VGS1+VGS9=(VBST-VSW)/2。
The detection voltage Vsns is independent of the gate-source voltage VGS of the MOS transistor.
By adjusting the resistance values of the resistor R2, the resistor R3 and the resistor R4 and the capacitance values of the capacitor C1, the capacitor C2 and the capacitor C3, the coupling interference of the high-side floating voltage BST and the floating ground SW to the sampling voltage Vsns is eliminated.
The invention provides a floating power supply voltage detection circuit and a detection method thereof, the obtained detection voltage is irrelevant to the gate-source voltage VGS of an MOS tube, the noise coupling problem of BST and SW to the detection voltage is eliminated, and the precision of the floating power supply voltage detection is improved.
The present invention is not limited to the preferred embodiments, and the present invention is described above in any way, but is not limited to the preferred embodiments, and any person skilled in the art will appreciate that the present invention is not limited to the embodiments described above, while the invention has been described with respect to specific examples including presently preferred modes of carrying out the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described embodiments that fall within the spirit and scope of the invention as set forth in the appended claims.
Claims (9)
1. A floating power supply voltage detection circuit is characterized in that: the MOS transistor comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3 and a zener diode Z1, wherein the source electrode of the PMOS tube MP1 and the source electrode of the PMOS tube MP3 are connected with a high-side floating voltage BST, the grid electrode of the PMOS tube MP1 is connected with the grid electrode of the PMOS tube MP3, the drain electrode of the PMOS tube MP1 and the source electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP2 is connected with the grid electrode of the PMOS tube MP4, one end of the drain electrode of the PMOS tube MP2 and one end of the resistor R1 are connected with a floating ground SW, the drain electrode of the PMOS tube MP4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the cathode of the zener diode Z1, the drain of the NMOS tube MN1, the grid of the NMOS tube MN2, one end of the capacitor C1 and one end of the resistor R3, the source of the NMOS tube MN1 is connected with the drain of the NMOS tube MN2, the other end of the resistor R3 is connected with one end of the capacitor C2, the grid of the NMOS tube NM4 and the grid of the NMOS tube MN3, the drain of the NMOS tube MN4 is connected with the source of the NMOS tube MN3, the drain of the NMOS tube MN3 is connected with the drain of the PMOS tube MP6, the grid of the PMOS tube MP6 and the grid of the PMOS tube MP8, the drain of the PMOS tube MP8 is connected with the source of the PMOS tube MP9 and outputs a detection voltage ns, the grid of the PMOS tube MP9 is connected with the drain of the PMOS tube MP9 and one end of the resistor R4, the source of the PMOS tube MP6 is connected with the drain of the PMOS tube MP5, the grid of the PMOS tube MP5 and one end of the resistor R5 is connected with the one end of the capacitor C3 and the grid of the PMOS tube MP7, the drain of the PMOS tube MP8 is connected with the drain of the PMOS tube MP7, the drain of the PMOS tube MP7 is connected with the drain of the PMOS tube MP5, the other end of the capacitor C3 and the source electrode of the PMOS tube MP7 are connected with a power supply VCC, and the anode of the zener diode Z1, the source electrode of the NMOS tube MN2, the other end of the capacitor C1, the other end of the capacitor C2, the source electrode of the NMOS tube MN4 and the other end of the resistor R4 are grounded.
2. The floating power supply voltage detection circuit according to claim 1, wherein the PMOS transistor MP1, the PMOS transistor MP2 and the PMOS transistor MP3 are low-voltage transistors, and the PMOS transistor MP4 is a high-voltage transistor.
3. The floating power supply voltage detection circuit of claim 1, wherein the ratio of the width to length ratios of the PMOS transistor MP3 and the PMOS transistor MP1 is k1, and the width to length ratios of the PMOS transistor MP1 and the PMOS transistor MP2 are equal.
4. The floating power supply voltage detection circuit of claim 1, wherein the ratio of the aspect ratio of the NMOS transistor MN1 to the NMOS transistor MN3 is k2, and the ratio of the aspect ratio of the NMOS transistor MN2 to the NMOS transistor MN4 is k2.
5. The floating power supply voltage detection circuit of claim 1, wherein the ratio of the width to length ratios of the PMOS transistor MP5 and the PMOS transistor MP7 is k3, and the ratio of the width to length ratios of the PMOS transistor MP6 and the PMOS transistor MP8 is k3.
6. A floating power supply voltage detection circuit according to claim 1 wherein the resistor R4 and the resistor R1 are of the same type, and the ratio of the resistance of the resistor R4 to the resistance of the resistor R1 is k4.
7. The floating power supply voltage detection circuit according to claim 1, wherein back gates of the PMOS transistors MP1, MP2 and MP9 are connected with the source electrode.
8. A floating power supply voltage detection circuit according to claim 1 wherein said resistor R2 and capacitor C1 form a first stage of filtering, resistor R3 and capacitor C2 form a second stage of filtering, and resistor R5 and capacitor C3 form a third stage of filtering.
9. A detection method of a floating power supply voltage detection circuit according to any one of claims 1 to 8, characterized by comprising the steps of:
the current i1= (VBST-VSW-VGS 1-VGS 2)/R1 flowing through the resistor R1, wherein VBST is the voltage of the high-side floating voltage BST, VSW is the voltage of the floating ground SW, VGS1 is the gate-source voltage of the PMOS transistor MP1, VGS2 is the gate-source voltage of the PMOS transistor MP 2;
The current flowing through the PMOS transistor MP1 is equal to the current I1, the PMOS transistors MP1 and MP3 form a current mirror, and the ratio of the width to length ratios of the PMOS transistors MP3 and MP1 is k1, the current flowing through the PMOS transistor MP3 is k1×i1, the current I2 flowing through the resistor R2 is equal to the current flowing through the PMOS transistor MP3, and i2=k1×i1;
The current flowing through the NMOS tube MN1 and the NMOS tube MN2 is equal to the current I2, and since the ratio of the width to length ratios of the NMOS tube MN1 and the NMOS tube MN3 is k2, the ratio of the width to length ratios of the NMOS tube MN2 and the NMOS tube MN4 is k2, the current flowing through the NMOS tube MN3 and the NMOS tube MN4 is k2×i2, the current flowing through the PMOS tube MP5 and the PMOS tube MP6 is equal to the current flowing through the NMOS tube MN3 and the NMOS tube MN4, and since the ratio of the width to length ratios of the PMOS tube MP5 and the PMOS tube MP7 is k3, the ratio of the width to length ratios of the PMOS tube MP6 and the PMOS tube MP8 is k3, the current flowing through the PMOS tube MP7 and the PMOS tube MP8 is k3×k2×i2, the current I4 flowing through the resistor R4 is equal to the current flowing through the PMOS tube MP7 and the PMOS tube MP8, i.e. i4=k3×i2;
Detection voltage Vsns =i4×r4+vgs 9=k3 k2. 2R 4+vgs9
=k3*k2*k1*I1*R4+VGS9
=k3*k2*k1*(VBST-VSW-VGS1-VGS2)*R4/R1+VGS9,
Wherein VGS9 is the gate-source voltage of the PMOS tube MP 9;
because the width-to-length ratio of the PMOS tube MP1 and the PMOS tube MP2 is equal, VGS 1=vgs 2;
Vsns=k3×k2 x k1 (VBST-VSW-2 VGS 1) R4/R1+VGS9;
The width-to-length ratio of the PMOS tube MP9 is equal to that of the PMOS tube MP1, so that VGS1=VGS9;
Taking k1 x k 2x k3=1, k4=1/2,
Vsns= (VBST-VSW-2 vgs1)/2+vgs9 can be obtained
=(VBST-VSW)/2-VGS1+VGS9=(VBST-VSW)/2;
The detection voltage Vsns is irrelevant to the gate-source voltage VGS of the MOS transistor;
by adjusting the resistance values of the resistor R2, the resistor R3 and the resistor R4 and the capacitance values of the capacitor C1, the capacitor C2 and the capacitor C3, the coupling interference of the high-side floating voltage BST and the floating ground SW to the sampling voltage Vsns is eliminated.
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| CN118739785A (en) * | 2023-03-31 | 2024-10-01 | 中国科学院微电子研究所 | A DC-DC converter and current sampling circuit thereof |
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