CN119342896A

CN119342896A - Array substrate and manufacturing method thereof and display device

Info

Publication number: CN119342896A
Application number: CN202310877275.2A
Authority: CN
Inventors: 张仁伟; 曾亭; 胡海峰; 刘欢; 查鑫; 柳宵宵; 肖涛; 杨财桂; 李鑫
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Ruisheng Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Ruisheng Technology Co Ltd
Priority date: 2023-07-17
Filing date: 2023-07-17
Publication date: 2025-01-21
Also published as: WO2025016102A1

Abstract

Provided is an array substrate, comprising: a substrate; a first passivation layer disposed on the substrate; a first conductive layer disposed on a side of the first passivation layer away from the substrate; and a second passivation layer disposed on a side of the first conductive layer away from the substrate. The first conductive layer has a stacked structure, comprising a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer being located on a side of the first passivation layer away from the substrate, the second sub-conductive layer being located on a side of the first sub-conductive layer away from the substrate, and the third sub-conductive layer being located on a side of the second sub-conductive layer away from the substrate; the first sub-conductive layer and the third sub-conductive layer are made of the same material, and the second sub-conductive layer and the third sub-conductive layer are made of different materials; the thickness of the third sub-conductive layer is less than the thickness of the first sub-conductive layer, and the thickness of the second sub-conductive layer is greater than the thickness of each of the first sub-conductive layer and the third conductive layer.

Description

Array substrate, preparation method thereof and display device

Technical Field

The disclosure relates to the technical field of display, in particular to an array substrate, a display device and a preparation method of the array substrate.

Background

Light emitting Diode (LIGHT EMITTING Diode, abbreviated as LED) technology has been developed for nearly thirty years, and its application range is expanding, for example, it may be applied to the display field, used as a backlight source of a display device or used as an LED display screen. With the development of technology, a sub-millimeter light emitting Diode (MINI LIGHT EMITTING Diode, abbreviated as Mini LED) and a Micro light emitting Diode (Micro LIGHT EMITTING Diode, abbreviated as Micro LED) are becoming one of research hotspots in the field of display technology. For example, mini LEDs or Micro LEDs may be used in light emitting modules in liquid crystal display devices as light emitting elements of the light emitting modules.

The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure, and thus, the above information may contain information that does not constitute prior art.

Disclosure of Invention

In one aspect, an array substrate is provided, the array substrate comprises a substrate, a first passivation layer arranged on one side of the substrate, far away from the substrate, of the first passivation layer, a first conductive layer arranged on one side of the first conductive layer, far away from the substrate, of the second passivation layer, the array substrate comprises a plurality of array units which are distributed on the substrate in an array mode, at least one array unit comprises a light emitting diode, the light emitting diode comprises a first electrode and a second electrode, the array substrate comprises a plurality of pad pairs, the pad pairs comprise a first pad and a second pad, the first pad is used for being electrically connected with the first electrode, the second pad is used for being electrically connected with the second electrode, the first conductive layer is provided with a laminated structure, the laminated structure of the first conductive layer comprises a first sub-conductive layer, a second sub-layer and a third sub-layer, the first sub-conductive layer is located on one side of the substrate, far away from the first conductive sub-layer, of the first conductive layer is located on the same thickness as the first conductive sub-layer, the second conductive sub-layer is located on the first conductive layer, the second conductive sub-layer is located on the second side of the substrate, the second conductive layer is located on the same thickness as the first conductive sub-layer, the first conductive layer is located on the second conductive layer is located on the side of the first conductive layer, and the second conductive sub-layer is located on the second conductive layer is located on the second side, and is located on the second sub-layer is located on the second conductive layer, and is located on the second conductive layer side, the second sub-conductive layer has a thickness greater than a thickness of each of the first sub-conductive layer and the third conductive layer.

For example, in some exemplary embodiments, the array substrate may be an array substrate of a display panel, and accordingly, the array unit may be a pixel unit of the display panel, or the array substrate may be a substrate of a backlight module, and accordingly, the array unit may be a light emitting unit of the backlight module.

According to some exemplary embodiments, the thickness of the third sub-conductive layer is less than or equal to one half of the thickness of the first sub-conductive layer.

According to some exemplary embodiments, the third sub-conductive layer has a thickness of greater than 0 angstroms and less than or equal to 150 angstroms.

According to some exemplary embodiments, the second sub-conductive layer has a thickness of 1.8 microns or greater.

According to some exemplary embodiments, a ratio of a thickness of the second passivation layer to a thickness of the third sub-conductive layer is greater than 26.

According to some exemplary embodiments, the thickness of the second passivation layer is greater than the thickness of the first passivation layer.

According to some exemplary embodiments, the thickness of the second passivation layer is 4000 angstroms or more and 6000 angstroms or less.

According to some exemplary embodiments, the orthographic projection of the third sub-conductive layer onto the substrate falls within the orthographic projection of the second sub-conductive layer onto the substrate, and/or the orthographic projection of the second sub-conductive layer onto the substrate falls within the orthographic projection of the first sub-conductive layer onto the substrate.

According to some exemplary embodiments, the array substrate further includes a second conductive layer, the second conductive layer being located on a side of the first passivation layer adjacent to the substrate, and the second conductive layer having a thickness smaller than a thickness of the first conductive layer.

According to some exemplary embodiments, the array substrate further includes a plurality of terminals in the first conductive layer, the plurality of terminals for electrically connecting with pins of a driving chip, and the array substrate further includes a plurality of conductive connection portions in the first conductive layer, at least one of the conductive connection portions electrically connecting at least one of the terminals with at least one of the first pads.

According to some exemplary embodiments, the array substrate further includes a plurality of traces in the second conductive layer, the array substrate further includes a via in the first passivation layer, and a conductive portion in the first conductive layer, and one end of the conductive portion is electrically connected to at least one of the second pads, and at least one of the traces is electrically connected to the conductive portion through the via.

According to some exemplary embodiments, the plurality of terminals includes a first terminal for electrically connecting with a ground signal pin of a driving chip, the plurality of traces includes a first trace for transmitting a ground signal, and the via includes a plurality of first vias through which the first trace is electrically connected with the first conductive portion, the other end of the first conductive portion is electrically connected with the first terminal, and orthographic projections of the plurality of first vias on the substrate are arranged side by side in a first direction within orthographic projections of the first conductive portion on the substrate.

According to some exemplary embodiments, the array substrate further comprises a grounding wire, the grounding wire is located in the first conductive layer, the grounding wire extends along a first direction, the first routing wire extends along a second direction, the first direction and the second direction intersect, the via hole comprises a plurality of second via holes, the first routing wire is electrically connected with the grounding wire through the plurality of second via holes, and orthographic projections of the plurality of second via holes on the substrate are arranged in a orthographic projection of the grounding wire on the substrate along the first direction side by side.

According to some exemplary embodiments, the array unit may be a pixel unit, at least one of the pixel units includes a first sub-pixel including a first light emitting diode, a second sub-pixel including a second light emitting diode, and a third sub-pixel including a third light emitting diode, the plurality of terminals further includes a second terminal, a third terminal, and a fourth terminal, the plurality of pad pairs includes a first pad pair, a second pad pair, and a third pad pair, a first pad and a second pad of the first pad pair are electrically connected to a first electrode and a second electrode of the first light emitting diode, respectively, a first pad and a second pad of the second pad pair are electrically connected to a first electrode and a second electrode of the second light emitting diode, respectively, a first pad and a second pad of the third pad pair are electrically connected to a first electrode and a second electrode of the third light emitting diode, respectively, and the conductive connection portion includes a first conductive connection portion, a second conductive portion, and a third conductive portion are electrically connected to the first terminal and the third terminal.

According to some exemplary embodiments, the plurality of traces further includes a second trace for transmitting a first voltage signal to the first light emitting diode and a third trace for transmitting a second voltage signal to the second light emitting diode and the third light emitting diode, the via includes a third via and a plurality of fourth vias, the conductive portion includes a second conductive portion and a third conductive portion, the second trace is electrically connected to one end of the second conductive portion through the third via, the other end of the second conductive portion is electrically connected to the second pad of the first pad pair, the third trace is electrically connected to the third conductive portion through the plurality of fourth vias, the third conductive portion is electrically connected to both the second pad of the second pad pair and the second pad of the third pad pair, and the plurality of fourth vias are arranged in a side-by-side arrangement in a second direction on the substrate.

According to some exemplary embodiments, the array unit may be a pixel unit, at least one of the pixel units includes a first subpixel including a first light emitting diode, a second subpixel including a second light emitting diode, and a third subpixel including a third light emitting diode, the plurality of pad pairs includes a first pad pair, a second pad pair, and a third pad pair, the first pad and the second pad of the first pad pair are electrically connected to a first electrode and a second electrode of the first light emitting diode, respectively, the first pad and the second pad of the second pad pair are electrically connected to a first electrode and a second electrode of the second light emitting diode, respectively, the first pad and the second pad of the third pad pair are electrically connected to a first electrode and a second electrode of the third light emitting diode, respectively, and the array substrate includes a first voltage signal line and a second voltage signal line in the first conductive layer, the first pad pair is electrically connected to the first voltage signal line and the second pad pair, and the first voltage signal line is electrically connected to the first pad pair, and the second pad pair is electrically connected to the first voltage signal line and the second pad pair.

According to some exemplary embodiments, the material of the first and third sub-conductive layers comprises MoNb and the material of the second sub-conductive layer comprises Cu.

In another aspect, an array substrate is provided, the array substrate including a substrate; the substrate comprises a substrate, a first passivation layer arranged on one side of the substrate, which is far away from the substrate, a first conductive layer arranged on one side of the first passivation layer, which is far away from the substrate, and a second passivation layer arranged on one side of the first conductive layer, which is far away from the substrate, wherein the array substrate comprises a plurality of array units which are distributed on the substrate in an array manner, at least one array unit comprises a light emitting diode, the light emitting diode comprises a first electrode and a second electrode, the array substrate comprises a plurality of bonding pad pairs, which are positioned in the first conductive layer, at least one bonding pad pair comprises a first bonding pad and a second bonding pad, which are used for being electrically connected with the first electrode, the second bonding pad is used for being electrically connected with the second electrode, the first conductive layer comprises a laminated structure, the laminated structure of the first conductive sub-layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer is positioned on one side of the first passivation layer, which is far away from the substrate, and the second conductive sub-layer is positioned on one side of the substrate, which is far away from the substrate, and the second conductive sub-layer is thicker than the first conductive sub-layer 26.

In yet another aspect, a display device is provided, wherein the display device includes the array substrate as described above.

In yet another aspect, a method for fabricating an array substrate is provided, the method comprising providing a substrate, forming a first passivation layer on the substrate, forming a first conductive material layer on a side of the first passivation layer away from the substrate, performing a patterning process on the first conductive material layer to form a plurality of pad pairs, wherein at least one of the pad pairs comprises a first pad for electrically connecting with a first electrode of a light emitting diode and a second pad for electrically connecting with a second electrode of the light emitting diode, and forming a second passivation layer on a side of the plurality of pad pairs away from the substrate, wherein forming a first conductive material layer on a side of the first passivation layer away from the substrate comprises forming a first sub-conductive material layer on a side of the first passivation layer away from the substrate, forming a second sub-conductive material layer on a side of the first sub-conductive layer away from the substrate, and forming a third conductive material layer of the same thickness as the first conductive material layer and the third conductive material layer on a side of the second sub-conductive material layer, wherein the third conductive material layer is different from the first conductive material layer and the first conductive material layer.

According to some exemplary embodiments, the performing a patterning process on the first conductive material layer includes coating a photoresist layer on the first conductive material layer, performing a pre-bake process on the photoresist layer, exposing the photoresist layer, and performing a post-bake process on the photoresist layer, wherein a post-bake temperature is greater than 130 ℃ and a post-bake time is greater than 8 minutes in the post-bake process.

According to some exemplary embodiments, the forming a second passivation layer on a side of the plurality of pad pairs away from the substrate includes forming a second passivation layer on a side of the plurality of pad pairs away from the substrate by a chemical vapor deposition process.

Drawings

Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, and may assist in a comprehensive understanding of the present disclosure.

Fig. 1 is a partial structural schematic view of a display panel according to some exemplary embodiments of the present disclosure;

fig. 2 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, in which an electrical connection relationship between a pad and a pixel unit is shown;

FIG. 3 is a partial plan view of a display panel showing projected relationship of first, second, and third sub-conductive layers in a vertical substrate space according to some exemplary embodiments of the present disclosure;

fig. 4 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, in which a positional relationship of a second conductive layer and a first passivation layer is shown;

Fig. 5 illustrates a schematic plan view of a display panel of some embodiments of the present disclosure, in which an electrical connection structure of a driving chip, terminals, conductive connection parts, and pads is shown;

Fig. 6 illustrates a schematic plan view of a display panel of other embodiments of the present disclosure, in which an electrical connection relationship between a first conductive layer and a second conductive layer and an electrical connection relationship between wires, conductive parts, terminals and a driving chip are illustrated, and fig. 6 also illustrates an electrical connection relationship between a ground line and a first wire;

FIG. 7 illustrates a schematic plan view of a display panel of some embodiments of the present disclosure, showing electrical connection relationships of pixels, terminals, pads, and conductive connections;

FIG. 8 is a schematic plan view of a display panel illustrating electrical connections of traces, conductive portions, pads, and LEDs according to further embodiments of the present disclosure;

Fig. 9 is a schematic plan view of a display panel according to still other embodiments of the present disclosure, in which electrical connection relations between first and second voltage signal lines and pads, light emitting diodes are shown;

fig. 10 illustrates a schematic structural view of a display panel of other embodiments of the present disclosure, in which a thickness ratio of a second passivation layer to a third sub-conductive layer is illustrated;

FIG. 11 is a schematic diagram of other embodiments of the present disclosure, wherein a backlight module is used as a backlight source in a liquid crystal panel;

Fig. 12A illustrates a schematic structure of a backlight module according to other embodiments of the present disclosure, fig. 12B illustrates a schematic plan view of a backlight module, and fig. 12B illustrates an electrical connection relationship between a light emitting unit and a pair of pads in the backlight module;

FIG. 13 is a schematic view showing a structure of a backlight module according to other embodiments of the present disclosure, in which a thickness relationship between a second conductive layer and a first conductive layer is shown;

fig. 14A and 14B are respectively a display device according to an exemplary embodiment of the present disclosure;

fig. 15 is a method of manufacturing a display panel according to an exemplary embodiment of the present disclosure, and

Fig. 16 is a flowchart of a patterning process performed on a first conductive material layer according to an exemplary embodiment of the present disclosure.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments. It may be evident, however, that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

In the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or description. As such, the dimensions and relative dimensions of the various elements are not necessarily limited to those shown in the figures. While the exemplary embodiments may be practiced differently, the specific process sequence may be performed differently than as described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order of the order described. Furthermore, like reference numerals denote like elements.

When an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, connected to, or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms and/or expressions used to describe the relationship between elements should be interpreted in a similar manner, e.g. "between" and "directly between", "adjacent" and "directly adjacent" or "in" and "directly on" etc. Furthermore, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and/or a fluid connection. Further, the X-axis, Y-axis, and Z-axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y and Z such as XYZ, XY, YZ and XZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments.

Herein, the inorganic light emitting diode refers to a light emitting element made of an inorganic material, wherein the LED means an inorganic light emitting element different from the OLED. Specifically, the inorganic light emitting element may include a sub-millimeter light emitting Diode (MINI LIGHT EMITTING Diode, abbreviated as Mini LED) and a Micro light emitting Diode (Micro LIGHT EMITTING Diode, abbreviated as Micro LED). Wherein, the Micro light emitting diode (i.e. Micro LED) refers to a Micro light emitting diode with a grain size below 100 micrometers, the sub-millimeter light emitting diode (i.e. Mini LED) refers to a Micro light emitting diode with a grain size between Micro LED and conventional LED, for example, the grain size of Mini LED may be between 50-400 micrometers.

In the conventional liquid crystal display, the brightness is controlled by the deflection of the liquid crystal, and the deflection of the liquid crystal takes a long time, generally on the order of microseconds. Under the rapid movement and submission of the image, the phenomenon of trailing the picture is easy to occur. The tailing phenomenon, which is an inherent phenomenon of the liquid crystal display system, is said to be reduced in the driving technique generally by overdrive (over-driving), but is not eliminated, as long as the moving speed of the object exceeds the limit reaction speed of the display device. The novel display system overcomes the tailing phenomenon because the Mini LED or Micro LED directly emits light by a light-emitting diode to realize display. In new Mini LED or Micro LED displays, the conductive medium in the circuit needs to have excellent conductivity and high ductility. In the actual process, the conductive medium is often poor in protection, so that the conductive medium is corroded, and finally abnormal display of the product is caused. Therefore, in the preparation of the display panel, the protection capability of the conductive medium is improved, and the conductive medium is prevented from being corroded, so that the use reliability of the display panel is improved.

The embodiment of the disclosure provides an array substrate, which comprises a substrate; a first passivation layer disposed on the substrate; the array substrate comprises a plurality of array units which are distributed on the substrate in an array way, at least one array unit comprises a light emitting diode, the light emitting diode comprises a first electrode and a second electrode, the array substrate comprises a plurality of bonding pad pairs, the bonding pad pairs are positioned in the first conductive layer, at least one bonding pad pair comprises a first bonding pad and a second bonding pad, the first bonding pad is used for being electrically connected with the first electrode, the second bonding pad is used for being electrically connected with the second electrode, the first conductive layer is provided with a laminated structure, the laminated structure of the first conductive layer comprises a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer is positioned on one side of the first layer away from the substrate, the second sub-conductive layer is positioned on one side of the substrate, the second sub-conductive layer is positioned on the second sub-layer, the second sub-conductive layer is positioned on the other side of the substrate, the second sub-conductive layer is positioned on the other side of the first sub-conductive layer, the second sub-conductive layer is positioned on the same thickness as the first sub-conductive layer, the second sub-conductive layer is positioned on the other side of the substrate, the second sub-conductive layer is positioned on the other side of the substrate, and the first sub-conductive layer is positioned on the same thickness as the sub-conductive layer, the first sub-conductive layer is positioned on the second sub-conductive layer is positioned on the side of the substrate, and the sub-conductive layer is positioned on the layer is larger thickness than the conductive layer, and the sub-conductive layer is the conductive layer from the first conductive layer, the etching rate of the second sub-conductive layer and the third sub-conductive layer can be adjusted by optimizing the thickness relation of the second sub-conductive layer and the third sub-conductive layer, so that the phenomenon of retraction or protruding top end during etching is avoided, and the product yield can be improved.

It should be noted that, in the embodiment of the present disclosure, the array substrate may be an array substrate of a display panel, and correspondingly, the array unit may be a pixel unit of the display panel, or the array substrate may be a substrate of a backlight module, and correspondingly, the array unit may be a light emitting unit of the backlight module. In the following description, a display panel and a backlight module are taken as examples, respectively, and an array substrate according to an embodiment of the present disclosure is described in detail. It should be understood that such separate descriptions are for convenience of description only, and that the structures of the display panel and the backlight module may be combined with each other and referred to each other without conflict.

Fig. 1 is a partial structural schematic diagram of a display panel according to some exemplary embodiments of the present disclosure.

Referring to fig. 1 in combination, the display panel 100 may include a plurality of film layers disposed on a substrate 1, for example, the plurality of film layers include a first passivation layer 2 disposed on the substrate 1, a first conductive layer 3 disposed on a side of the first passivation layer 2 remote from the substrate, and a second passivation layer 4 disposed on a side of the first conductive layer 3 remote from the substrate.

For example, the material of the base substrate 1 may include, but is not limited to, glass, quartz, plastic, silicon, polyimide, and the like.

Referring to fig. 1, in the embodiment of the disclosure, the first conductive layer 3 is a stacked structure, and includes a first sub-conductive layer 31 located on a side of the first passivation layer 2 away from the substrate, a second sub-conductive layer 32 located on a side of the first sub-conductive layer 31 away from the substrate, and a third sub-conductive layer 33 located on a side of the second sub-conductive layer 32 away from the substrate. The conductive member for connection with the light emitting diode or the driving chip may be located in the first conductive layer 3, and for example, the second sub-conductive layer 32 of the first conductive layer 3 may be a material having a high conductivity such as Cu.

In the display manufacturing process, cu ions are diffused into the semiconductor across the gate insulating layer when the copper electrode is at a high temperature, so that the thin film transistor performance is deteriorated, and it is generally required to add a diffusion preventing layer on the surface of the copper electrode. For example, the first sub-conductive layer 31 and the third sub-conductive layer 33 of the first conductive layer 3 in the embodiment of the present disclosure are diffusion preventing layers, wherein the materials of the first sub-conductive layer 31 and the third sub-conductive layer 33 may be the same. The material of the first sub-conductive layer 31 may be a metal layer, a metal nitride layer, a metal alloy, etc., such as metallic titanium (Ti), molybdenum (Mo), niobium molybdenum alloy (MoNb), etc. The second sub-conductive layer 32 is of a different material than the first sub-conductive layer 31. The first sub-conductive layer 31 is located between the first passivation layer 2 and the second sub-conductive layer 32, and when the thickness of the first sub-conductive layer 31 is thicker, for example, the thickness D1 of the first sub-conductive layer 31 is 300 angstroms, the first sub-conductive layer 31 can better prevent the second sub-conductive layer 32 from diffusing into the gate insulating layer.

The inventors have found that, although the diffusion preventing layer can prevent the diffusion of the copper electrode into the gate insulating layer, the diffusion preventing layer and the copper electrode may have different etching shapes in the subsequent patterning process due to inconsistent etching rates of the diffusion preventing layer and the copper electrode, resulting in poor protection of the copper electrode by the diffusion preventing layer and thus poor product. For example, when the first conductive layer 3 adopts a laminated structure, since the etching rates of the third sub-conductive layer 33 and the second sub-conductive layer 32 are not uniform, when the etching rate of the third sub-conductive layer 33 is higher than the etching rate of the second sub-conductive layer 32, the etched area is indented, so that the third sub-conductive layer 33 and the second sub-conductive layer 32 are not level, the remaining area of the third sub-conductive layer is smaller than the area of the second sub-conductive layer 32, and the product is determined to be poor due to poor appearance. When the etching speed of the third sub-conductive layer 33 is lower than that of the second sub-conductive layer 32, the top protrusion phenomenon occurs in the etched area, and the remaining area of the third sub-conductive layer is larger than that of the second sub-conductive layer 32, which eventually causes poor appearance. The etching rate of the second sub-conductive layer 32 and the third sub-conductive layer 33 can be adjusted by optimizing the thickness relationship of the second sub-conductive layer 32 and the third sub-conductive layer 33, and the occurrence of the recession phenomenon or the top protrusion phenomenon during etching is avoided.

In the embodiment of the present disclosure, referring to fig. 1, the thickness D3 of the third sub-conductive layer 33 is smaller than the thickness D1 of the first sub-conductive layer 31, and the thickness D2 of the second sub-conductive layer 32 is larger than the thickness of each of the first sub-conductive layer 31 and the third sub-conductive layer 33.

Illustratively, in other embodiments of the present disclosure, the thickness D3 of the third sub-conductive layer 33 is less than or equal to one-half the thickness D1 of the first sub-conductive layer.

Illustratively, in other embodiments of the present disclosure, the thickness D3 of the third sub-conductive layer is greater than 0 angstroms and less than or equal to 150 angstroms.

By controlling the thickness D3 of the third sub-conductive layer 33 to be thinner, the third sub-conductive layer 33 is etched more easily, and the top protrusion phenomenon is not easy to occur. In addition, the third sub-conductive layer 33 may be protected by controlling the photoresist on the surface of the third sub-conductive layer 33, so that the etching speed of the third sub-conductive layer 33 is reduced, and thus, the recessing phenomenon is not easy to occur. Therefore, the uniformity of the etching morphology of the second sub-conductive layer 32 and the third sub-conductive layer 33 can be improved, and the yield of the product can be further improved.

Fig. 2 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, in which an electrical connection relationship between a pad and a pixel unit is shown.

Referring to fig. 2 in combination, the display panel may include a plurality of pixel units 5, the plurality of pixel units 5 being distributed in an array on the substrate 1, at least one of the pixel units including a light emitting diode 51, the light emitting diode 51 including a first electrode 511 and a second electrode 512. The display panel further comprises a plurality of pad pairs 6, the plurality of pad pairs 6 being located in the first conductive layer 3, at least one of the pad pairs 6 comprising a first pad 61 and a second pad 62, the first pad 61 being for electrical connection with the first electrode 511, the second pad 62 being for electrical connection with the second electrode 512.

In the novel display panel, as the pixel density is larger and larger, the space for carrying out signal wiring is smaller and smaller, the line width of the conductive wiring is narrower and narrower, the signal wiring is provided with enough conductive performance for keeping the signal wiring, so that the high-speed response speed is satisfied, the thickness of the conductive wiring needs to be thicker, the resistance of the conductive wiring is reduced, and the display panel is ensured to have a high corresponding speed.

Illustratively, in some embodiments of the present disclosure, the second sub-conductive layer has a thickness D2 of 1.8 microns or greater.

In a display panel, the first conductive layer, for example for wire routing, also needs a passivation layer for protection. Referring to fig. 1, a side of the first conductive layer 3 far from the substrate is covered with a layer of the second passivation layer 4, and the second passivation layer 4 may reduce corrosion of other processes, such as etching process, nickel-gold process, etc., on the first conductive layer in a subsequent process, so that in order to improve the protection effect of the second passivation layer 4 on the first conductive layer 3, the second passivation layer 4 needs to have sufficient wrapping property on the first conductive layer 3 to form a good bonding coverage. For example, the second passivation layer 4 may be prepared by a chemical vapor deposition method. When the first conductive layer 3 has a larger thickness, the second passivation layer 4 also needs to be correspondingly increased in thickness to match the thickness of the first conductive layer in order to achieve good coverage of the first conductive layer 3.

Illustratively, in some embodiments of the present disclosure, the ratio of the thickness D4 of the second passivation layer 4 to the thickness D3 of the third sub-conductive layer 33 is greater than 26.

Illustratively, in some embodiments of the present disclosure, the thickness D4 of the second passivation layer 4 is greater than the thickness D5 of the first passivation layer 2.

Illustratively, in some embodiments of the present disclosure, the second passivation layer 4 has a thickness D4 of 4000 angstroms or more and 6000 angstroms or less.

The second passivation layer 4 and the first passivation layer 2 may be manufactured by physical vapor deposition, chemical vapor deposition, spraying, sputtering, and the like, and materials of the second passivation layer 4 and the first passivation layer 2 may be the same or different. The first passivation layer 2 may be formed in one step by a single process, the first passivation layer 2 may be formed in several steps by a single process, and the first passivation layer 2 may be formed in several steps by different processes. Similarly, the second passivation layer 4 may be formed in a single process, the second passivation layer 4 may be formed in several steps in a single process, and the second passivation layer 4 may be formed in different steps in a different process.

Fig. 3 is a partial plan view of a display panel of some exemplary embodiments of the present disclosure, illustrating an orthographic projection relationship of a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer on a substrate base plate.

Referring to fig. 1 and 3 in combination, the display panel includes a first conductive layer 3, the first conductive layer 3 having a stacked structure, and the first conductive layer 3 includes a first sub-conductive layer 31, a second sub-conductive layer 32, and a third sub-conductive layer 33. The second sub-conductive layer 32 is located on a side of the first sub-conductive layer 31 remote from the substrate 1, wherein the orthographic projection of the second sub-conductive layer 32 onto the substrate 1 falls within the orthographic projection of the first sub-conductive layer 31 onto the substrate 1, and/or the third sub-conductive layer 33 is located on a side of the second sub-conductive layer 32 remote from the substrate 1, wherein the orthographic projection of the third sub-conductive layer 33 onto the substrate 1 falls within the orthographic projection of the second sub-conductive layer 32 onto the substrate 1.

With continued reference to fig. 1 and 3, the first sub-conductive layer 31 is located between the first passivation layer 2 and the second sub-conductive layer 32, and since the first sub-conductive layer 31 is made of a metal or alloy with relatively high thermal stability, such as metallic titanium (Ti), molybdenum (Mo), or niobium-molybdenum alloy (MoNb), the second sub-conductive layer 32 is generally made of a high-conductivity material such as metallic copper, aluminum, or the like, considering high requirements of the conductive performance, but such high-conductivity metals are generally poor in thermal stability. Therefore, the first sub-conductive layer 31 located between the second sub-conductive layer 32 and the first passivation layer 2 can prevent the second sub-conductive layer 32 from diffusing into the first passivation layer 2 and the semiconductor region located under the first passivation layer 2 during the manufacturing process of the display panel, thereby reducing the probability of occurrence of the transistor performance degradation. In order to achieve a better diffusion-preventing effect, it is generally designed that the orthographic projection of the second sub-conductive layer 32 on the substrate base plate 1 falls within the orthographic projection of the first sub-conductive layer 31 on the substrate base plate 1. The design can block the channel of the metal in the second sub-conductive layer 32 directly diffusing into the first passivation layer 2, reduce the probability of the metal in the second sub-conductive layer 32 diffusing into the semiconductor region, and better improve the stability of the display panel.

With continued reference to fig. 1 and 3, the third sub-conductive layer 33 is located on a side of the second sub-conductive layer 32 away from the substrate 1, and generally, the third sub-conductive layer 33 is made of a metal or alloy with high thermal stability similar to that of the first sub-conductive layer 31, so that the second sub-conductive layer 32 can be prevented from diffusing into other film layers, and the second sub-conductive layer 32 can be protected during etching or other processes. The orthographic projection of the third sub-conductive layer 33 on the substrate 1 falls within the orthographic projection of the second sub-conductive layer 32 on the substrate 1. When the local area needs to realize the direct electrical connection between the second sub-conductive layer 32 and other wires to meet the high-performance conduction, the local area of the third sub-conductive layer 33 may be opened to form an exposed local area of the second sub-conductive layer to realize the direct electrical connection with other wires.

Fig. 4 is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure, in which a second conductive layer is shown.

Referring to fig. 4 in combination, the display panel may further include a second conductive layer 7, and the second conductive layer 7 may have a single layer structure or a stacked structure similar to the first conductive layer 3, and the second sub-conductive layer 7 is located between the substrate 1 and the first passivation layer 2. Through designing double-layer conducting layers, such as the first conducting layer 3 and the second conducting layer 7 shown in fig. 4, the longitudinal space of the vertical substrate base plate can be fully utilized, the wiring layout can be designed more flexibly, the electric connection between the conducting layers and the grid electrode, the source electrode, the drain electrode, the pins of an external driving chip and the like of the transistor is realized, the wiring width in the conducting layers is further reduced, the pixel density of the display panel is improved, and the high resolution of the display panel is further realized.

Fig. 5 illustrates a schematic plan view of a display panel of some embodiments of the present disclosure, in which an electrical connection structure of a driving chip, terminals, conductive connection parts, and pads is shown.

The display panel can be controlled by the drive chip through the connection IC (integrated circuit). Referring to fig. 5 in combination, the display panel further includes a plurality of terminals 8, the plurality of terminals 8 being located in the first conductive layer 3, the plurality of terminals 8 being for electrical connection with pins 9 of a driving chip, and a plurality of conductive connection portions 10, the plurality of conductive connection portions 10 being located in the first conductive layer 3, at least one of the conductive connection portions 10 connecting at least one of the terminals 8 and a first pad 61 of at least one pad pair. The control of the driving chip to the pixel unit can be realized by the electrical connection between at least one of the pad pairs, at least one of the conductive connection parts 10, at least one of the terminals 8 and at least one of the pins of the driving chip, and the electrical connection between at least one of the pad pairs and the pixel unit, such as a light emitting diode, so as to realize different display effects.

Fig. 6 illustrates a schematic plan view of a display panel of other embodiments of the present disclosure, in which an electrical connection relationship between a first conductive layer and a second conductive layer and an electrical connection relationship between wires, conductive parts, terminals, and a driving chip are illustrated, and fig. 6 also illustrates an electrical connection relationship between a ground line and a first wire.

Referring to fig. 6 in combination, the display panel further comprises a plurality of traces 72, the plurality of traces 72 being located in the second conductive layer 7, vias 13 in the first passivation layer 2, and conductive portions 11 in the first conductive layer 3. One end of the conductive portion 11 is electrically connected to the second pad 62 of at least one pad pair, and at least one trace 72 is electrically connected to the conductive portion 11 through the via 13.

With continued reference to fig. 6, the display panel further includes a plurality of terminals including a first terminal 81, the first terminal 81 being configured to be electrically connected to a ground signal pin 91 of the driving chip, the display panel further includes a plurality of traces 72, the plurality of traces 72 including a first trace 721, the first trace 721 being configured to transmit a ground signal, the display panel further includes a plurality of vias 13, the plurality of vias 13 including a plurality of first vias 131, and the display panel further includes a conductive portion 11, the conductive portion 11 including the first conductive portion 111. The first wires 721 are electrically connected to the first conductive portions 111 through the first vias 131, the other ends of the first conductive portions 111 are electrically connected to the first terminals 81, and orthographic projections of the first vias 131 on the substrate 1 are arranged side by side in the first direction in orthographic projections of the first conductive portions 111 on the substrate 1.

With continued reference to fig. 6, the display panel further includes a ground line 14, the ground line 14 is located in the first conductive layer 3, the ground line 14 extends along a first direction, the display panel further includes a first trace 721, the first trace 721 extends along a second direction, the first direction and the second direction intersect, the display panel further includes a plurality of vias 13, the plurality of vias 13 includes a plurality of second vias 132, the first trace 721 is electrically connected to the ground line 14 through the plurality of second vias 132, and orthographic projections of the plurality of second vias 132 on the substrate 1 are arranged side by side in the first direction within orthographic projections of the ground line 14 on the substrate 1.

Fig. 7 illustrates a schematic plan view of a display panel of some embodiments of the present disclosure, in which an electrical connection relationship of a pixel, a terminal, a pad, and a conductive connection portion is illustrated.

Referring to fig. 7 in combination, the display panel includes a plurality of pixel units, a plurality of terminals and a plurality of pad pairs. Of the plurality of pixel units, at least one of the pixel units includes a first sub-pixel 52, a second sub-pixel 53, and a third sub-pixel, the first sub-pixel 52 includes a first light emitting diode 521, the second sub-pixel 53 includes a second light emitting diode 53l, and the third sub-pixel includes a third light emitting diode. The plurality of terminals further includes a second terminal 82, a third terminal 83, and a fourth terminal 84, the plurality of pad pairs includes a first pad pair 601, a second pad pair 602, and a third pad pair 603, the first pad and the second pad of the first pad pair 601 are for electrically connecting with the first electrode and the second electrode of the first light emitting diode 521, respectively, the first pad and the second pad of the second pad pair 602 are for electrically connecting with the first electrode and the second electrode of the second light emitting diode, respectively, and the first pad and the second pad of the third pad pair 603 are for electrically connecting with the first electrode and the second electrode of the third light emitting diode, respectively. The display panel further includes a conductive connection part 10, the conductive connection part 10 includes a first conductive connection part 101, a second conductive connection part 102, and a third conductive connection part 103, the second terminal 82 is electrically connected to the first pad of the first pad pair 601 through the first conductive connection part 101, the third terminal 83 is electrically connected to the first pad of the second pad pair 602 through the second conductive connection part 102, and the fourth terminal 84 is electrically connected to the first pad of the third pad pair 603 through the third conductive connection part 103.

Fig. 8 shows a schematic plan view of a display panel of other embodiments of the present disclosure, in which electrical connection relationships of wirings, conductive parts, pads, and light emitting diodes are shown.

Referring to fig. 8 in combination, a display panel includes a plurality of wires including a second wire 722 and a third wire 723, the second wire 722 for transmitting a first voltage signal to a first light emitting diode 521, and the third wire 723 for transmitting a second voltage signal to a second light emitting diode 531 and a third light emitting diode 541. The display panel further includes a plurality of vias including a third via 133 and a plurality of fourth vias 134, the conductive portion includes a second conductive portion 112 and a third conductive portion 113, the second trace 722 is electrically connected to one end of the second conductive portion 112 through the third via 133, the other end of the second conductive portion 112 is electrically connected to the second pad of the first pad pair 601, the third trace 723 is electrically connected to the third conductive portion 113 through the plurality of fourth vias 134, the third conductive portion 113 is electrically connected to both the second pad of the second pad pair 602 and the second pad of the third pad pair 603, and orthographic projections of the plurality of fourth vias 134 on the substrate 1 are arranged side by side in the orthographic projection of the third conductive portion 113 on the substrate 1 along the second direction.

The display panel can control the display effect through an IC driving chip, and can control the display effect through a low-temperature polysilicon technology LTPS (Low Temperature Poly-silicon) driving circuit, so that control of different pictures is realized.

Fig. 9 illustrates a schematic plan view of a display panel of other embodiments of the present disclosure, in which electrical connection relations between first and second voltage signal lines and pads, light emitting diodes are shown.

Referring to fig. 7 and 9 in combination, a display panel employing LTPS driving circuit control is exemplarily shown. Referring to fig. 7, the display panel includes a plurality of pixel units and a plurality of pad pairs, at least one of the pixel units includes a first sub-pixel 52 including a first light emitting diode 521, a second sub-pixel 53 including a second light emitting diode 531, and a third sub-pixel 54 including a third light emitting diode 541, the plurality of pad pairs includes a first pad pair 601, a second pad pair 602, and a third pad pair 603, the first pad and the second pad of the first pad pair 601 are for electrically connecting with a first electrode and a second electrode of the first light emitting diode 521, respectively, the first pad and the second pad of the second pad pair 602 are for electrically connecting with a first electrode and a second electrode of the second light emitting diode, respectively, and the first pad and the second pad of the third pad pair 603 are for electrically connecting with a first electrode and a second electrode of the third light emitting diode, respectively. Referring to fig. 9, the display panel includes a first voltage signal line V1 and a second voltage signal line V2 in a first conductive layer 3, a first pad of the first pad pair 601 is electrically connected to the first voltage signal line, a first pad of the second pad pair 602 and a first pad of the third pad pair 603 are each electrically connected to the second voltage signal line, and the first pad pair 601, the second pad pair 602 and the third pad pair are located between the first voltage signal line V1 and the second voltage signal line V2 in a first direction.

Illustratively, the display panel includes a first conductive layer 3, and referring to fig. 1, the first conductive layer 3 includes a first sub-conductive layer 31, a second sub-conductive layer 32, and a third sub-conductive layer 33, materials of the first sub-conductive layer 31 and the third sub-conductive layer 33 include a molybdenum-niobium alloy (MoNb), and materials of the second sub-conductive layer 32 include copper (Cu).

Fig. 10 illustrates a schematic structure diagram of a display panel of other embodiments of the present disclosure, in which a thickness ratio of a second passivation layer to a third sub-conductive layer is illustrated.

Referring to fig. 10 in combination, the present disclosure provides a display panel including a substrate 1, a first passivation layer 2 disposed on the substrate, a first conductive layer 3 disposed on a side of the first passivation layer 2 away from the substrate 1, and a second passivation layer 4 disposed on a side of the first conductive layer 3 away from the substrate 1. Referring to fig. 2 in combination, the display panel includes a plurality of pixel units 5, the plurality of pixel units 5 are distributed on the substrate board 1 in an array, at least one pixel unit 5 includes a light emitting diode 51, the light emitting diode includes a first electrode 511 and a second electrode 512, the display panel includes a plurality of pad pairs 6, the plurality of pad pairs 6 are located in the first conductive layer 3, at least one pad pair 6 includes a first pad 61 and a second pad 62, the first pad 61 is used for electrically connecting with the first electrode 511, the second pad 62 is used for electrically connecting with the second electrode 512, referring to fig. 10, the first conductive layer 3 has a laminated structure, the laminated structure of the first conductive layer includes a first sub-conductive layer 31, a second sub-conductive layer 32 and a third sub-conductive layer 33, the first sub-conductive layer 31 is located on a side of the first passivation layer 2 away from the substrate board 1, and the second sub-conductive layer 32 is located on a side of the first sub-conductive layer 31 away from the substrate board 32. The thickness of the second passivation layer 4 is D4, the thickness of the third sub-conductive layer 33 is D3, and the ratio of the thickness D4 of the second passivation layer 4 to the thickness D3 of the third sub-conductive layer 33 is greater than 26.

The LED light source can be used not only as a display pixel to manufacture a display panel but also as a backlight light source in the display panel, and then is combined with a light guide plate, a diffusion plate, a prism plate, a liquid crystal module, and the like to manufacture a display device.

Fig. 11 is a schematic structural view of other embodiments of the present disclosure, in which a backlight module is shown for use as a backlight source in a display device.

Referring to fig. 11 in combination, the present disclosure further provides a backlight module for use as a backlight source in a display device. The display device includes a backlight module 30, a light guide plate 31, a diffusion plate 32, a prism plate 33, and a liquid crystal module 34.

Fig. 12A illustrates a schematic structure of a backlight module according to other embodiments of the present disclosure, and fig. 12B illustrates a schematic plan view of a backlight module, wherein fig. 12B illustrates an electrical connection relationship between a light emitting unit and a pair of pads in the backlight module.

Referring to fig. 12A in combination, the backlight module 30 includes a plurality of film layers disposed on the substrate 1, for example, the film layers include a first passivation layer 2 disposed on the substrate 1, a first conductive layer 3 disposed on a side of the first passivation layer 2 away from the substrate, and a second passivation layer 4 disposed on a side of the first conductive layer 3 away from the substrate. The material of the substrate base plate 1 may include, but is not limited to, glass, quartz, plastic, silicon, polyimide, and the like.

With continued reference to fig. 12A, in the embodiment of the disclosure, the first conductive layer 3 is a stacked structure, and includes a first sub-conductive layer 31 located on a side of the first passivation layer 2 away from the substrate, a second sub-conductive layer 32 located on a side of the first sub-conductive layer 31 away from the substrate, and a third sub-conductive layer located on a side of the second sub-conductive layer 32 away from the substrate. The conductive member for connection with the light emitting diode or the driving chip may be located in the first conductive layer 3, and for example, the second sub-conductive layer 32 of the first conductive layer 3 may be a material having a high conductivity such as Cu. The materials of the first sub-conductive layer 31 and the third sub-conductive layer 33 are the same, the second sub-conductive layer 32 is different from the third sub-conductive layer 33, the thickness D3 of the third sub-conductive layer 33 is smaller than the thickness D1 of the first sub-conductive layer 31, and the thickness D2 of the second sub-conductive layer 32 is larger than the thickness of each of the first sub-conductive layer 31 and the third sub-conductive layer 33.

Referring to fig. 12B in combination, in some embodiments of the present disclosure, the backlight module 30 includes a plurality of light emitting units 20 distributed in an array on the substrate 1, at least one of the pixel units includes a light emitting diode 51, and the light emitting diode 51 includes a first electrode 511 and a second electrode 512. The backlight module further comprises a plurality of pad pairs 6, wherein the pad pairs 6 are located in the first conductive layer 3, at least one pad pair 6 comprises a first pad 61 and a second pad 62, the first pad 61 is used for being electrically connected with the first electrode 511, and the second pad 62 is used for being electrically connected with the second electrode 512.

Fig. 13 illustrates a schematic structure of a backlight module according to other embodiments of the present disclosure, in which a thickness relationship of a second conductive layer and a first conductive layer is illustrated.

Referring to fig. 13 in combination, the present disclosure provides another backlight module. The backlight module comprises a first conductive layer 3 and a second conductive layer 7, wherein the second conductive layer 7 is positioned on one side of the first passivation layer 2 close to the substrate 1. The thickness D6 of the second conductive layer is smaller than the thickness D7 of the first conductive layer.

Fig. 14A and 14B are respectively a display device according to an exemplary embodiment of the present disclosure.

Referring to fig. 14A in combination, a display device 200 is exemplarily provided according to an embodiment of the present disclosure, the display device 200 including any one of the display panels 100 described above.

Referring to fig. 14B in combination, another display device 200 is provided by way of example in an embodiment of the disclosure, where the display device 200 includes any of the backlight modules 30 described above.

Fig. 15 is a method of manufacturing a display panel according to an exemplary embodiment of the present disclosure. As shown in fig. 15, the method may include steps S01-S07.

It should be noted that some steps of the above manufacturing method may be performed alone or in combination, and may be performed in parallel or sequentially, and are not limited to the specific order of operations shown in the drawings.

In step S01, a substrate base 1 is provided;

In step S02, a first passivation layer 2 is formed on the substrate base 1;

In step S03, forming a first sub-conductive material layer 31 of a first conductive layer on a side of the first passivation layer 2 away from the substrate 1;

In step S04, forming a second sub-conductive material layer 32 of the first conductive layer on a side of the first sub-conductive material layer 31 away from the substrate base plate 1;

In step S05, forming a third sub-conductive material layer 33 of the first conductive layer on a side of the second sub-conductive material layer 32 away from the substrate 1;

Wherein the first sub-conductive material layer 31, the second sub-conductive material layer 32 and the third sub-conductive material layer 33 are collectively referred to as the first conductive material layer 3.

The first sub-conductive material layer and the third sub-conductive material layer are the same in material, the second sub-conductive material layer is different from the third sub-conductive material layer in material, the third sub-conductive material layer is smaller in thickness than the first sub-conductive material layer, and the second sub-conductive material layer is larger in thickness than each of the first sub-conductive material layer and the third sub-conductive material layer.

In step S06, a patterning process is performed on the first conductive material layer 3 to form a plurality of pad pairs 6, wherein at least one of the pad pairs includes a first pad for electrically connecting with a first electrode of a light emitting diode and a second pad for electrically connecting with a second electrode of the light emitting diode.

In step S07, a second passivation layer 4 is formed on a side of the plurality of pad pairs 6 remote from the substrate base plate 1.

Fig. 16 is a flowchart of a patterning process performed on a first conductive material layer according to an exemplary embodiment of the present disclosure. As shown in fig. 16, the method may include steps S061-S064.

In step S061, a photoresist layer is coated on the first conductive material layer;

in step S062, performing a pre-baking process on the photoresist layer;

exposing the photoresist layer in step S063;

In step S064, a post-bake process is performed on the photoresist layer,

In the post-baking process, the post-baking temperature is more than 130 ℃, and the post-baking time is more than 8 minutes.

By optimizing the post-baking temperature and the post-baking time in the patterning process in the first conductive material layer, the etching speed of the first sub-conductive material layer and the second sub-conductive material layer in the first conductive material layer in the etching process is close, the patterns of the first sub-conductive material layer and the second sub-conductive material layer after etching are ensured to be consistent, the retraction phenomenon or the top protrusion phenomenon cannot occur, and further the stability and the yield of products are improved.

In step S07, forming the second passivation layer 4 on the side of the plurality of pad pairs 6 away from the substrate 1 includes forming the second passivation layer 4 on the side of the plurality of pad pairs 6 away from the substrate 1 by a chemical vapor deposition process.

Through the chemical vapor deposition process, the bonding force between the second passivation layer 4 and the first conductive material layer 3 can be increased, the wrapping performance of the second passivation layer 4 on the first conductive material layer 3 is improved, the second passivation layer 4 plays a better protective role on the first conductive material layer, and the reliability of the display panel is further improved.

Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be provided in a variety of combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.

While the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. The scope of the disclosure should, therefore, not be limited to the above-described embodiments, but should be determined not only by the following claims, but also by the equivalents of the following claims.

Claims

1. An array substrate, characterized in that the array substrate comprises:

a substrate base;

a first passivation layer disposed on the substrate;

A first conductive layer disposed on a side of the first passivation layer away from the substrate base plate, and

A second passivation layer disposed on a side of the first conductive layer away from the substrate,

The array substrate comprises a plurality of array units which are distributed on the substrate in an array manner, at least one array unit comprises a light emitting diode, and the light emitting diode comprises a first electrode and a second electrode;

The display panel comprises a plurality of pad pairs, the plurality of pad pairs are positioned in the first conductive layer, at least one pad pair comprises a first pad and a second pad, the first pad is used for being electrically connected with the first electrode, and the second pad is used for being electrically connected with the second electrode;

The first conductive layer is provided with a laminated structure, the laminated structure of the first conductive layer comprises a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer is positioned on one side of the first passivation layer far away from the substrate, the second sub-conductive layer is positioned on one side of the first sub-conductive layer far away from the substrate, and the third sub-conductive layer is positioned on one side of the second sub-conductive layer far away from the substrate;

the first and third sub-conductive layers being of the same material, the second and third sub-conductive layers being of a different material, and

The third sub-conductive layer has a thickness less than the thickness of the first sub-conductive layer, and the second sub-conductive layer has a thickness greater than the thickness of each of the first sub-conductive layer and the third conductive layer.

2. The array substrate of claim 1, wherein the thickness of the third sub-conductive layer is less than or equal to one half of the thickness of the first sub-conductive layer.

3. The array substrate of claim 1 or 2, wherein the thickness of the third sub-conductive layer is greater than 0a and less than or equal to 150 a.

4. The array substrate of claim 1 or 2, wherein the second sub-conductive layer has a thickness of 1.8 μm or more.

5. The array substrate of claim 1 or 2, wherein a ratio of a thickness of the second passivation layer to a thickness of the third sub-conductive layer is greater than 26.

6. The array substrate of claim 5, wherein a thickness of the second passivation layer is greater than a thickness of the first passivation layer.

7. The array substrate of claim 5, wherein the second passivation layer has a thickness of 4000 angstroms or more and 6000 angstroms or less.

8. The array substrate according to claim 1 or 2, wherein the orthographic projection of the third sub-conductive layer on the substrate falls within the orthographic projection of the second sub-conductive layer on the substrate, and/or the orthographic projection of the second sub-conductive layer on the substrate falls within the orthographic projection of the first sub-conductive layer on the substrate.

9. The array substrate of claim 1 or 2, wherein the array substrate further comprises a second conductive layer on a side of the first passivation layer adjacent to the substrate, and

The second conductive layer has a thickness less than a thickness of the first conductive layer.

10. The array substrate of claim 1 or 2, wherein the array substrate further comprises a plurality of terminals in the first conductive layer, the plurality of terminals for electrically connecting with pins of a driving chip, and

The array substrate further comprises a plurality of conductive connecting parts, wherein the conductive connecting parts are positioned in the first conductive layer, and at least one conductive connecting part is electrically connected with at least one terminal and at least one first bonding pad.

11. The array substrate of claim 10, wherein the array substrate further comprises a plurality of traces in the second conductive layer;

The array substrate further comprises a via hole in the first passivation layer, a conductive part in the first conductive layer, and

One end of the conductive part is electrically connected with at least one second bonding pad, and at least one routing wire is electrically connected with the conductive part through the via hole.

12. The array substrate of claim 11, wherein the plurality of terminals includes a first terminal for electrically connecting with a ground signal pin of the driving chip;

The plurality of traces includes a first trace for transmitting a ground signal, and

The via holes comprise a plurality of first via holes, the conductive parts comprise first conductive parts, the first wiring is electrically connected with the first conductive parts through the first via holes, the other ends of the first conductive parts are electrically connected with the first terminals, and orthographic projections of the first via holes on the substrate are arranged in the orthographic projections of the first conductive parts on the substrate side by side along a first direction.

13. The array substrate of claim 12, wherein the array substrate further comprises a ground line in the first conductive layer, the ground line extending in a first direction, the first trace extending in a second direction, the first direction intersecting the second direction;

the via holes comprise a plurality of second via holes, the first routing wires are electrically connected with the grounding wires through the plurality of second via holes, and orthographic projections of the plurality of second via holes on the substrate are arranged in orthographic projections of the grounding wires on the substrate side by side along a first direction.

14. The array substrate of any one of claims 11-13, wherein the array unit is a pixel unit, at least one of the pixel units including a first sub-pixel including a first light emitting diode, a second sub-pixel including a second light emitting diode, and a third sub-pixel including a third light emitting diode;

The plurality of terminals further includes a second terminal, a third terminal, and a fourth terminal, the plurality of pad pairs including a first pad pair, a second pad pair, and a third pad pair, the first pad and the second pad of the first pad pair being for electrically connecting with the first electrode and the second electrode of the first light emitting diode, respectively, the first pad and the second pad of the second pad pair being for electrically connecting with the first electrode and the second electrode of the second light emitting diode, respectively, the first pad and the second pad of the third pad pair being for electrically connecting with the first electrode and the second electrode of the third light emitting diode, respectively, and

The conductive connecting part comprises a first conductive connecting part, a second conductive connecting part and a third conductive connecting part, the second terminal is electrically connected with the first bonding pad of the first bonding pad pair through the first conductive connecting part, the third terminal is electrically connected with the first bonding pad of the second bonding pad pair through the second conductive connecting part, and the fourth terminal is electrically connected with the first bonding pad of the third bonding pad pair through the third conductive connecting part.

15. The array substrate of claim 14, wherein the plurality of wires further comprises a second wire for transmitting a first voltage signal to the first light emitting diode and a third wire for transmitting a second voltage signal to the second light emitting diode and the third light emitting diode;

The via hole comprises a third via hole and a plurality of fourth via holes, the conductive part comprises a second conductive part and a third conductive part, the second routing wire is electrically connected with one end of the second conductive part through the third via hole, the other end of the second conductive part is electrically connected with the second bonding pad of the first bonding pad pair, the third routing wire is electrically connected with the third conductive part through the fourth via holes, the third conductive part is electrically connected with the second bonding pad of the second bonding pad pair and the third bonding pad of the third bonding pad pair, and orthographic projections of the fourth via holes on the substrate are arranged in orthographic projections of the third conductive part on the substrate side by side along the second direction.

16. The array substrate of claim 1 or 2, wherein the array unit is a pixel unit, at least one of the pixel units includes a first sub-pixel including a first light emitting diode, a second sub-pixel including a second light emitting diode, and a third sub-pixel including a third light emitting diode;

The plurality of pad pairs includes a first pad pair, a second pad pair and a third pad pair, the first pad and the second pad of the first pad pair are used for being respectively electrically connected with the first electrode and the second electrode of the first light emitting diode, the first pad and the second pad of the second pad pair are used for being respectively electrically connected with the first electrode and the second electrode of the second light emitting diode, the first pad and the second pad of the third pad pair are used for being respectively electrically connected with the first electrode and the second electrode of the third light emitting diode, and

The array substrate comprises a first voltage signal line and a second voltage signal line which are positioned in the first conductive layer, a first bonding pad of the first bonding pad pair is electrically connected with the first voltage signal line, a first bonding pad of the second bonding pad pair and a first bonding pad of the third bonding pad pair are electrically connected with the second voltage signal line, and the first bonding pad pair, the second bonding pad pair and the third bonding pad pair are positioned between the first voltage signal line and the second voltage signal line in a first direction.

17. The array substrate of claim 1 or 2, wherein the material of the first and third sub-conductive layers comprises MoNb and the material of the second sub-conductive layer comprises Cu.

18. An array substrate, characterized in that the array substrate comprises:

a substrate base;

a first passivation layer disposed on the substrate;

The array substrate comprises a plurality of pad pairs, the plurality of pad pairs are positioned in the first conductive layer, at least one pad pair comprises a first pad and a second pad, the first pad is used for being electrically connected with the first electrode, and the second pad is used for being electrically connected with the second electrode;

The first conductive layer has a laminated structure, the laminated structure of the first conductive layer comprises a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, the first sub-conductive layer is positioned on one side of the first passivation layer far away from the substrate, the second sub-conductive layer is positioned on one side of the first sub-conductive layer far away from the substrate, the third sub-conductive layer is positioned on one side of the second sub-conductive layer far away from the substrate, and

The ratio of the thickness of the second passivation layer to the thickness of the third sub-conductive layer is greater than 26.

19. A display device, wherein the display device comprises the array substrate of any one of claims 1-18.

20. The preparation method of the array substrate is characterized by comprising the following steps:

Providing a substrate;

Forming a first passivation layer on the substrate base plate;

forming a first conductive material layer on one side of the first passivation layer away from the substrate base plate;

Performing a patterning process on the first conductive material layer to form a plurality of pad pairs, wherein at least one of the pad pairs includes a first pad for electrically connecting with a first electrode of a light emitting diode and a second pad for electrically connecting with a second electrode of the light emitting diode, and

Forming a second passivation layer on a side of the plurality of pad pairs away from the substrate base plate,

Wherein the forming the first conductive material layer on the side of the first passivation layer away from the substrate base plate includes:

forming a first sub-conductive material layer on one side of the first passivation layer away from the substrate base plate;

forming a second sub-conductive material layer on the side of the first sub-conductive layer away from the substrate base plate, and

Forming a third sub-conductive material layer on one side of the second sub-conductive layer away from the substrate,

Wherein the first sub-conductive material layer and the third sub-conductive material layer are the same material, the second sub-conductive material layer is different from the third sub-conductive material layer, and

The third sub-conductive material layer has a thickness less than the thickness of the first sub-conductive material layer, and the second sub-conductive material layer has a thickness greater than the thickness of each of the first sub-conductive material layer and the third conductive material layer.

21. The method of claim 20, wherein the performing a patterning process on the first conductive material layer comprises:

coating a photoresist layer on the first conductive material layer;

performing a pre-baking process on the photoresist layer;

Exposing the photoresist layer;

performing a post-baking process on the photoresist layer,

22. The method of claim 20 or 21, wherein forming a second passivation layer on a side of the plurality of pad pairs remote from the substrate comprises forming a second passivation layer on a side of the plurality of pad pairs remote from the substrate by a chemical vapor deposition process.