CN119342872B

CN119342872B - Semiconductor device, power module, conversion circuit, vehicle and device manufacturing method

Info

Publication number: CN119342872B
Application number: CN202411885611.9A
Authority: CN
Inventors: 罗成志; 谢炜; 唐宇坤
Original assignee: Changfei Advanced Semiconductor Wuhan Co ltd
Current assignee: Changfei Advanced Semiconductor Wuhan Co ltd
Priority date: 2024-12-20
Filing date: 2024-12-20
Publication date: 2025-03-25
Anticipated expiration: 2044-12-20
Also published as: CN119342872A

Abstract

The present invention discloses a semiconductor device, a power module, a conversion circuit, a vehicle and a method for preparing the device, wherein the semiconductor device comprises: a semiconductor body, the semiconductor body comprises a substrate, an epitaxial layer, a well region, a first region and a second region, the semiconductor body is provided with a gate trench and a source trench, both of which extend from the first surface to the epitaxial layer; the second region is provided on the side of the source trench away from or close to the gate trench; the first region and the epitaxial layer are of the first doping type, the well region and the second region are of the second doping type; the gate structure is located in the gate trench; the source structure is located in the source trench; the drain is located on the side of the substrate away from the epitaxial layer. The semiconductor device provided by the present invention reduces the reverse conduction voltage drop of the semiconductor device, increases the leakage speed of the semiconductor device when it is reversely connected, and improves the performance stability and safety of the semiconductor device.

Description

Semiconductor device, power module, conversion circuit, vehicle and device manufacturing method

Technical Field

The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor device, a power module, a conversion circuit, a vehicle and a device manufacturing method.

Background

The silicon carbide groove device has the advantages of high current density, small cell pitch (CELL PITCH) and the like, and is widely applied. In the existing trench device, a PN junction parasitic diode exists between a source electrode and a drain electrode and is commonly used as a freewheeling diode, but when a positive voltage is connected to a source stage, the reverse conduction voltage drop is larger, and the stability and the reliability of the device are affected.

Disclosure of Invention

The invention provides a semiconductor device, a power module, a conversion circuit, a vehicle and a device manufacturing method, which can reduce the reverse conduction voltage drop of the semiconductor device, improve the leakage speed of the semiconductor device during reverse connection and improve the performance stability and safety of the semiconductor device.

In a first aspect, an embodiment of the present invention provides a semiconductor device, including:

The semiconductor body comprises a substrate, an epitaxial layer, a well region, a first region and a second region, wherein the epitaxial layer is positioned on one side of the substrate, the well region is arranged on one side of the epitaxial layer, which is far away from the substrate, the first region is arranged on one side of the well region, which is far away from the substrate, the surface of the first region, which is far away from one side of the substrate, is used as a first surface, a gate groove and a source groove are respectively arranged on the first surface, the gate groove and the source groove extend into the epitaxial layer from the first surface, the second region is arranged on one side of the source groove, which is far away from or close to the gate groove, the first region and the epitaxial layer are of a first doping type, and the well region and the second region are of a second doping type;

the grid structure is positioned in the grid groove;

the source electrode structure is positioned in the source electrode groove;

and the drain electrode is positioned on one side of the substrate away from the epitaxial layer.

Optionally, the second region is disposed on a side of the source trench away from the gate trench, the second region extends from the first surface into the epitaxial layer, and an orthographic projection of the second region on the bottom of the source trench covers at least a portion of the bottom of the source trench.

Optionally, the semiconductor body further comprises:

The first buried layer is arranged in the epitaxial layer at one side of the source electrode groove close to the gate electrode groove, and orthographic projection of the first buried layer on the side wall of the source electrode groove close to the gate electrode groove is not overlapped with orthographic projection of the well region and the first region on the side wall of the source electrode groove close to the gate electrode groove.

Optionally, the second region is disposed on a side of the source trench near the gate trench, and extends from the first surface into the epitaxial layer, and an orthographic projection of the second region on the bottom of the source trench covers at least a portion of the bottom of the source trench.

Optionally, the semiconductor body further comprises:

the second buried layer is arranged in the epitaxial layer at one side of the source electrode groove far away from the gate electrode groove, and orthographic projection of the second buried layer on the side wall of the source electrode groove far away from the gate electrode groove is not overlapped with orthographic projection of the well region and the first region on the side wall of the source electrode groove far away from the gate electrode groove.

Optionally, the source structure includes a first insulating layer and a trench source;

the first insulating layer is arranged on the inner wall and the bottom of the source electrode groove;

the trench source is arranged in the source trench at one side of the first insulating layer, wherein the length of the trench source in the extending direction of the source trench is larger than the depth of the source trench.

Optionally, the semiconductor device further includes:

The second insulation layer is arranged on one side of the first surface far away from the grid structure, and orthographic projection of the second insulation layer on the first surface covers the grid structure;

And the ohmic contact metal layer is positioned on one side of the second insulating layer far away from the gate structure, and is electrically connected with the first region, and the metal material of the ohmic contact metal layer comprises titanium.

In a second aspect, an embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device according to any embodiment of the present invention, where the substrate is used to carry the semiconductor device.

In a third aspect, embodiments of the present invention provide a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction;

The power conversion circuit comprises a circuit board and at least one semiconductor device according to any embodiment of the present invention, wherein the semiconductor device is electrically connected to the circuit board.

In a fourth aspect, an embodiment of the present invention provides a vehicle, including a load and the power conversion circuit according to any embodiment of the present invention, where the power conversion circuit is configured to convert ac power into dc power, convert ac power into ac power, convert dc power into dc power, or convert dc power into ac power, and then input the dc power into the load.

In a fifth aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:

The method comprises the steps of providing a semiconductor body, wherein the semiconductor body comprises a substrate, an epitaxial layer, a well region, a first region and a second region, the epitaxial layer is located on one side of the substrate, the well region is arranged on one side of the epitaxial layer, which is far away from the substrate, the first region is arranged on one side of the well region, which is far away from the substrate, the surface of the first region, which is far away from the substrate, is used as a first surface, a gate groove and a source groove are respectively arranged on the first surface, the gate groove and the source groove extend into the epitaxial layer from the first surface, the second region is arranged on one side of the source groove, which is far away from or close to the gate groove, the first region and the epitaxial layer are of a first doping type, and the well region and the second region are of a second doping type;

Forming a gate structure in the gate trench;

forming a source electrode structure in the source electrode groove;

And forming a drain electrode on one side of the substrate away from the epitaxial layer.

Optionally, in a case that the second region is disposed on a side of the source trench away from the gate trench, the second region extends from the first surface into the epitaxial layer, and an orthographic projection of the second region on a bottom of the source trench covers at least a portion of the bottom of the source trench.

Optionally, the semiconductor body further includes a first buried layer;

The preparation method further comprises the following steps:

And forming the first buried layer in the epitaxial layer at one side of the source electrode groove close to the gate electrode groove, wherein the orthographic projection of the first buried layer on the side wall of the source electrode groove close to the gate electrode groove is not overlapped with the orthographic projection of the well region and the first region on the side wall of the source electrode groove close to the gate electrode groove.

Optionally, in the case that the second region is disposed on a side of the source trench near the gate trench, the second region extends from the first surface into the epitaxial layer, and an orthographic projection of the second region on the bottom of the source trench covers at least a portion of the bottom of the source trench.

Optionally, the semiconductor body further includes a second buried layer;

The preparation method further comprises the following steps:

And forming the second buried layer in the epitaxial layer at one side of the source electrode groove far away from the gate electrode groove, wherein the orthographic projection of the second buried layer on the side wall of the source electrode groove far away from the gate electrode groove is not overlapped with the orthographic projection of the well region and the first region on the side wall of the source electrode groove far away from the gate electrode groove.

Optionally, forming a source structure in the source trench includes:

forming a first insulating layer on the inner wall and the bottom of the source electrode groove;

and forming a groove source electrode in the source electrode groove on one side of the first insulating layer, wherein the length of the groove source electrode in the extending direction of the source electrode groove is larger than the depth of the source electrode groove.

Optionally, the semiconductor device further includes an ohmic contact metal layer and a second insulating layer;

The preparation method further comprises the following steps:

Forming a second insulating layer on one side of the first surface far away from the gate structure, wherein the orthographic projection of the second insulating layer on the first surface covers the gate structure;

And forming the ohmic contact metal layer on one side of the second insulating layer far away from the gate structure, wherein the ohmic contact metal layer is electrically connected with the first region, and the metal material of the ohmic contact metal layer comprises titanium.

The semiconductor device provided by the technical scheme comprises a semiconductor body, an epitaxial layer, a well region, a first region and a second region, wherein the semiconductor body comprises a substrate, the epitaxial layer is located on one side of the substrate, the well region is arranged on one side of the epitaxial layer away from the substrate, the first region is arranged on one side of the well region away from the substrate, the surface of the first region away from one side of the substrate serves as a first surface, a gate groove and a source groove are respectively arranged on the first surface, the gate groove and the source groove extend into the epitaxial layer from the first surface, the second region is arranged on one side of the source groove away from or close to the gate groove, the gate structure is located in the gate groove, the source structure is located in the source groove, and the drain electrode is located on one side of the substrate away from the epitaxial layer. The first region and the epitaxial layer are of a first doping type, the well region and the second region are of a second doping type, and a PN junction parasitic diode can be formed between the second region and the epitaxial layer and used as a freewheeling diode due to the fact that the doping types of the second region and the epitaxial layer are different. Furthermore, PNP or NPN triode is formed among the epitaxial layer, the well region and the first region on one side of the source electrode groove close to the gate electrode groove and is used as a freewheel triode. Therefore, when the source stage is connected with positive voltage, the freewheeling diode can be conducted, the source electrode structure is used as the control electrode of the freewheeling triode, and the freewheeling triode can also be conducted. Through integrating the freewheel diode and the freewheel triode, the reverse connection freewheel channel of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the bleeder speed of the semiconductor device during reverse connection is improved, and the performance stability and the safety of the semiconductor device are improved.

Drawings

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;

fig. 5 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

Fig. 6 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present invention;

Fig. 7 to 13 are schematic views showing intermediate structures of the preparation process according to the embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, referring to fig. 1, including:

The semiconductor body 100 comprises a substrate 10, an epitaxial layer 20, a well region 30, a first region 40 and a second region 50, wherein the epitaxial layer 20 is positioned on one side of the substrate 10, the well region 30 is arranged on one side of the epitaxial layer 20 away from the substrate 10, the first region 40 is arranged on one side of the well region 30 away from the substrate 10, the surface of one side of the first region 40 away from the substrate 10 is used as a first surface, a gate trench 70 and a source trench 60 are respectively arranged on the first surface, the gate trench 70 and the source trench 60 extend into the epitaxial layer 20 from the first surface, the second region 50 is arranged on one side of the source trench 60 away from or close to the gate trench 70, the first region 40 and the epitaxial layer 20 are of a first doping type, and the well region 30 and the second region 50 are of a second doping type;

a gate structure located within the gate trench 70;

a source structure located within the source trench 60;

And a drain electrode 110 on a side of the substrate 10 remote from the epitaxial layer 20.

Specifically, the material of the substrate 10 and the material of the epitaxial layer 20 may be the same or different, and illustratively, the material of the substrate 10 and the epitaxial layer 20 may include silicon or silicon carbide. The semiconductor device in the embodiment of the invention can be a silicon carbide trench metal oxide semiconductor field effect Transistor (Metal Oxide Semiconductor FIELD EFFECT Transistor, MOSFET). In the embodiment of the invention, the first doping type may be N-type doping, the second doping type may be P-type doping, or the first doping type may be P-type doping, and the second doping type may be N-type doping. P+ and N+ shown in the drawing indicate that the ion doping concentration of the region is high, and P-, N-indicate that the ion doping concentration of the region is low. Wherein, the N-type doping ion can be P (phosphorus) or N (nitrogen) ion, and the P-type doping ion can be Al (aluminum) ion or B (boron) ion. For example, in the embodiment of the present invention, the first doping type is N-type doping, the second doping type is P-type doping, and when the semiconductor device is an N-type device, the substrate 10 is n+ type doping, for example, may be an n+ silicon carbide substrate 10, the epitaxial layer 20 is N-type doping, for example, may be an N-silicon carbide epitaxial layer 20, and when the semiconductor device is a P-type device, the substrate 10 is p+ type doping, and the epitaxial layer 20 is P-type doping.

An epitaxial layer 20 is formed on a side of the substrate 10, a well region 30 is provided on a side of the epitaxial layer 20 remote from the substrate 10, and a first region 40 is provided on a side of the well region 30 remote from the substrate 10. Wherein the well region 30 is of the second doping type and the first region 40 is of the first doping type. The well region 30 and the first region 40 are used to form a conductive channel of the semiconductor device, and the well region 30 and the first region 40 may be formed by epitaxial growth, ion implantation, vapor deposition, or the like.

The gate trench 70 and the source trench 60 are formed on the first surface by an etching process, wherein the gate trench 70 and the source trench 60 may be simultaneously etched in the same manufacturing process. In other embodiments, the gate trench 70 and the source trench 60 are set to different depths, so that the gate trench 70 and the source trench 60 need to be formed by step etching in different manufacturing processes, and the depth of the source trench 60 may be 1.2-2.5 μm, and the depth of the gate trench 70 may be 0.7-1.2 μm, so that the device can stably operate at a higher voltage by optimizing on-resistance and improving breakdown voltage of the semiconductor device while ensuring device performance by selecting appropriate depths of the source trench 60 and the gate trench 70. The gate trench 70 and the source trench 60 extend from the first surface to the epitaxial layer 20 through the first region 40 and the well region 30. The source trench 60 is located at one side of the gate trench 70, and the source trench 60 may be a ring-shaped trench disposed in a structure surrounding the gate trench 70. The source trenches 60 may also be independent trenches, and a plurality of source trenches 60 are distributed on two sides of the gate trench 70, for example, in fig. 1, the source trenches 60 are disposed on two sides of the gate trench 70, and the two source trenches 60 may be disposed symmetrically or asymmetrically. The second region 50 is formed by ion implantation on the side of the source trench 60 remote from the gate trench 70.

A gate structure is disposed in the gate trench 70 and a source structure is disposed in the source trench 60. Illustratively, the gate structure may include a first insulating layer 71 and a trench gate 72, the first insulating layer 71 is disposed on the inner wall and bottom of the gate trench 70, the first insulating layer 71 may be a gate oxide layer, the gate oxide layer may be a high dielectric constant (K) material, the trench gate 72 may be a polysilicon layer, the gate structure is disposed in the gate trench 70, the well regions 30 on both sides of the gate structure may form vertical conductive channels, and Junction Field Effect Transistor (JFET) regions may be eliminated, so that on-resistance of the semiconductor device is lower.

The source structure may include a first insulating layer 71 and a trench source 62, the first insulating layer 71 being disposed at an inner wall and a bottom of the source trench 60, the trench source 62 may be a polysilicon layer, and the first insulating layer 71 in the source structure may be the same as the first insulating layer 71 in the gate structure. Therefore, at the time of preparation, the first insulating layer 71 in the source structure and the first insulating layer 71 in the gate structure may be formed simultaneously. The source structure is disposed in the source trench 60, the second region 50 is disposed on a side of the source trench 60 away from the gate trench 70, that is, the second region 50 is disposed on a side of the source structure away from the gate structure, and the doping type of the second region 50 is the same as that of the well region 30, so that a depletion region can be formed between the second region 50 and the epitaxial layer 20, which can play a role in shielding an electric field of the gate structure, thereby improving the breakdown problem of the gate oxide layer and ensuring the reliability of the device. Also, since the doping types of the second region 50 and the epitaxial layer 20 are different, a PN junction parasitic diode may be formed between the second region 50 and the epitaxial layer 20 to serve as the flywheel diode 102. Further, since the second region 50 is not provided at a side of the source trench 60 close to the gate trench 70, a PNP or NPN transistor is formed between the epitaxial layer 20, the well region 30, and the first region 40 at a side of the source trench 60 close to the gate trench 70, and serves as the freewheeling transistor 101. Therefore, the freewheeling diode 102 and the freewheeling transistor 101 are integrated on two sides of the source trench, the source metal layer 120 is electrically connected with the source structure, the source metal layer 120 is used as a source of the semiconductor device, and when the source is connected with a positive voltage, the freewheeling diode 102 can be turned on. When the source is connected to a positive voltage, the source structure is used as a control electrode of the freewheeling triode 101, and the freewheeling triode 101 can be conducted. By integrating the flywheel diode 102 and the flywheel triode 101, the reverse connection flywheel path of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the current leakage speed of the semiconductor device during reverse connection is improved, and the performance stability and the safety of the semiconductor device are improved.

In some embodiments, the second region 50 may also be disposed on a side of the source trench 60 near the gate trench 70, and fig. 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention, and referring to fig. 2, the doping type of the second region 50 is the same as that of the well region 30, and similarly, the second region 50 may also function as a shielding function for the electric field of the gate structure. A freewheeling diode 102 is provided between the second region 50 and the epitaxial layer 20 on the side of the source trench 60 adjacent to the gate trench 70. A PNP or NPN freewheeling transistor 101 is formed between the epitaxial layer 20, the well region 30, and the first region 40 on the side of the source trench 60 remote from the gate trench 70. The method can also play a role in increasing the reverse connection follow current path of the semiconductor device, reducing the reverse connection voltage drop of the semiconductor device and improving the leakage speed of the semiconductor device during reverse connection.

The semiconductor device provided by the technical scheme provided by the embodiment of the invention comprises a semiconductor body 100, wherein the semiconductor body 100 comprises a substrate 10, an epitaxial layer 20, a well region 30, a first region 40 and a second region 50, the epitaxial layer 20 is located on one side of the substrate 10, the well region 30 is located on one side of the epitaxial layer 20 away from the substrate 10, the first region 40 is located on one side of the well region 30 away from the substrate 10, the surface of one side of the first region 40 away from the substrate 10 is used as a first surface, a gate groove 70 and a source groove 60 are respectively arranged on the first surface, the gate groove 70 and the source groove 60 extend into the epitaxial layer 20 from the first surface, the second region 50 is located on one side of the source groove 60 away from or close to the gate groove 70, a gate structure is located in the gate groove 70, a source structure is located in the source groove 60, and a drain 110 is located on one side of the substrate 10 away from the epitaxial layer 20. The first region 40 and the epitaxial layer 20 are of a first doping type, the well region 30 and the second region 50 are of a second doping type, and a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20 to serve as the freewheeling diode 102 due to the different doping types of the second region 50 and the epitaxial layer 20. Further, since the second region 50 is not disposed on the side of the source trench 60 near the gate trench 70, a PNP or NPN transistor is formed between the epitaxial layer 20, the well region 30 and the first region 40, and is used as the freewheeling transistor 101. Therefore, when the source is connected to the positive voltage, the freewheeling diode 102 may be turned on, and the source structure may be used as the control electrode of the freewheeling triode 101, so that the freewheeling triode 101 may also be turned on. By integrating the flywheel diode 102 and the flywheel triode 101, the reverse connection flywheel path of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the current leakage speed of the semiconductor device during reverse connection is improved, and the performance stability and the safety of the semiconductor device are improved.

In some embodiments, the second region 50 is disposed on a side of the source trench 60 away from the gate trench 70, the second region 50 extends from the first surface into the epitaxial layer 20, and an orthographic projection of the second region 50 at the bottom of the source trench 60 covers at least a portion of the bottom of the source trench 60.

With continued reference to fig. 1, specifically, the second region 50 may be formed on a side of the source trench 60 by ion implantation, so that the second region 50 is distributed on a side of the source trench 60 away from the gate trench 70, and in this embodiment, the second region 50 is distributed on a side of the source trench 60 away from the gate trench 70, and a PN junction parasitic diode may be formed between the second region 50 and the epitaxial layer 20 and used as the freewheeling diode 102. The orthographic projection of the second region 50 on the bottom of the source trench 60 covers at least a portion of the bottom of the source trench 60, that is, the second region 50 may at least partially cover the bottom of the source trench 60, or entirely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and further increasing the electric field of the shield gate structure.

Fig. 3 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention, and referring to fig. 3, the semiconductor body 100 further includes a first buried layer 80 disposed in the epitaxial layer 20 on a side of the source trench 60 close to the gate trench 70, wherein an orthographic projection of the first buried layer 80 on a sidewall of the source trench 60 close to the gate trench 70 does not overlap with an orthographic projection of the well region 30 and the first region 40 on a sidewall of the source trench 60 close to the gate trench 70.

Specifically, the semiconductor device shown in fig. 1 is different in that the first buried layer 80 is disposed in the epitaxial layer 20 on the side of the source trench 60 close to the gate trench 70, the first buried layer 80 may be formed by ion implantation, and the doping type of the first buried layer 80 is the same as that of the second region 50. Illustratively, in forming the epitaxial layer 20, the first buried layer 80 may be formed by ion implantation, and the source trench 60 may be formed according to a position of the first buried layer 80 such that the first buried layer 80 is distributed on a side of the source trench 60 adjacent to the gate trench 70. The first buried layer 80 may also cover the bottom of the source trench 60, so as to be disposed adjacent to the second region 50 at the bottom of the source trench 60, and further improve the effect of shielding the electric field of the gate structure. The first buried layer 80 may extend along a sidewall of the source trench 60 in a direction pointing to the first region 40, but the first buried layer 80 is not in contact with the first region 40 and the well region 30, so as to avoid blocking a channel of the freewheeling transistor 101.

In some embodiments, the second region 50 is disposed on a side of the source trench 60 adjacent to the gate trench 70, the second region 50 extends from the first surface into the epitaxial layer 20, and an orthographic projection of the second region 50 at the bottom of the source trench 60 covers at least a portion of the bottom of the source trench 60.

With continued reference to fig. 2, specifically, the second region 50 may be formed on a side of the source trench 60 by ion implantation, so that the second region 50 is distributed on a side of the source trench 60 close to the gate trench 70, and in an embodiment of the present invention, the second region 50 is distributed on a side of the source trench 60 close to the gate trench 70, and a PN junction parasitic diode may be formed between the second region 50 and the epitaxial layer 20, and may be used as the freewheeling diode 102. The orthographic projection of the second region 50 on the bottom of the source trench 60 covers at least a portion of the bottom of the source trench 60, that is, the second region 50 may at least partially cover the bottom of the source trench 60, or entirely cover the bottom of the source trench 60, so as to increase the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and the side of the second region 50 near the gate trench 70 may further increase the electric field of the shielding gate structure.

Fig. 4 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention, referring to fig. 4, specifically, the semiconductor device is different from the semiconductor device shown in fig. 2in that a second buried layer 90 is disposed in the epitaxial layer 20 on a side of the source trench 60 away from the gate trench 70, the second buried layer 90 may be formed by ion implantation, and the doping type of the second buried layer 90 is the same as that of the second region 50. Illustratively, in forming the epitaxial layer 20, the second buried layer 90 may be formed by ion implantation, and the source trench 60 may be formed according to the position of the second buried layer 90, such that the second buried layer 90 is distributed on a side of the source trench 60 adjacent to the gate trench 70. The second buried layer 90 may also cover the bottom of the source trench 60, so as to be disposed adjacent to the second region 50 at the bottom of the source trench 60, and further improve the effect of shielding the electric field of the gate structure. The first buried layer 80 may extend along a sidewall of the source trench 60 in a direction pointing to the first region 40, but the first buried layer 80 is not in contact with the first region 40 and the well region 30, so as to avoid blocking a channel of the freewheeling transistor 101.

Based on the above embodiment, the source structure may optionally include a first insulating layer 71 and a trench source 62, the first insulating layer 71 being disposed on an inner wall and a bottom of the source trench 60, the trench source 62 being disposed in the source trench 60 on one side of the first insulating layer 71, wherein a length of the trench source 62 in an extending direction of the source trench 60 is greater than a depth of the source trench 60.

Specifically, the first insulating layer 71 is disposed on the inner wall and bottom of the source trench 60, the trench source 62 may be a polysilicon layer, and the first insulating layer 71 in the source structure is the same as the first insulating layer 71 in the gate structure. Therefore, during the preparation, the first insulating layer 71 in the source electrode structure and the first insulating layer 71 in the gate electrode structure may be formed simultaneously, then a polysilicon layer is deposited, and then the entire polysilicon layer is etched back, so that 200-500nm remains on the first surface of the polysilicon layer, then the polysilicon layer in the source electrode trench 60 is protected by using the photoresist, and then the etching back is continued, so that the polysilicon layer is filled in the gate electrode trench 70, and the deposition height of the polysilicon layer in the source electrode trench 60 is greater than the depth of the source electrode trench 60. That is, the polysilicon layer forms a protruding portion beyond the plane of the first surface, so that when the source metal layer 120 is formed on the first surface, the protruding portion is located inside the source metal layer 120, thereby increasing the contact area between the polysilicon layer and the source metal layer 120, which is beneficial to increasing the voltage sensitivity of the control electrode of the freewheeling triode 101 and controlling the conduction process of the freewheeling triode 101. By way of example, the protruding portion may be cylindrical, trapezoidal, conical, or other regular or irregular shape, capable of increasing the contact area between the polysilicon layer and the source metal layer 120.

Referring to fig. 1-4, the semiconductor device further includes a second insulating layer 130 disposed on a side of the first surface remote from the gate structure, wherein an orthographic projection of the second insulating layer 130 on the first surface covers the gate structure;

The ohmic contact metal layer 140 is located at a side of the second insulating layer 130 away from the gate structure, the ohmic contact metal layer 140 is electrically connected with the first region 40, and the metal material of the ohmic contact metal layer 140 includes titanium.

Specifically, a second insulating layer 130 is formed on the surface of the first region 40 away from the substrate 10, the second insulating layer 130 may be an interlayer dielectric layer (INTER LAYER DIELECTRIC, ILD), the second insulating layer 130 may cover the surface of the gate structure, an ohmic contact metal layer 140 is disposed on one side of the second insulating layer 130 away from the gate structure, a source metal layer 120 is formed on the surface of the ohmic contact metal layer 140 away from the substrate 10, and the second insulating layer 130 isolates the gate structure from the source metal layer 120. The ohmic contact metal layer 140 is electrically connected with the trench source electrode 62, and when the ohmic contact metal layer 140 is in contact with the trench source electrode 62, the resistance of the contact surface is very small, so that the current-voltage relationship is linear, and no obvious additional impedance is generated. The good ohmic contact can significantly reduce the contact resistance between the source and the trench source 62, thereby improving the conduction efficiency of the device. The ohmic contact metal of the ohmic contact metal layer 140 may be nickel (Ni), but Ni is easily reacted with the polysilicon layer to lower the reliability of the device, so that the ohmic contact metal may be titanium (Ti), for example, ti is used as the ohmic contact metal, the ohmic contact metal layer 140 does not react with the polysilicon layer, and the ohmic contact metal layer 140 has a contact connection with the first region 40, and when the first region 40 is n+ doped, the contact resistance between the titanium and the first region 40 may be lower, so that the reverse conduction voltage drop of the freewheeling triode 101 may be reduced.

The embodiment of the invention provides a power module based on the embodiment, which comprises a substrate and the semiconductor device of any embodiment of the invention, wherein the substrate is used for bearing the semiconductor device.

The power module provided by the technical scheme of the embodiment of the invention has the same beneficial effects as the semiconductor device of any embodiment of the invention.

The embodiment of the invention provides a power conversion circuit which is used for one or more of current conversion, voltage conversion and power factor correction on the basis of the embodiment, wherein the power conversion circuit comprises a circuit board and at least one semiconductor device according to any embodiment of the invention, and the semiconductor device is electrically connected with the circuit board.

The power conversion circuit provided by the technical scheme of the embodiment of the invention has the same beneficial effects as the semiconductor device of any embodiment of the invention.

The embodiment of the invention provides a vehicle which comprises a load and the power conversion circuit according to any embodiment of the invention, wherein the power conversion circuit is used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current or converting direct current into alternating current and then inputting the alternating current into the load.

The embodiment of the present invention provides a method for manufacturing a semiconductor device on the basis of the above embodiment, and fig. 5 is a flowchart of the method for manufacturing a semiconductor device provided by the embodiment of the present invention, and referring to fig. 5, the method for manufacturing a semiconductor device includes:

S110, providing a semiconductor body 100, wherein the semiconductor body 100 comprises a substrate 10, an epitaxial layer 20, a well region 30, a first region 40 and a second region 50, the epitaxial layer 20 is positioned on one side of the substrate 10, the well region 30 is arranged on one side of the epitaxial layer 20 away from the substrate 10, the first region 40 is arranged on one side of the well region 30 away from the substrate 10, the surface of one side of the first region 40 away from the substrate 10 is used as a first surface, a gate trench 70 and a source trench 60 are respectively arranged on the first surface, the gate trench 70 and the source trench 60 extend into the epitaxial layer 20 from the first surface, the second region 50 is arranged on one side of the source trench 60 away from or close to the gate trench 70, the first region 40 and the epitaxial layer 20 are of a first doping type, and the well region 30 and the second region 50 are of a second doping type;

wherein the material of the substrate 10 and the material of the epitaxial layer 20 may be the same or different, the material of the substrate 10 and the epitaxial layer 20 may include silicon or silicon carbide, for example. The semiconductor device in the embodiment of the invention can be a silicon carbide trench metal oxide semiconductor field effect Transistor (Metal Oxide Semiconductor FIELD EFFECT Transistor, MOSFET). In the embodiment of the invention, the first doping type may be N-type doping, the second doping type may be P-type doping, or the first doping type may be P-type doping, and the second doping type may be N-type doping. P+ and N+ shown in the drawing indicate that the ion doping concentration of the region is high, and P-, N-indicate that the ion doping concentration of the region is low. Wherein, the N-type doping ion can be P (phosphorus) or N (nitrogen) ion, and the P-type doping ion can be Al (aluminum) ion or B (boron) ion. For example, in the embodiment of the present invention, the first doping type is N-type doping, the second doping type is P-type doping, and when the semiconductor device is an N-type device, the substrate 10 is n+ type doping, for example, may be an n+ silicon carbide substrate 10, the epitaxial layer 20 is N-type doping, for example, may be an N-silicon carbide epitaxial layer 20, and when the semiconductor device is a P-type device, the substrate 10 is p+ type doping, and the epitaxial layer 20 is P-type doping.

Specifically, the epitaxial layer 20 is formed on one side of the substrate 10, the well region 30 is disposed on the side of the epitaxial layer 20 away from the substrate 10, and the first region 40 is disposed on the side of the well region 30 away from the substrate 10. Wherein the well region 30 is of the second doping type and the first region 40 is of the first doping type. The well region 30 and the first region 40 are used to form a conductive channel of the semiconductor device, and the well region 30 and the first region 40 may be formed by epitaxial growth, ion implantation, vapor deposition, or the like. The surface of the first region 40 on the side away from the substrate 10 is used as a first surface, and the gate trench 70 and the source trench 60 are formed on the first surface through an etching process, wherein the gate trench 70 and the source trench 60 may be simultaneously etched in the same manufacturing process. Illustratively, in some embodiments, the depths of the gate trench 70 and the source trench 60 are different, so that the gate trench 70 and the source trench 60 are formed by step etching in different manufacturing processes, for example, the depth of the source trench 60 may be 1.2-2.5 μm, and the depth of the gate trench 70 may be 0.7-1.2 μm, so that the device can stably operate at a higher voltage by optimizing on-resistance while ensuring device performance and improving breakdown voltage of the semiconductor device by selecting appropriate depths of the source trench 60 and the gate trench 70. The gate trench 70 and the source trench 60 extend from the first surface to the epitaxial layer 20 through the first region 40 and the well region 30. The source trench 60 is located at one side of the gate trench 70, and the source trench 60 may be a ring-shaped trench disposed in a structure surrounding the gate trench 70. The source trenches 60 may also be independent trenches, and a plurality of source trenches 60 are distributed on two sides of the gate trench 70, and the source trenches 60 are disposed on two sides of the gate trench 70 in the illustrated embodiment, and the two source trenches 60 may be disposed symmetrically or asymmetrically. The second region 50 is formed by ion implantation on the side of the source trench 60 remote from the gate trench 70.

Alternatively, referring to fig. 1, in the case where the second region 50 is disposed on a side of the source trench 60 remote from the gate trench 70, the second region 50 extends from the first surface into the epitaxial layer 20, and an orthographic projection of the second region 50at the bottom of the source trench 60 covers at least a portion of the bottom of the source trench 60. That is, the second region 50 may at least partially cover the bottom of the source trench 60, or entirely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and further increasing the electric field to the shield gate structure.

Referring to fig. 2, the second region 50 may also be disposed on a side of the source trench 60 adjacent to the gate trench 70. Alternatively, where the second region 50 is disposed on a side of the source trench 60 adjacent to the gate trench 70, the second region 50 extends from the first surface into the epitaxial layer 20, and an orthographic projection of the second region 50 at the bottom of the source trench 60 covers at least a portion of the bottom of the source trench 60. That is, the second region 50 may at least partially cover the bottom of the source trench 60 or entirely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and the second region 50 near the side of the gate trench 70 may be further increased to shield the electric field of the gate structure.

S120, forming a grid structure in the grid groove;

Specifically, a gate structure is disposed in the gate trench 70, and a source structure is disposed in the source trench 60. Illustratively, the gate structure may include a first insulating layer 71 and a trench gate 72, the first insulating layer 71 is disposed on the inner wall and bottom of the gate trench 70, the first insulating layer 71 may be a gate oxide layer, the gate oxide layer may be a high dielectric constant (K) material, the trench gate 72 may be a polysilicon layer, the gate structure is disposed in the gate trench 70, the well regions 30 on both sides of the gate structure may form vertical conductive channels, and Junction Field Effect Transistor (JFET) regions may be eliminated, so that on-resistance of the semiconductor device is lower.

S130, forming a source electrode structure in the source electrode groove;

Specifically, the source structure may include a first insulating layer 71 and a trench source 62, where the first insulating layer 71 is disposed on an inner wall and a bottom of the source trench 60, the trench source 62 may be a polysilicon layer, the source structure is disposed in the source trench 60, and the second region 50 is disposed on a side of the source trench 60 far away from the gate trench 70, that is, on a side of the source structure far away from the gate structure, and the doping type of the second region 50 is the same as that of the well region 30, so that a depletion region may be formed between the second region 50 and the epitaxial layer 20, which may play a role in shielding an electric field of the gate structure, thereby improving a breakdown problem of a gate oxide layer and ensuring the reliability of the device operation. Also, since the doping types of the second region 50 and the epitaxial layer 20 are different, a PN junction parasitic diode may be formed between the second region 50 and the epitaxial layer 20 to serve as the flywheel diode 102. Further, since the second region 50 is not provided at a side of the source trench 60 close to the gate trench 70, a PNP or NPN transistor is formed between the epitaxial layer 20, the well region 30, and the first region 40 at a side of the source trench 60 close to the gate trench 70, and serves as the freewheeling transistor 101. Therefore, the freewheeling diode and the freewheeling triode 101 are integrated on two sides of the source trench, and the source metal layer 120 covers the first surface, where the source metal layer 120 is electrically connected to the source structure, and when the source is connected to the positive voltage, the freewheeling diode 102 can be turned on. When the source is connected to a positive voltage, the source structure is used as a control electrode of the freewheeling triode 101, and the freewheeling triode 101 can be conducted. By integrating the flywheel diode 102 and the flywheel triode 101, the reverse connection flywheel path of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the current leakage speed of the semiconductor device during reverse connection is improved, and the performance stability and the safety of the semiconductor device are improved.

Referring to fig. 2, the second region 50 may also be disposed on a side of the source trench 60 near the gate trench 70, where the doping type of the second region 50 is the same as that of the well region 30, and the second region 50 may also function as a shield for the electric field of the gate structure. A freewheeling diode 102 is provided between the second region 50 and the epitaxial layer 20 on the side of the source trench 60 adjacent to the gate trench 70. A PNP or NPN freewheeling transistor 101 is formed between the epitaxial layer 20, the well region 30, and the first region 40 on the side of the source trench 60 remote from the gate trench 70. The method can also play a role in increasing the reverse connection follow current path of the semiconductor device, reducing the reverse connection voltage drop of the semiconductor device and improving the leakage speed of the semiconductor device during reverse connection.

And S140, forming a drain electrode on one side of the substrate away from the epitaxial layer.

Specifically, the drain electrode 110 may be formed on the side of the substrate 10 away from the epitaxial layer 20 by means of Sputter coating (spin), or the like, wherein the surface of the substrate 10 away from the epitaxial layer 20 is thinned, and then the drain electrode 110 is formed by means of Sputter coating, or the like. The drain electrode 110 is a metal conductive layer, and exemplary, the metal conductive layer may be titanium (Ti), nickel (Ni), or silver (Ag).

The method for manufacturing the semiconductor device provided by the technical scheme provided by the embodiment of the invention comprises the steps of providing a semiconductor body 100, wherein the semiconductor body 100 comprises a substrate 10, an epitaxial layer 20, a well region 30, a first region 40 and a second region 50, the epitaxial layer 20 is located on one side of the substrate 10, the well region 30 is located on one side of the epitaxial layer 20 away from the substrate 10, the first region 40 is located on one side of the well region 30 away from the substrate 10, the surface of one side of the first region 40 away from the substrate 10 is used as a first surface, a gate groove 70 and a source groove 60 are respectively arranged on the first surface, the gate groove 70 and the source groove 60 extend into the epitaxial layer 20 from the first surface, the second region 50 is located on one side of the source groove 60 away from or close to the gate groove 70, a gate structure is formed in the gate groove 70, a source structure is formed in the source groove 60, and a drain electrode 110 is formed on one side of the substrate 10 away from the epitaxial layer 20. The first region 40 and the epitaxial layer 20 are of a first doping type, the well region 30 and the second region 50 are of a second doping type, and a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20 to serve as the freewheeling diode 102 due to the different doping types of the second region 50 and the epitaxial layer 20. Further, since the second region 50 is not disposed on the side of the source trench 60 near the gate trench 70, a PNP or NPN transistor is formed between the epitaxial layer 20, the well region 30 and the first region 40, and is used as the freewheeling transistor 101. Therefore, when the source is connected to the positive voltage, the freewheeling diode 102 may be turned on, and the source structure may be used as the control electrode of the freewheeling triode 101, so that the freewheeling triode 101 may also be turned on. By integrating the flywheel diode 102 and the flywheel triode 101, the reverse connection flywheel path of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the current leakage speed of the semiconductor device during reverse connection is improved, and the performance stability and the safety of the semiconductor device are improved.

Optionally, the semiconductor body 100 further comprises a first buried layer 80;

the preparation method also comprises the following steps:

A first buried layer 80 is formed in the epitaxial layer 20 on a side of the source trench 60 adjacent to the gate trench 70, wherein an orthographic projection of the first buried layer 80 on a side wall of the source trench 60 adjacent to the gate trench 70 does not overlap with an orthographic projection of the well region 30 and the first region 40 on a side wall of the source trench 60 adjacent to the gate trench 70.

Specifically, referring to fig. 3, the first buried layer 80 may be formed by ion implantation, and the doping type of the first buried layer 80 is the same as that of the second region 50. Illustratively, in forming the epitaxial layer 20, the first buried layer 80 may be formed by ion implantation, and the source trench 60 may be formed according to a position of the first buried layer 80 such that the first buried layer 80 is distributed on a side of the source trench 60 adjacent to the gate trench 70. The first buried layer 80 may also cover the bottom of the source trench 60, so as to be disposed adjacent to the second region 50 at the bottom of the source trench 60, and further improve the effect of shielding the electric field of the gate structure. The first buried layer 80 may extend along a sidewall of the source trench 60 in a direction pointing to the first region 40, but the first buried layer 80 is not in contact with the first region 40 and the well region 30, so as to avoid blocking a channel of the freewheeling transistor 101.

Optionally, the semiconductor body 100 further comprises a second buried layer 90;

the preparation method also comprises the following steps:

A second buried layer 90 is formed in the epitaxial layer 20 on a side of the source trench 60 remote from the gate trench 70, wherein an orthographic projection of the second buried layer 90 on a side of the source trench 60 remote from the gate trench 70 does not overlap with an orthographic projection of the well region 30 and the first region 40 on a side of the source trench 60 remote from the gate trench 70.

Specifically, referring to fig. 4, the second buried layer 90 may be formed by ion implantation, and the second buried layer 90 may be of the same doping type as the second region 50. Illustratively, in forming the epitaxial layer 20, the second buried layer 90 may be formed by ion implantation, and the source trench 60 may be formed according to the position of the second buried layer 90, such that the second buried layer 90 is distributed on a side of the source trench 60 adjacent to the gate trench 70. The second buried layer 90 may also cover the bottom of the source trench 60, so as to be disposed adjacent to the second region 50 at the bottom of the source trench 60, and further improve the effect of shielding the electric field of the gate structure. The first buried layer 80 may extend along a sidewall of the source trench 60 in a direction pointing to the first region 40, but the first buried layer 80 is not in contact with the first region 40 and the well region 30, so as to avoid blocking a channel of the freewheeling transistor 101.

Optionally, forming the source structure within the source trench 60 includes:

forming a first insulating layer 71 on the inner wall and bottom of the source trench 60;

a trench source 62 is formed in the source trench 60 on the first insulating layer 71 side, wherein the length of the trench source 62 in the extending direction of the source trench 60 is greater than the depth of the source trench 60.

Specifically, the first insulating layer 71 is disposed on the inner wall and bottom of the source trench 60, the trench source 62 may be a polysilicon layer, and the first insulating layer 71 in the source structure may be the same as the first insulating layer 71 in the gate structure. Therefore, during the preparation, the first insulating layer 71 in the source electrode structure and the first insulating layer 71 in the gate electrode structure may be formed simultaneously, then a polysilicon layer is deposited, and then the entire polysilicon layer is etched back, so that 200-500nm remains on the first surface of the polysilicon layer, then the polysilicon layer in the source electrode trench 60 is protected by using the photoresist, and then the etching back is continued, so that the polysilicon layer is filled in the gate electrode trench 70, and the deposition height of the polysilicon layer in the source electrode trench 60 is greater than the depth of the source electrode trench 60. That is, the polysilicon layer forms a protruding portion beyond the plane of the first surface, so that when the source metal layer 120 is formed on the first surface, the protruding portion is located inside the source metal layer 120, thereby increasing the contact area between the polysilicon layer and the source metal layer 120, which is beneficial to increasing the voltage sensitivity of the control electrode of the freewheeling triode 101 and controlling the conduction process of the freewheeling triode 101. By way of example, the protruding portion may be cylindrical, trapezoidal, conical, or other regular or irregular shape, capable of increasing the contact area between the polysilicon layer and the source metal layer 120.

Optionally, the semiconductor device further includes an ohmic contact metal layer 140 and a second insulating layer 130;

the preparation method also comprises the following steps:

Forming a second insulating layer 130 on one side of the first surface away from the gate structure, wherein the orthographic projection of the second insulating layer 130 on the first surface covers the gate structure;

An ohmic contact metal layer 140 is formed on a side of the second insulating layer 130 away from the gate structure, the ohmic contact metal layer 140 is electrically connected to the first region 40, and a metal material of the ohmic contact metal layer 140 includes titanium.

Specifically, a second insulating layer 130 is formed on the surface of the first region 40 away from the substrate 10, the second insulating layer 130 may be an interlayer dielectric layer (INTER LAYER DIELECTRIC, ILD), the second insulating layer 130 may cover the surface of the gate structure, an ohmic contact metal layer 140 is disposed on one side of the second insulating layer 130 away from the gate structure, a source is formed on the surface of the ohmic contact metal layer 140 away from the substrate 10, and the second insulating layer 130 isolates the gate structure from the source. The ohmic contact metal layer 140 is electrically connected with the trench source electrode 62, and when the ohmic contact metal layer 140 is in contact with the trench source electrode 62, the resistance of the contact surface is very small, so that the current-voltage relationship is linear, and no obvious additional impedance is generated. The good ohmic contact can significantly reduce the contact resistance between the source and the trench source 62, thereby improving the conduction efficiency of the device. The ohmic contact metal of the ohmic contact metal layer 140 may be nickel (Ni), but Ni is easily reacted with the polysilicon layer to lower the reliability of the device, so that the ohmic contact metal may be titanium (Ti), for example, ti is used as the ohmic contact metal, the ohmic contact metal layer 140 does not react with the polysilicon layer, and the ohmic contact metal layer 140 has a contact connection with the first region 40, and when the first region 40 is n+ doped, the contact between the titanium and the first region 40 may obtain a lower contact resistance, and thus the reverse conduction voltage drop of the freewheeling triode 101 may be reduced.

In the embodiment of the present invention, taking the semiconductor device structure in fig. 3 as an example to describe a method for manufacturing a semiconductor device, fig. 6 is a flowchart of another method for manufacturing a semiconductor device provided in the embodiment of the present invention, and fig. 7 to 13 are schematic diagrams of intermediate structures of the manufacturing process provided in the embodiment of the present invention, where the manufacturing method includes:

s210, forming a first portion of the epitaxial layer 20 on one side of the substrate 10, and forming a first buried layer 80 in the first portion of the epitaxial layer 20;

The substrate 10 may be an n+ doped silicon carbide substrate, and the first buried layer 80 of p+ doped type is formed by growing a first portion of the epitaxial layer 20 on the substrate 10 and then performing ion implantation at a certain location, and the structure thereof is shown in fig. 7.

S220, forming a second portion of the epitaxial layer 20 on the side of the first portion of the epitaxial layer 20 away from the substrate 10, where the structure is shown in fig. 8.

S230, forming a well region 30 on the side of the epitaxial layer 20 of the second part far away from the substrate 10, and forming a first region 40 on the side of the well region 30 far away from the substrate 10;

The well region 30 and the first region 40 are used to form a conductive channel of the semiconductor device, and the well region 30 and the first region 40 may be formed by epitaxial growth, ion implantation, vapor deposition, or the like, and the structure thereof is shown in fig. 9.

S240, taking the surface of the first region 40, which is far from the side of the substrate 10, as a first surface, and forming a gate trench 70 and a source trench 60 on the first surface respectively, so that the first buried layer 80 is positioned on the side of the source trench 60, which is close to the gate trench 70, wherein the gate trench 70 and the source trench 60 extend into the epitaxial layer 20 from the first surface;

Specifically, the gate trench 70 and the source trench 60 are set to different depths, so that the gate trench 70 and the source trench 60 need to be formed by step etching in different manufacturing processes, and the depth of the source trench 60 may be 1.2-2.5 μm, and the depth of the gate trench 70 may be 0.7-1.2 μm, so that the device can stably operate at a higher voltage by optimizing on-resistance and improving breakdown voltage of the semiconductor device while ensuring device performance by selecting appropriate depths of the source trench 60 and the gate trench 70. The gate trench 70 and the source trench 60 extend from the first surface to the epitaxial layer 20 through the first region 40 and the well region 30. The structure is shown in fig. 10.

S250, forming a second region 50 on one side of the source trench 60 away from the gate trench 70;

Wherein the second region 50 is formed by ion implantation at a side of the source trench 60 remote from the gate trench 70. The first region 40 is of a first doping type and the well region 30 and the second region 50 are of a second doping type, the structure of which is shown in fig. 11.

S260, forming a gate structure in the gate trench 70 and forming a source structure in the source trench 60;

Specifically, a gate structure is disposed in the gate trench 70, and a source structure is disposed in the source trench 60. The gate structure may include a first insulating layer 71 and a trench gate 72, the first insulating layer 71 being disposed at an inner wall and a bottom of the gate trench 70, the source structure may include the first insulating layer 71 and a trench source 62, the first insulating layer 71 being disposed at an inner wall and a bottom of the source trench 60, and the first insulating layer 71 in the source structure and the first insulating layer 71 in the gate structure may be simultaneously formed through a thermal oxidation process in preparation, wherein the first insulating layer 71 at the bottom of the gate trench 70 is thicker, and the sidewall first insulating layer 71 of the gate trench 70 is thinner. Then depositing a polysilicon layer, back etching the entire polysilicon layer to ensure that the polysilicon layer on the first surface is remained by 200-500nm, then protecting the polysilicon layer in the source trench 60 by using a photoresist, and continuing back etching to ensure that the polysilicon layer is filled in the gate trench 70 to form a trench gate 72, wherein the deposition height of the polysilicon layer in the source trench 60 is greater than the depth of the source trench 60. That is, the polysilicon layer forms a protruding portion beyond the plane of the first surface, so that when the source metal layer 120 is formed on the subsequent first surface, the protruding portion will be inside the source metal layer 120, thereby increasing the contact area between the polysilicon layer and the source metal layer 120, which is beneficial to increasing the voltage sensitivity of the control electrode of the freewheeling triode 101 and controlling the conduction process of the freewheeling triode 101. By way of example, the protruding portion may be cylindrical, trapezoidal, conical, or other regular or irregular shape, capable of increasing the contact area between the polysilicon layer and the source metal layer 120. The structure of which is shown in fig. 12.

S270, forming a second insulating layer 130 on one side of the first surface far away from the gate structure, wherein the orthographic projection of the second insulating layer 130 on the first surface covers the gate structure, and forming an ohmic contact metal layer 140 on one side of the second insulating layer 130 far away from the gate structure;

Specifically, the second insulating layer 130 is prepared, the second insulating layer 130 covers the surface of the gate structure, and the ohmic contact region is exposed, and the ohmic contact region includes a portion of the first region, so that the ohmic contact metal layer 140 is prepared. The ohmic contact metal layer 140 is electrically connected to the first region 40, and the metal material of the ohmic contact metal layer 140 includes titanium. The structure is shown in fig. 13.

S280, the source metal layer 120, the passivation layer 150, and the drain electrode 110 on the other side of the substrate 10 are formed. The structure of which is shown in figure 3.

It should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to the above-mentioned embodiments, it should be understood by those skilled in the art that the technical solution described in the above-mentioned embodiments may be modified or some technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solution of the embodiments of the present invention.

Claims

1. A semiconductor device, comprising:

The semiconductor body comprises a substrate, an epitaxial layer, a well region, a first region, a second region and a buried layer, wherein the epitaxial layer is positioned on one side of the substrate, the well region is arranged on one side of the epitaxial layer, which is far away from the substrate, the first region is arranged on one side of the well region, which is far away from the substrate, the surface of the first region, which is far away from one side of the substrate, is used as a first surface, a gate groove and a source groove are respectively arranged on the first surface, the gate groove and the source groove extend into the epitaxial layer from the first surface, the second region is arranged on one side of the source groove, which is far away from or close to the gate groove, the buried layer is arranged on the other side of the source groove, the second region extends into the epitaxial layer from the first surface, the orthographic projection of the buried layer on the side wall of the source groove does not overlap with the orthographic projection of the well region and the first region on the side of the source groove, the first region and the epitaxial layer are of a first doping type, and the second region and the second doping type are of the well region and the second doping type;

the grid structure is positioned in the grid groove;

the source electrode structure is positioned in the source electrode groove;

The source metal layer is positioned on the first surface and is in contact with the source structure;

2. The semiconductor device of claim 1, wherein the second region is disposed on a side of the source trench away from the gate trench, and wherein an orthographic projection of the second region at a bottom of the source trench covers at least a portion of the bottom of the source trench.

3. The semiconductor device of claim 2, wherein the buried layer comprises:

4. The semiconductor device of claim 1, wherein the second region is disposed on a side of the source trench adjacent to the gate trench, and wherein an orthographic projection of the second region on a bottom of the source trench covers at least a portion of the bottom of the source trench.

5. The semiconductor device of claim 4, wherein the buried layer comprises:

6. The semiconductor device of any of claims 1-5, wherein the source structure comprises a first insulating layer and a trench source;

7. The semiconductor device according to claim 6, wherein the semiconductor device further comprises:

8. A power module comprising a substrate and at least one semiconductor device according to any of claims 1-7, said substrate being arranged to carry said semiconductor device.

9. A power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction;

the power conversion circuit comprising a circuit board and at least one semiconductor device according to any one of claims 1-7, the semiconductor device being electrically connected to the circuit board.

10. A vehicle comprising a load and the power conversion circuit according to claim 9, wherein the power conversion circuit is configured to convert alternating current into direct current, alternating current into alternating current, direct current into direct current, or direct current into alternating current, and then input the alternating current into the load.

11. A method of manufacturing a semiconductor device, comprising:

Providing a semiconductor body, wherein the semiconductor body comprises a substrate, an epitaxial layer, a well region, a first region, a second region and a buried layer, the epitaxial layer is positioned on one side of the substrate, the well region is arranged on one side of the epitaxial layer away from the substrate, the first region is arranged on one side of the well region away from the substrate, the surface of the first region away from one side of the substrate is used as a first surface, the first surface is respectively provided with a gate groove and a source groove, the gate groove and the source groove extend into the epitaxial layer from the first surface, the second region is arranged on one side of the source groove away from or close to the gate groove, the buried layer is arranged on the other side of the source groove, the second region extends into the epitaxial layer from the first surface, the orthographic projection of the well region on the side wall of the source groove and the orthographic projection of the first region on the side wall of the source groove do not overlap, the first region and the source groove extend into the epitaxial layer, the first region and the second region are of a first doping type and a second doping type;

Forming a gate structure in the gate trench;

forming a source electrode structure in the source electrode groove;

12. The method for manufacturing the semiconductor device according to claim 11, wherein in a case where the second region is provided on a side of the source trench away from the gate trench, an orthographic projection of the second region on a bottom of the source trench covers at least a portion of the bottom of the source trench.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the buried layer includes a first buried layer;

The preparation method further comprises the following steps:

14. The method for manufacturing the semiconductor device according to claim 11, wherein in a case where the second region is provided on a side of the source trench close to the gate trench, an orthographic projection of the second region on a bottom of the source trench covers at least a portion of the bottom of the source trench.

15. The method of manufacturing a semiconductor device according to claim 14, wherein the buried layer comprises a second buried layer;

The preparation method further comprises the following steps:

16. The method of manufacturing a semiconductor device according to any one of claims 11 to 15, wherein forming a source structure in the source trench comprises:

17. The method of manufacturing a semiconductor device according to claim 16, wherein the semiconductor device further comprises an ohmic contact metal layer and a second insulating layer;

The preparation method further comprises the following steps: