CN119336669A - Memory controller and control method - Google Patents
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Abstract
存储器控制器及控制方法。存储器控制器包括多个电压转换电路、检查电路及选择电路。电压转换电路经组态以接收外部电压，并分别转换为多个电源电压。电压转换电路分别检测其所产生的该些电源电压的电平，以产生多个电源确认信号。检查电路耦接于电压转换电路。检查电路用以根据电源确认信号来产生第一检查信号以及第二检查信号，其中第一检查信号对应于电源电压中的内部电源电压，且第二检查信号对应于所有的电源电压。选择电路用以选择性地将第一检查信号或第二检查信号输出为重设确认信号。
A memory controller and a control method. The memory controller includes a plurality of voltage conversion circuits, a check circuit, and a selection circuit. The voltage conversion circuit is configured to receive an external voltage and convert it into a plurality of power supply voltages. The voltage conversion circuit detects the levels of the power supply voltages generated by it to generate a plurality of power supply confirmation signals. The check circuit is coupled to the voltage conversion circuit. The check circuit is used to generate a first check signal and a second check signal according to the power supply confirmation signal, wherein the first check signal corresponds to an internal power supply voltage in the power supply voltage, and the second check signal corresponds to all power supply voltages. The selection circuit is used to selectively output the first check signal or the second check signal as a reset confirmation signal.
Description
Technical Field
The present disclosure relates to controllers, and particularly to a memory controller and a control method thereof.
Background
In the application of the flash memory controller, the flash memory controller needs to perform voltage conversion according to different specifications of the host device to adaptively drive the operation of the flash memory. Therefore, how to quickly and efficiently confirm whether the converted voltages are ready or not is one of the problems to be solved in the related art when the flash memory is started or restarted.
Disclosure of Invention
The invention provides a memory controller and a control method, which can effectively and rapidly confirm whether the converted voltages are ready or not when a flash memory is started or restarted.
The memory controller of the invention comprises a plurality of voltage conversion circuits, a checking circuit and a selecting circuit. The voltage conversion circuit is configured to receive an external voltage and convert the external voltage into a plurality of power supply voltages, respectively. The voltage conversion circuit detects the levels of the power supply voltages respectively so as to generate a plurality of power supply confirmation signals. The checking circuit is coupled to the voltage converting circuit. The checking circuit is used for generating a first checking signal and a second checking signal according to the power supply confirmation signal, wherein the first checking signal corresponds to an internal power supply voltage in the power supply voltages, and the second checking signal corresponds to all the power supply voltages. The selection circuit is used for selectively outputting the first check signal or the second check signal to the reset confirmation signal.
The control method is suitable for driving the flash memory. The control method comprises the steps of receiving external voltage, converting the external voltage into a plurality of power supply voltages, detecting the levels of the power supply voltages to generate a plurality of power supply confirmation signals respectively corresponding to the power supply voltages, generating a first check signal and a second check signal according to the power supply confirmation signals, wherein the first check signal corresponds to the internal power supply voltage in the power supply voltages, the second check signal corresponds to all the power supply voltages, and selectively outputting the first check signal or the second check signal to a reset confirmation signal.
Based on the above, the memory controller and the control method of the present invention provide a method for checking the power supply voltage by software or hardware, and provide a flexible and rapid flash memory start-up or restart procedure.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a circuit block diagram of a memory controller according to an embodiment of the invention;
FIG. 2 is a circuit block diagram of a memory controller according to an embodiment of the invention;
FIG. 3 is a flow chart of a control method according to an embodiment of the invention;
fig. 4 is a flowchart of a control method according to an embodiment of the invention.
Description of the reference numerals
10, A host device;
11. a memory controller;
A flash memory;
110. 210, checking a circuit;
111. 211, a selection circuit;
112, a processor;
2100 voltage level setting circuit;
2101, a confirmation result judging circuit;
2110-2112;
DS1, DS 2;
DS2 Cont, checking a result custom signal;
LDO 1-LDOx voltage conversion circuit;
MS, mode selection signal;
RSC, reset acknowledgement signal;
S1, S2 and S3, setting signals;
s2_en, mode enable signal;
S31-S34, S41-S46;
VC 1-VCx, power supply confirmation signal;
Vext, external voltage;
VS, converting the setting signal;
VS1 to VSx, the power supply voltage.
Detailed Description
FIG. 1 is a block diagram of a memory controller 11 according to an embodiment of the invention. Generally, the memory controller 11 is coupled between the flash memory 12 and the host device 10. The memory controller 11 can receive the external voltage Vext provided by the host device 10 and the externally input setting signals S1 and S2, and correspondingly convert the external voltage Vext into a suitable voltage level, so as to drive the operations of the flash memory 12 and the internal circuits of the memory controller 11. In practical applications, the external voltage Vext provided by the host device 10 of different specifications is different, so that the memory controller 10 connected between the host device 10 and the flash memory 12 plays an important role, and is responsible for adaptively performing voltage conversion between the host device 10 of different specifications and voltage requirements and the flash memory 12, so as to better region the flash memory 12 and further increase the system compatibility of the flash memory 12.
In detail, the host device 10 may be a Secure Digital (SD) memory card, an embedded multimedia card (embedded MultiMedia Card, eMMC), a universal serial bus (Universal Serial Bus, USB), a universal flash memory storage (Universal Flash Storage, UFS), a Non-volatile memory communication protocol (Non-Volatile Memory Express, NVMe), or other host devices 10 of suitable specifications. Further, the host device 10 may provide an external voltage Vext to the memory controller 11. Meanwhile, the voltage combination set by the user or the system requirement is indicated by externally inputting the first setting signal S1 and the second setting signal S2 to the memory controller 11.
In some embodiments, the memory controller 11 can receive the external voltage Vext and generate the appropriate first power voltage VS1 and the second power voltage VS2 according to the first setting signal S1, respectively for driving the core circuit blocks in the flash memory 12. On the other hand, each time the memory controller 11 is started or restarted, it is necessary to recheck the voltage of the external voltage Vext to confirm that the converted power supply voltages have reached the system requirements. In this embodiment, the memory controller 11 can also operate in different modes according to the second setting signal S2, and check the levels of the converted power voltages VS1 to VSx (including the first power voltage VS1 and the second power voltage VS 2) in different manners according to the setting. When operating in the first mode, the memory controller 11 can check all the converted power supply voltages VS 1-VSx one by one through the internal processor 112 in a software operation mode. When operating in the second mode, the memory controller 11 can check the converted power supply voltages VS 1-VSx in hardware through its internal circuits.
In some embodiments, the memory controller 11 includes a plurality of voltage conversion circuits LDO 1-LDOx, a checking circuit 110, a selecting circuit 111, and a processor 112. The voltage conversion circuits LDO 1-LDOx can be used for receiving an external voltage Vext to generate a plurality of power voltages VS 1-VSx, wherein the power voltages include a first power voltage VS1, a second power voltage VS2 and a third power voltage VS3. The first power voltage VS1 and the second power voltage VS2 can be provided to the flash memory 12 for driving, for example, the flash memory core circuit block and the input/output circuit block, respectively. The third power voltage VS3 (i.e., the internal power voltage) may be provided to the memory controller 11 for driving, and is, for example, a basic power voltage for driving the memory controller 11 to operate. In some embodiments, each of the voltage converting circuits LDOs 1-LDOx may be, for example, a low dropout converting circuit (low dropout circuit), a buck converter (buck converter), or other suitable circuits for stepping down the external voltage Vext to an appropriate voltage level. In this embodiment, the number x of the voltage converting circuits LDOs 1 to LDOx can be adjusted according to the number of power supply voltages required by the system or the number of divided voltage domains (voltage domains).
Further, the checking circuit 110 is coupled to the voltage converting circuits LDO 1-LDOx, and the checking circuit 110 can generate a plurality of conversion setting signals VS according to the first setting signal S1 for controlling and setting the operation of the voltage converting circuits LDO 1-LDOx, so that the voltage converting circuits LDO 1-LDOx can convert and generate the power voltage according to the specifications of the host device 10 and the flash memory 12. In detail, each of the voltage converting circuits LDOs 1 to LDOx can independently operate and generate a different power supply voltage, which can have the same or different voltage levels. The first voltage converting circuit LDO1 and the second voltage converting circuit LDO2 (not explicitly shown in FIG. 1) among the voltage converting circuits LDO 1-LDOx can generate power supply voltages VS1 and VS2, respectively, for driving the core circuit blocks and the input/output circuit blocks in the flash memory 12, respectively. In addition, the third voltage conversion circuit LDO3 (not explicitly shown in fig. 1) can generate the third power voltage VS3 required by the memory controller 11. In addition, each time the power-on or the power-off of the external voltage Vext is performed, the memory controller 11 needs to determine whether each of the power supply voltages VS1 to VSx reaches or exceeds the corresponding voltage threshold. More specifically, the voltage conversion circuits LDO 1-LDOx can sense the power supply voltages VS 1-VSx generated by themselves respectively to determine whether each power supply voltage VS 1-VSx exceeds the corresponding voltage threshold value, and generate corresponding power supply confirmation signals VC 1-VCx accordingly.
In some embodiments, the first setting signal S1 and the second setting signal S2 can be provided in real time from outside or written in advance to the memory controller 11, thereby controlling the operation of the memory controller 11. For example, the first setting signal S1 and the second setting signal S2 may be obtained by reading a pre-written electronic fuse (efuse). Alternatively, the first setting signal S1 and the second setting signal S2 may be obtained by, for example, reading the voltage level connected to the corresponding pad (pad) and the bonding wire (bonding wire). Alternatively, the first setting signal S1 and the second setting signal S2 may be provided in real time by an external device that is the same as or different from the host device 10, for example.
Further, the checking circuit 110 is coupled to the voltage converting circuits LDO 1-LDOx, and the checking circuit 110 can generate a first checking signal DS1 and a second checking signal DS2 according to the power confirming signals VC 1-VCx, wherein the first checking signal DS1 corresponds to the third power confirming signal VC3, which contains checking information of the third power voltage VS3 for driving the processor 112. The second inspection signal DS2 corresponds to the power supply confirm signals VC 1-VCx of all the power supply voltages VS1-VSx, and comprises inspection information of all the power supply voltages VS1-VSx. Further, the checking circuit 110 may generate the mode selection signal MS according to the second setting signal S2, and provide the mode selection signal MS, the first checking signal DS1, and the second checking signal DS2 to the selecting circuit 111.
The selection circuit 111 is coupled to the inspection circuit 110. The selection circuit 111 may select the first check signal DS1 or the second check signal DS as the reset confirm signal RSC according to the mode select signal MS and output to the processor 112. More specifically, when the memory controller 11 is operating in the first mode, the processor 112 is used to check the power confirm signals VC 1-VCx. In this case, to ensure that the processor 112 can first obtain a stable supply voltage for inspection, the inspection circuit 110 may first inspect only the supply voltage received by the processor 112. In this embodiment, the processor 112 operates in need of the third supply voltage VS3. Therefore, the checking circuit 110 outputs the power confirmation signal VC3 generated by the voltage converting circuit LDO3 checking the third power voltage VS3 as the first checking signal DS1, and provides the first checking signal DS1 to the selecting circuit 111. In addition, when the memory controller 11 is operating in the second mode, all the power confirm signals VC 1-VCx are checked by the checking circuit 110 in a hardware circuit mode, and the second checking signal DS2 is generated according to all the power confirm signals VC 1-VCx.
On the other hand, the second setting signal S2 indicates whether the memory controller 11 is to check the power supply voltages VS1 to VSx in a software manner or a hardware manner. In this case, the checking circuit 110 can generate the mode selection signal MS according to the second setting signal S2 to inform the selecting circuit 111 whether the host device 10 is to instruct the software or hardware to check the power supply voltages VS 1-VSx. When the second setting signal S2 indicates to check the power voltages VS1 to VSx in a software manner, the memory controller 11 is controlled to operate in the first mode, and the selection circuit 111 outputs the first check signal DS1 as the reset confirm signal RSC according to the mode select signal MS, so that the processor 112 checks all the power confirm signals VC1 to VCx after the reset confirm signal RSC indicates that the third power voltage VS3 is ready. In addition, when the second setting signal S2 indicates to check the power supply voltages VS1 to VSx in hardware, the memory controller 11 is controlled to operate in the second mode, and the checking circuit 110 checks all the power supply confirm signals VC1 to VCx simultaneously, and generates the corresponding second checking signal DS2 accordingly. The selection circuit 111 outputs the second checking signal DS2 as a reset acknowledge signal RSC in the second mode according to the mode selection signal MS, thereby indicating the checking result of the processor 112 with respect to the checking circuit 110.
Under control of the reset acknowledge signal RSC, the processor 112 performs operations corresponding to the first mode and the second mode. Specifically, when the memory controller 11 is operated in the first mode and the reset confirm signal RSC indicates that the basic operating voltage VS3 is ready, the processor 112 executes a software program to check the power confirm signals VC 1-VCx sequentially, so as to ensure that the driving and the reading/writing operation of the flash memory 12 are performed after the power voltages VS 1-VSx are greater than or equal to their corresponding voltage thresholds. In addition, when the memory controller 11 is operated in the second mode and the reset acknowledge signal RSC indicates that all the power voltages VS 1-VSx are ready, the processor 112 can immediately start driving and performing the read/write operation of the flash memory 12.
FIG. 2 is a block diagram of a memory controller 21 according to an embodiment of the invention. The memory controller 21 of fig. 2 is similar to the memory controller 11 of fig. 1, and is used for illustrating the internal circuit structures of the checking circuit 210 and the selecting circuit 211 in the memory controller 21, so the same elements are denoted by the same symbols, and the description thereof is omitted herein.
In this embodiment, the memory controller 21 includes a checking circuit 210, a selecting circuit 211, a processor 112 and voltage converting circuits LDOs 1-LDOx. Further, the inspection circuit 210 includes a voltage level setting circuit 2100 and a confirmation result judging circuit 2101. Specifically, the voltage level setting circuit 2100 receives the first setting signal S1 and the second setting signal S2. The voltage level setting circuit 2100 can generate a switching setting signal VS according to the first setting signal, so as to adaptively adjust the voltage switching circuits LDO 1-LDOx to generate the power supply voltages VS 1-VSx required by the system. Further, the voltage level setting circuit 2100 may provide the mode information MI to the confirmation result judging circuit 2101 according to the second setting signal S2.
In this embodiment, the confirmation result determining circuit 2101 receives the third setting signal S3 from the host device 10 and the mode enabling signal s2_en and the inspection result custom signal ds2_cont from the processor 112 in addition to the power confirmation signals VC1 to VCx and the mode information MI related to the second setting signal S2 from the voltage level setting circuit 2100. In detail, the third setting signal S3 includes an output time of the reset acknowledge signal RSC, i.e. how long the operation time is needed to wait after the start or the restart, and the output time of the reset acknowledge signal RSC is generally related to the ramp-up slope and the acknowledge time required by the power acknowledge signals VC1 to VCx. The mode enable signal s2_en contains information about whether the memory controller 21 is allowed to operate in the second mode, i.e. whether the memory controller 21 is open to perform the confirmation determination of the power supply voltage in hardware. Finally, the check result custom signal ds2_cont is a power confirm signal that is asserted by the system or user to define the memory controller 21 to check in the second mode. For example, in some embodiments, the determining circuit 2101 may receive all the power confirm signals VC 1-VCx through an AND gate to determine whether all the power confirm signals VC 1-VCx are ready, and generate the second check signal DS2 accordingly. However, in some other embodiments, the determining circuit 2101 can select a part of the selected power confirm signals from the power confirm signals VC 1-VCx according to the checking result custom signal ds2_cont, so as to determine whether the selected power confirm signals are ready, and generate the second checking signal DS2 accordingly.
The selection circuit 211 includes an and gate 2110, an exclusive or gate 2111, and an or gate 2112. The first input of the and gate 2110 receives the mode information MI and the second input receives the first check signal DS1. The exclusive or gate 2111 has a first input receiving the mode information MI and a second input receiving the second check signal DS2. And, the outputs of the and gate 2110 and the exclusive-or gate 2111 are respectively connected to the first input and the second input of the or gate 2112 to generate the reset acknowledge signal RSC at the output of the or gate 2112. In detail, when the mode enable signal s2_en indicates that the memory controller 21 opens the second mode, the selection circuit 211 selectively selects the first check signal DS1 or the second check signal DS2 as the reset confirm signal RSC according to the control of the second set signal S2. In contrast, when the mode enable signal s2_en indicates that the memory controller 21 does not open the second mode, the determination result determining circuit 2101 may operate only the mode selection signal MS in the first mode according to the mode enable signal s2_en, so that the selection circuit 211 outputs the first check signal DS1 as the reset determination signal RSC according to the mode selection signal MS. Although an implementation in which the selection circuit 211 is implemented with an and gate 2110, an exclusive or gate 2111, and an or gate 2112 is shown in fig. 2. It should be understood that the circuit structure in fig. 3 is only one implementation of various alternative embodiments of the present invention, and those skilled in the art can naturally change the circuit structure by themselves, and the same result can be achieved by different circuit structures. For example, the selection circuit 211 may be realized by a multiplexer, as long as it can selectively output the first check signal DS1 or the second check signal DS2 as the reset acknowledge signal RSC.
Fig. 3 is a flowchart of a control method according to an embodiment of the invention. The flowchart shown in fig. 3 can be applied to the memory controllers 11, 21 shown in fig. 1,2, and the operation contents with respect to the memory controllers 11, 21 can be generalized to the flowchart shown in fig. 3. The flowchart shown in FIG. 3 includes steps S31-S34. In step S31, the memory controller 11/21 receives the external voltage Vext and converts the external voltage Vext into a plurality of power voltages VS 1-VSx. In step S32, the memory controller 11/21 can detect the levels of the converted power supply voltages VS 1-VSx to generate corresponding power supply confirmation signals VC 1-VCx, respectively. In step S33, the memory controller 11/21 generates a first check signal DS1 and a second check signal DS2 according to the power confirm signals VC 1-VCx, wherein the first check signal DS1 corresponds to a third power voltage VS3 among the power voltages, and the second check signal DS2 corresponds to all the power voltages. Finally, the memory controller 11/21 may selectively output the first check signal DS1 or the second check signal DS2 as the reset confirm signal RSC. For details of the control method shown in fig. 3, please refer to the description of the memory controllers 11 and 21 in the above paragraphs, and the detailed description is omitted here.
Fig. 4 is a flowchart of a control method according to an embodiment of the invention. The flow chart shown in fig. 4 can be applied to the memory controllers 11, 21 shown in fig. 1,2, and the operation contents concerning the memory controllers 11, 21 can also be generalized to the flow chart shown in fig. 4. The flowchart shown in FIG. 4 includes steps S41-S46. In step S41, the memory controller 11/21 can set the first voltage conversion circuit LDO1 and the second voltage conversion circuit LDO2 of the flash memory 12 according to the first setting signal S1. In step S42, the memory controller 11/21 receives the external voltage Vext and converts the external voltage Vext into a plurality of power voltages VS1-VSx. In step S43, the memory controller 11/21 can detect the levels of the power voltages VS 1-VSx to generate the corresponding power confirmation signals VC 1-VCx, respectively. In step S44, the memory controller 11/21 may determine in which operation mode the memory controller 11/21 is controlled according to the second setting signal. When the memory controller 11/21 determines that the memory controller 11/21 is controlled in the first mode, the process proceeds to step S45, where the memory controller 11/21 can check the power supply voltages VS 1-VSx in a software manner through the processor 112. Conversely, when the memory controller 11/21 determines that the memory controller 11/21 is controlled in the second mode, the process proceeds to step S46, where the memory controller 11/21 can check the power supply voltages VS1 to VSx in hardware through the checking circuit 110.
In summary, the memory controller and the control method of the present invention provide for checking the power supply voltage by means of software or hardware. Compared with the process of checking all power supply voltages one by one in a software mode through a processor, the process of checking all power supply voltages one by one can be omitted by checking the power supply voltages in a hardware mode, and the checking speed of the memory controller after starting or restarting is effectively improved.
Claims (17)
1. A memory controller, comprising:
A plurality of voltage conversion circuits configured to receive an external voltage and respectively convert the external voltage into a plurality of power supply voltages, the plurality of voltage conversion circuits respectively detecting levels of the plurality of power supply voltages generated by the plurality of voltage conversion circuits to generate a plurality of power supply confirmation signals;
A checking circuit coupled to the voltage converting circuits for generating a first checking signal and a second checking signal according to the power supply confirmation signals, wherein the first checking signal corresponds to an internal power supply voltage of the power supply voltages and the second checking signal corresponds to all the power supply voltages, and
And a selection circuit for selectively outputting the first check signal or the second check signal as a reset confirm signal.
2. The memory controller of claim 1, wherein the checking circuit is configured to receive a first setting signal for setting a first voltage converting circuit and a second voltage converting circuit of the plurality of voltage converting circuits to generate a first power voltage and a second power voltage to drive the flash memory, such that the levels of the first power voltage and the second power voltage conform to the specification of the flash memory.
3. The memory controller of claim 1, further comprising a processor, wherein the checking circuit is further configured to receive a second setting signal to indicate whether the memory controller is operating in a first mode or a second mode,
Wherein when the memory controller is operating in the first mode, the processor is configured to check the plurality of power supply acknowledge signals, an
The checking circuit is configured to check the plurality of power supply acknowledge signals when the memory controller is operating in the second mode.
4. The memory controller of claim 3, wherein the internal power supply is electrically used to drive the processor.
5. The memory controller of claim 3, wherein the checking circuit is further configured to generate a mode select signal to the select circuit based on the second set signal,
Wherein when the memory controller is operating in the first mode, the selection circuit selects the first check signal as the reset confirm signal according to the mode select signal and provides the reset confirm signal to the processor, and
The selection circuit selects the second check signal as the reset confirm signal according to the mode select signal when the memory controller is operating in the second mode, and provides the reset confirm signal to the processor.
6. The memory controller of claim 5, wherein when the memory controller is operating in the first mode, the processor sequentially asserts the plurality of power supply acknowledge signals to determine whether the plurality of power supply voltages have been greater than a plurality of voltage thresholds, respectively, after the first check signal indicates that the internal power supply voltage has been greater than a first voltage threshold.
7. The memory controller of claim 5, wherein when the memory controller is operating in the second mode, the checking circuit checks whether the plurality of power supply acknowledge signals have been respectively greater than a plurality of voltage thresholds at the same time, and generates the second checking signal accordingly indicating that the plurality of power supply voltages have been respectively greater than the plurality of voltage thresholds.
8. The memory controller of claim 1, wherein the selection circuit comprises:
An AND gate having a first input for receiving a mode selection signal, a second input for receiving the first check signal, and an output for generating a first operation signal;
An exclusive-or gate having a first input receiving the mode selection signal, a second input receiving the second check signal, and an output generating a second operation signal;
an or gate having a first input receiving the first operation signal, a second input receiving the second operation signal, and an output generating the reset acknowledge signal.
9. The memory controller of claim 2, wherein the check circuit further receives a third setting signal to set an output time of the check circuit to generate the reset confirm signal.
10. The memory controller of claim 9, wherein the checking circuit comprises:
A voltage level setting circuit for generating a plurality of voltage setting signals according to the first setting signal to set the plurality of voltage conversion circuits respectively, and
And the confirmation result judging circuit is used for receiving the plurality of power supply confirmation signals to generate the first check signal according to the power supply confirmation signals corresponding to the internal power supply voltage in the plurality of power supply confirmation signals and generating the second check signal according to all the plurality of power supply confirmation signals.
11. A control method adapted to drive a flash memory, the control method comprising:
Receiving an external voltage and converting the external voltage into a plurality of power supply voltages;
detecting the levels of the power supply voltages to generate a plurality of power supply confirmation signals respectively corresponding to the power supply voltages;
Generating a first check signal and a second check signal according to the plurality of power supply confirmation signals, wherein the first check signal corresponds to an internal power supply voltage of the plurality of power supply voltages and the second check signal corresponds to all of the plurality of power supply voltages, and
Selectively outputting the first check signal or the second check signal as a reset confirm signal.
12. The control method of claim 11, further comprising receiving a first setting signal for setting a first voltage conversion circuit and a second voltage conversion circuit for generating a first power voltage and a second power voltage to drive the flash memory, such that the levels of the first power voltage and the second power voltage meet the specification of the flash memory.
13. The control method of claim 11, further comprising receiving a second setting signal to indicate operation in the first mode or the second mode,
Wherein when operating in the first mode, the processor is configured to examine the plurality of power supply acknowledge signals, an
When operating in the second mode, a checking circuit is used to check the plurality of power supply acknowledge signals.
14. The control method of claim 13, further comprising generating a mode select signal based on the second set signal,
Wherein when operating in the first mode, the first check signal is selected as the reset confirm signal according to the mode select signal and the reset confirm signal is provided to the processor, and
When operating in the second mode, the second check signal is selected as the reset confirm signal according to the mode select signal and the reset confirm signal is provided to the processor.
15. The control method of claim 14, wherein when operating in the first mode, after the first check signal indicates that the internal power supply voltage has been greater than a first voltage threshold, determining, by the processor, whether the plurality of power supply voltages have been greater than a plurality of voltage thresholds, respectively, is performed by sequentially asserting the plurality of power supply acknowledge signals.
16. The control method of claim 14, wherein when operating in the second mode, the checking circuit checks whether the plurality of power supply confirmation signals have been respectively greater than a plurality of voltage valves at the same time, and generates the second check signal indicating that the plurality of power supply voltages have been respectively greater than the plurality of voltage valves accordingly.
17. The control method of claim 12, further comprising receiving a third setting signal for setting an output time for generating the reset confirm signal.
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| TW112127308 | 2023-07-21 | ||
| TW112127308A TWI867629B (en) | 2023-07-21 | 2023-07-21 | Memory controller and control method |
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| EP1032964A2 (en) * | 1997-11-17 | 2000-09-06 | Lifestyle Technologies | Universal power supply |
| US7864615B2 (en) * | 2005-02-25 | 2011-01-04 | Kingston Technology Corporation | Flash memory controller utilizing multiple voltages and a method of use |
| TW201017389A (en) * | 2008-10-28 | 2010-05-01 | Dominion Tech Co Ltd | A power supply device capable of supplying multiple types of power source voltages |
| CN102377495B (en) * | 2010-08-13 | 2015-08-12 | 中兴通讯股份有限公司 | Radio frequency detection method, Apparatus and system |
| TWI672704B (en) * | 2018-08-14 | 2019-09-21 | 華邦電子股份有限公司 | Memory device and memory control method thereof |
| KR20210054188A (en) * | 2019-11-05 | 2021-05-13 | 에스케이하이닉스 주식회사 | Memory system, memory controller |
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