CN119317139A - Semiconductor device and manufacturing method thereof, and electronic device - Google Patents
Semiconductor device and manufacturing method thereof, and electronic device Download PDFInfo
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- CN119317139A CN119317139A CN202411833962.5A CN202411833962A CN119317139A CN 119317139 A CN119317139 A CN 119317139A CN 202411833962 A CN202411833962 A CN 202411833962A CN 119317139 A CN119317139 A CN 119317139A
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Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the method comprises the steps of providing a substrate, wherein a body region and a drift region are formed in the substrate; forming a mask layer on the surface of a substrate, patterning the mask layer to expose part of the drift region, etching the substrate to form a groove in the drift region, forming a field oxide layer, filling the groove with the field oxide layer, wherein the top surface of the field oxide layer is higher than the surface of the substrate, removing part of the mask layer to enable the rest mask layer to be used as a gate dielectric layer, wherein the gate dielectric layer covers part of the body region and part of the surface of the drift region, and one side wall of the gate dielectric layer contacts the field oxide layer, and forming a gate electrode layer, wherein the gate electrode layer covers the gate dielectric layer and part of the top surface of the field oxide layer, and the gate dielectric layer and the gate electrode layer form a gate structure. According to the invention, the mask layer is formed, and then the field oxide layer is formed in the groove by taking the mask layer as a mask, so that the bird's beak effect can be effectively inhibited, the width of the bird's beak area of the field oxide layer is reduced, and the device performance is improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device, a method for manufacturing the same, and an electronic apparatus.
Background
DMOS (double-diffused MOSFET, double-diffused metal oxide semiconductor field effect transistor) is mainly of two types, namely VDMOS (vertical double-diffused MOSFET, vertical double-diffused metal oxide semiconductor field effect transistor) and LDMOS (lateral double-diffused MOSFET, lateral double-diffused metal oxide semiconductor field effect transistor). Among them, LDMOS are widely used in the industry because they are more compatible with CMOS (Complementary Metal Oxide Semiconductor ) processes and have advantages in terms of voltage resistance, gain, linearity, switching performance, heat dissipation performance, etc.
Two important parameters of LDMOS are breakdown voltage and on-resistance, wherein in order to increase the breakdown voltage of LDMOS, a gate field plate structure is usually adopted, i.e. a gate is extended onto a field oxide layer to form a gate field plate structure, and the field oxide layer in the gate field plate structure is generally manufactured by a local oxidation isolation (Local Oxidation of Silicon, abbreviated as LOCOS) process.
However, as shown in fig. 1, the field oxide layer 110 manufactured by the LOCOS process in the related art forms a "bird's beak" structure due to the bird's beak effect, which causes the current path of the field oxide layer to be long, resulting in the on-resistance of the device to be high, and the "bird's beak" structure also limits the thickness of the field oxide layer, so that a thicker field oxide layer cannot be formed, and thus the breakdown voltage of the device is limited.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the problems existing at present, an aspect of the present invention provides a method for manufacturing a semiconductor device, including:
Providing a substrate, wherein a body region and a drift region extending from the surface of the substrate into the substrate are formed in the substrate, the drift region is of a first conductivity type, and the body region is of a second conductivity type;
Forming a mask layer on the surface of the substrate;
Patterning the mask layer to expose a portion of the drift region and etching the substrate to form a trench within the drift region;
Forming a field oxide layer, wherein the field oxide layer fills the groove, and the top surface of the field oxide layer is higher than the surface of the substrate;
Removing part of the mask layer to enable the rest of the mask layer to be used as a gate dielectric layer, wherein the gate dielectric layer covers part of the surfaces of the body region and part of the drift region, and one side wall of the gate dielectric layer is in contact with the field oxide layer;
and forming a gate electrode layer, wherein the gate electrode layer covers the gate dielectric layer and part of the top surface of the field oxide layer, and the gate dielectric layer and the gate electrode layer form a gate structure.
Illustratively, the mask layer comprises silicon oxynitride, and the mask layer is formed on the surface of the substrate, including:
And forming the mask layer on the surface of the substrate through a thermal oxidation process in a nitrogen-containing atmosphere.
Illustratively, the nitrogen-containing atmosphere gas includes at least one of ammonia, nitric oxide, and nitrous oxide.
Illustratively, forming the gate dielectric layer includes:
Thinning the mask layer to a preset thickness;
And etching and removing part of the mask layer to expose part of the surface of the substrate, so as to form the gate dielectric layer.
Illustratively, after removing a portion of the mask layer to allow the remaining mask layer to function as the gate dielectric layer, the method further comprises:
And forming a source region and a drain region in the body region and in the drift region, wherein the source region and the drain region are respectively positioned at two sides of the gate structure, and the source region and the drain region have a first conductivity type.
Illustratively, the substrate further has a well region formed therein, the body region and the drift region being located in the well region, the well region having the first conductivity type.
Illustratively, the field oxide layer includes a field oxide region and bird's beak regions located on both sides of the field oxide region, the field oxide region having a thickness in the range of 0.5 μm to 0.8 μm.
Illustratively, the field oxide layer includes a field oxide region and beak regions located on both sides of the field oxide region, the beak regions having a width in the range of 0.1 μm to 0.5 μm.
Another aspect of the present invention provides a semiconductor device manufactured by the above method.
In yet another aspect, the present invention provides an electronic apparatus including the semiconductor device described above.
According to the semiconductor device, the manufacturing method thereof and the electronic device, the mask layer is formed, and then the field oxide layer is formed in the groove by taking the mask layer as the mask, so that the beak effect can be effectively restrained, the width of the beak area of the field oxide layer is reduced, the current path is shorter, the on-resistance of the device can be further reduced, meanwhile, a thicker field oxide layer can be formed, the breakdown voltage of the device can be further improved, the manufacturing process stability and the realizability are high, and the device performance is improved.
Drawings
The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention. In the accompanying drawings:
fig. 1 is a schematic cross-sectional view showing a related art semiconductor device manufactured by a LOCOS process to obtain a field oxide layer in a gate field plate structure;
Fig. 2 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 3A to 3F are schematic cross-sectional views showing a semiconductor device obtained by sequentially carrying out a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In order to provide a thorough understanding of the present invention, detailed steps and structures will be presented in the following description in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
In the related art, the field oxide layer in the gate field plate structure is generally manufactured by using a LOCOS process, however, as shown in fig. 1, in the process of manufacturing the field oxide layer 110 by using the LOCOS process, a bird's beak effect occurs, that is, oxygen atoms laterally diffuse into an active region to form a bird's beak structure, which causes the curvature of the field oxide layer to be reduced, and further causes the current path of the field oxide layer to be prolonged, resulting in the on-resistance of the device to be high, even resulting in the breakdown of the device, and the bird's beak structure also limits the thickness of the field oxide layer, so that a thicker field oxide layer cannot be formed, and the thicker field oxide layer cannot be formed, so that the higher breakdown voltage of the device cannot be obtained, and further the device performance is limited.
Accordingly, in view of the foregoing technical problems, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 2, which mainly includes the following steps:
step S1, providing a substrate, wherein a body region and a drift region extending from the surface of the substrate into the substrate are formed in the substrate, the drift region is of a first conductivity type, and the body region is of a second conductivity type;
Step S2, forming a mask layer on the surface of the substrate;
step S3, patterning the mask layer to expose part of the drift region, and etching the substrate to form a groove in the drift region;
S4, forming a field oxide layer, wherein the field oxide layer fills the groove, and the top surface of the field oxide layer is higher than the surface of the substrate;
Step S5, removing part of the mask layer to enable the rest mask layer to be used as a gate dielectric layer, wherein the gate dielectric layer covers part of the surfaces of the body region and part of the drift region, and one side wall of the gate dielectric layer is in contact with the field oxide layer;
And S6, forming a gate electrode layer, wherein the gate electrode layer covers the gate dielectric layer and part of the top surface of the field oxide layer, and the gate dielectric layer and the gate electrode layer form a gate structure.
According to the manufacturing method of the semiconductor device, the mask layer is formed, and then the field oxide layer is formed in the groove by taking the mask layer as a mask, so that the bird's beak effect can be effectively restrained, the width of the bird's beak area of the field oxide layer is reduced, the current path is shorter, the on-resistance of the device can be further reduced, meanwhile, a thicker field oxide layer can be formed, the breakdown voltage of the device can be further improved, the manufacturing process stability and the realizability are strong, and the device performance is improved.
Example 1
Next, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to fig. 2 to 3F, wherein fig. 2 shows a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 3A to 3F show schematic cross-sectional views of semiconductor devices obtained by sequentially carrying out the method for manufacturing a semiconductor device according to an embodiment of the present invention.
Illustratively, the method of fabricating a semiconductor device of the present invention comprises the steps of:
first, step S1 is performed to provide a substrate having a body region and a drift region formed therein extending from a surface of the substrate into the substrate, the drift region having a first conductivity type and the body region having a second conductivity type.
In one example, the substrate 300 is a bulk silicon substrate, which may include at least one of Si, ge, siGe, siC, siGeC, inAs, gaAs, inP, inGaAs or other III/V compound semiconductors, or the substrate 300 may also include silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like. Although a few examples of materials from which substrate 300 may be formed are described herein, any material that may serve as substrate 300 falls within the spirit and scope of the present invention.
In one example, as shown in fig. 3A, the drift region 302 has a first conductivity type and the body region 301 has a second conductivity type, wherein the first conductivity type is an N-type conductivity type, the second conductivity type is a P-type conductivity type, or the first conductivity type is a P-type conductivity type, the second conductivity is an N-type conductivity type.
In one example, as shown in fig. 3A, a well region 303 is also formed in the substrate 300, the body region 301 and the drift region 302 being located in the well region 303, the well region 303 having the first conductivity type. Optionally, one side of the drift region 302 is in lateral contact with the body region 301. Illustratively, the substrate 300 may be subjected to an ion implantation process to form a body region 301, a drift region 302, and a well region 303.
Next, step S2 is performed to form a mask layer on the surface of the substrate. Illustratively, as shown in fig. 3B, a mask layer 304 is formed on the surface of the substrate 300.
In one example, the material of the mask layer 304 comprises silicon oxynitride and forming the mask layer 304 on the surface of the substrate 300 comprises forming the mask layer 304 on the surface of the substrate 300 by a thermal oxidation process in a nitrogen-containing atmosphere. Illustratively, the nitrogen-containing atmosphere gas includes at least one of ammonia, nitric oxide, and nitrous oxide. The material of the mask layer 304 may also be selected from other suitable materials according to actual needs.
Next, step S3 is performed to pattern the mask layer to expose a portion of the drift region, and etch the substrate to form a trench in the drift region.
In one example, as shown in FIG. 3C, the mask layer 304 may be patterned to expose portions of the drift region 302 using various etching processes commonly used in the art, the exposed drift region 302 being a region intended to form a field oxide layer, and the substrate 300 may be etched using various etching processes commonly used in the art to form trenches 305 within the drift region 302. The etching process may include a conventional dry etching process and a wet etching process, such as reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods, and a single etching process may be used, or more than one etching process may be used. Illustratively, the depth and width of the trench 305 should be set reasonably according to practical requirements, for example, the depth of the trench 305 should be set according to the thickness required for the field oxide layer to be formed later. Illustratively, the region where the trench 305 is located is defined as a field oxide region, which is a region where a field oxide layer is intended to be formed, a region surrounding the field oxide region is defined as an active region, which is a region where various active components are intended to be formed (e.g., a source region, a drain region, etc. are formed in the active region).
Next, step S4 is performed to form a field oxide layer, where the field oxide layer fills the trench, and a top surface of the field oxide layer is higher than a surface of the substrate.
In one example, as shown in fig. 3D, a LOCOS process may be used to form a field oxide layer 306 filling the trench 305, i.e., the field oxide layer 306 is grown by thermal oxidation in a region not covered by the mask layer 304, and a surface of the field oxide layer 306 is higher than a surface of the substrate 300. Specifically, during thermal oxidation, oxygen atoms react with silicon in the substrate 300 exposed at the bottom of the trench 305 to form an oxide layer, and the top surface of the field oxide layer 306 formed is raised to be higher than the top surface of the substrate 300 because the oxide layer formed is thicker than the consumed silicon.
In one example, during the process of forming the field oxide layer 306, the mask layer 304 plays a role of a mask, and due to the existence of the mask layer 304, the bird's beak effect can be effectively inhibited, the width of the bird's beak region of the field oxide layer 306 is reduced, so that the current path is shorter, and further, the on-resistance of the device can be reduced, and meanwhile, the narrower bird's beak region enables the thicker field oxide layer 306 to be formed, so that the breakdown voltage of the device can be improved, and the manufacturing process stability and the realizability are strong, and the device performance is improved.
In one example, as shown in fig. 3D, the field oxide layer 306 includes a field oxide region and bird's beak regions (i.e., bird's beak-like structures) located at two sides of the field oxide region, wherein the field oxide region is a region of the field oxide layer 306 located within a predefined field oxide region, and the bird's beak region is a region of the field oxide layer 306 extending into the active region due to bird's beak effect. In this embodiment, the thickness range of the field oxide region is 0.5 μm to 0.8 μm, and in other embodiments, the thickness range of the field oxide region may be other suitable ranges, which is worth to be explained that, because in the scheme of the present application, the bird beak effect is suppressed, the bird beak region is narrower, so that a thicker field oxide region can be formed, and the breakdown voltage of the device can be further improved. In this embodiment, the width of the beak area is in the range of 0.1 μm to 0.5 μm, and in other embodiments, the width of the beak area may be in other suitable ranges, which is worth noting that, because the beak effect is suppressed, the beak area is narrower, so that the current path is shorter, and the on-resistance of the device can be reduced. Illustratively, the width of the beak region referred to herein refers to the width of the beak region in a direction perpendicular to the contact surface of the beak region and the field oxide region (i.e., the lateral diffusion direction of the field oxide layer 306).
Next, step S5 is performed, where a portion of the mask layer is removed to enable the remaining mask layer to be used as a gate dielectric layer, the gate dielectric layer covers a portion of the body region and a portion of the surface of the drift region, and a sidewall of the gate dielectric layer contacts the field oxide layer.
In one example, as shown in fig. 3E and 3F, after removing a portion of the mask layer 304, the remaining mask layer 304 may be used as the gate dielectric layer 307 of a subsequently formed gate structure without the need to reform the gate dielectric layer, simplifying process steps. Specifically, as shown in fig. 3E and 3F, forming the gate dielectric layer 307 as shown in fig. 3F includes, firstly, thinning the mask layer 304 to a predetermined thickness as shown in fig. 3E, where the predetermined thickness is a target thickness of the gate dielectric layer 307, and the predetermined thickness should be set reasonably according to practical requirements, where the mask layer 304 may be thinned by various conventional processes in the art, for example, a grinding process or an etching process, and then, as shown in fig. 3F, etching to remove a portion of the mask layer to expose a portion of the surface of the substrate 300, forming the gate dielectric layer 307, where the gate dielectric layer 307 covers a portion of the body region 301 and a portion of the surface of the drift region 302, and where a sidewall of the gate dielectric layer 307 contacts the field oxide layer 306, where the gate dielectric layer 307 plays a role in isolation and protection. Illustratively, the top surface of field oxide layer 306 is higher than the top surface of gate dielectric layer 307.
Finally, step S6 is executed to form a gate electrode layer, where the gate electrode layer covers the gate dielectric layer and a portion of the top surface of the field oxide layer, and the gate dielectric layer and the gate electrode layer form a gate structure.
In one example, as shown in fig. 3F, the gate electrode layer 308 covers the top surfaces of the gate dielectric layer 307 and a portion of the field oxide layer 306, and the gate dielectric layer 307 and the gate electrode layer 308 form a gate structure. Illustratively, the gate electrode layer 308 is comprised of a polysilicon material, and metals, metal nitrides, metal silicides, or similar compounds may also be generally used as the material of the gate layer. Illustratively, the number of gate electrode layers 308 may be at least one, and gate electrode layers 308 may act as field plates.
In one example, as shown in fig. 3F, the gate structure may further include sidewalls 309 on both sides of the gate electrode layer 308, where the sidewalls 309 can increase the channel length of the device, reducing short channel effects and hot carrier effects due to short channel effects. Sidewall spacers 309 may be formed using various deposition methods commonly used in the art, such as by Chemical Vapor Deposition (CVD). By way of example, sidewall 309 may be a single layer or a multi-layer structure, such as a single layer silicon dioxide structure, or a double layer structure of a single layer silicon dioxide and a single layer silicon nitride, or a triple layer structure of a double layer silicon dioxide and a single layer silicon nitride, as the present application is not limited thereto.
In one example, as shown in fig. 3D to 3F, after removing a portion of the mask layer 304 to allow the remaining mask layer 304 to serve as the gate dielectric layer 307, the method of the present application further includes forming a source region 310 located in the body region 301 and a drain region 311 located in the drift region 302, the source region 310 extending from a surface of the body region 301 into the body region 301 and adjacent to a side of the gate structure adjacent to the body region 301, the source region 310 and the drain region 311 being located on opposite sides of the gate structure, respectively, the source region 310 and the drain region 311 having a first conductivity type, the source region 310 and the drain region 311 being both heavily doped regions. Illustratively, the source region 310 and the drain region 311 may be formed by an ion implantation process followed by a rapid thermal annealing process, with the doping within the source region 310 and the drain region 311 being activated with a high temperature of 900 to 1050 degrees celsius, and simultaneously repairing the lattice structure of the surface of the semiconductor substrate damaged in each ion implantation process. Illustratively, the present application does not specifically limit the order of formation of the gate electrode layer 308, the source region 310, and the drain region 311. Illustratively, as shown in fig. 3D to 3F, after removing a portion of the mask layer 304 to make the remaining mask layer 304 serve as the gate dielectric layer 307, the present application further includes a step of forming a body contact region 312 in the body region 301, the body contact region 312 having a second conductivity type, the body contact region 312 having a doping concentration higher than that of the body region 301, the body contact region 312 being operable as an extraction region for the body region 301. Illustratively, a salicide layer may also be formed over the gate electrode layer 308, the source region 310, and the drain region 311. Illustratively, shallow trench isolation (shallow trench isolation, STI) structures may also be formed in the body region 301 and the drift region 302.
In one example, the gate structure and the field oxide layer 306 form a gate field plate structure that can weaken the surface electric field of the drift region 302, facilitating an increase in the breakdown voltage of the device.
In one example, taking the first conductivity type as N-type conductivity and the second conductivity type as P-type conductivity as an example, by applying a voltage to the gate structure, free electrons in the body region 301 can be attracted to the gate structure and holes in the body region 301 can be repelled, thereby forming an N-channel in the body region 301, where free electrons can move from the source region 310 to the drain region 311 through the N-channel.
In one example, the method of the present application further includes forming a first conductive contact hole and a second conductive contact hole, etc., for extracting the source region 310 and the drain region 311, respectively, wherein the first conductive contact hole is further electrically connected to the first metal layer as a source electrode, and the second conductive contact hole is further electrically connected to the second metal layer as a drain electrode. Optionally, a conductive contact hole electrically connected to the body contact region 312 may also be formed, and the conductive contact hole may also be electrically connected to the source electrode. In some embodiments, the gate structure may be connected to the source.
In one example, the length direction of the body region 301 is the direction from the source region 310 to the drift region 302, and the width direction of the body region 301 is the direction perpendicular to the length direction of the body region 301.
In one example, the gate structure, the source region 310, the body region 301, and the drift region 302 all extend continuously in the width direction of the body region 301, wherein the first conductive contact hole may include one or more and optionally be partially disposed in the source region 310 and the second conductive contact hole may include one or more and optionally be partially disposed in the drift region 302, for example in the drain region 311 in the drift region 302.
The method for manufacturing the semiconductor device of the present invention has been described so far, and the method for manufacturing the semiconductor device of the present invention may further include other steps, which are not described in detail herein, and it should be noted that the sequence of the steps may be adjusted without any conflict.
In summary, the method for manufacturing a semiconductor device according to the embodiment of the invention forms the mask layer, and forms the field oxide layer in the trench by using the mask layer as the mask, so that the bird's beak effect can be effectively inhibited, the width of the bird's beak region of the field oxide layer is reduced, the current path is shorter, the on-resistance of the device can be further reduced, and simultaneously, a thicker field oxide layer can be formed, so that the breakdown voltage of the device can be further improved, the process stability and the realizability are strong, and the device performance is improved.
Example two
The present application also provides a semiconductor device obtained by the method of the first embodiment. Since the device of the present application is obtained by the aforementioned method, the same advantages as the aforementioned method are obtained.
In one example, as shown in fig. 3F, the semiconductor device includes a substrate 300, a body region 301 and a drift region 302 are formed in the substrate 300, the drift region 302 has a first conductivity type, and the body region 301 has a second conductivity type, wherein the first conductivity type is an N-type conductivity type, the second conductivity type is a P-type conductivity type, or the first conductivity type is a P-type conductivity type, and the second conductivity is an N-type conductivity type.
In one example, the substrate 300 is a bulk silicon substrate, which may include at least one of Si, ge, siGe, siC, siGeC, inAs, gaAs, inP, inGaAs or other III/V compound semiconductors, or the substrate 300 may also include silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like. Although a few examples of materials from which substrate 300 may be formed are described herein, any material that may serve as substrate 300 falls within the spirit and scope of the present invention.
In one example, as shown in fig. 3F, a well region 303 is also formed in the substrate 300, the body region 301 and the drift region 302 being located in the well region 303, the well region 303 having the first conductivity type. Illustratively, the substrate 300 may be subjected to an ion implantation process to form a body region 301, a drift region 302, and a well region 303.
In one example, a field oxide layer 306 is further included, the field oxide layer 306 filling the trench 305 and a top surface of the field oxide layer 306 being higher than a surface of the substrate 300.
In one example, as shown in fig. 3F, the field oxide layer 306 includes a field oxide region and bird's beak regions (i.e., bird's beak-like structures) located at two sides of the field oxide region, wherein the field oxide region is a region of the field oxide layer 306 located within a predefined field oxide region, and the bird's beak region is a region of the field oxide layer 306 extending into the active region due to bird's beak effect. In this embodiment, the thickness of the field oxide region ranges from 0.5 μm to 0.8 μm, and in other embodiments, the thickness of the field oxide region may also range from other suitable ranges, which is worth noting that, because the beak effect is suppressed, the beak region is narrower, so that a thicker field oxide region can be formed, and the breakdown voltage of the device can be further improved. In this embodiment, the width of the beak area is in the range of 0.1 μm to 0.5 μm, and in other embodiments, the width of the beak area may be in other suitable ranges, which is worth noting that, because the beak effect is suppressed, the beak area is narrower, so that the current path is shorter, and the on-resistance of the device can be reduced. Illustratively, the width of the beak region referred to herein refers to the width of the beak region in a direction perpendicular to the contact surface of the beak region and the field oxide region (i.e., the lateral diffusion direction of the field oxide layer 306).
In one example, as shown in fig. 3F, the gate structure further includes a gate dielectric layer 307 and a gate electrode layer 308, where the gate dielectric layer 307 and the gate electrode layer 308 form a gate structure, and the gate dielectric layer 307 covers a portion of the surfaces of the body region 301 and a portion of the drift region 302, and a sidewall of the gate dielectric layer 307 contacts the field oxide layer 306, and the gate dielectric layer 307 performs an isolation and protection function, and the gate electrode layer 308 covers top surfaces of the gate dielectric layer 307 and a portion of the field oxide layer 306. Illustratively, the gate electrode layer 308 is comprised of a polysilicon material, and metals, metal nitrides, metal silicides, or similar compounds may also be generally used as the material of the gate layer. Illustratively, the number of gate electrode layers 308 may be at least one, and gate electrode layers 308 may act as field plates. Illustratively, the top surface of field oxide layer 306 is higher than the top surface of gate dielectric layer 307.
In one example, as shown in fig. 3F, the semiconductor device further includes a source region 310 located in the body region 301 and a drain region 311 located in the drift region 302, where the source region 310 extends from the surface of the body region 301 into the body region 301 and is adjacent to one side of the gate structure near the body region 301, the source region 310 and the drain region 311 are located on two sides of the gate structure, respectively, the source region 310 and the drain region 311 have the first conductivity type, and the source region 310 and the drain region 311 may be heavily doped regions. Illustratively, a body contact region 312 in the body region 301 is also included, the body contact region 312 having a second conductivity type, the body contact region 312 having a higher doping concentration than the body region 301, the body contact region 312 being operable as an extraction region for the body region 301. Illustratively, a salicide layer may also be formed over the gate electrode layer 308, the source region 310, and the drain region 311. Illustratively, STI structures may also be formed in the body region 301 and the drift region 302.
In one example, the gate structure and the field oxide layer 306 form a gate field plate structure that can weaken the surface electric field of the drift region 302, facilitating an increase in the breakdown voltage of the device.
In one example, taking the first conductivity type as N-type conductivity and the second conductivity type as P-type conductivity as an example, by applying a voltage to the gate structure, free electrons in the body region 301 can be attracted to the gate structure and holes in the body region 301 can be repelled, thereby forming an N-channel in the body region 301, where free electrons can move from the source region 310 to the drain region 311 through the N-channel.
In one example, the semiconductor device further comprises a first conductive contact hole and a second conductive contact hole for leading out the source region and the drain region respectively, wherein the first conductive contact hole is further electrically connected with the first metal layer serving as a source electrode, and the second conductive contact hole is further electrically connected with the second metal layer serving as a drain electrode. Optionally, a conductive contact hole electrically connected to the body contact region 312 may be further included, and the conductive contact hole may be electrically connected to the source electrode.
Thus, the description of the structure of the semiconductor device of the present invention is completed, and other constituent structures may be included in the complete device, which will not be described in detail herein.
The semiconductor device of the embodiment of the invention is manufactured by adopting the method, the mask layer is formed, and then the field oxide layer is formed in the groove by taking the mask layer as a mask, so that the bird's beak effect can be effectively inhibited, the width of the bird's beak area of the field oxide layer is reduced, the current path is shorter, the on-resistance of the device can be further reduced, and meanwhile, a thicker field oxide layer can be formed, so that the breakdown voltage of the device can be further improved, the manufacturing process stability and the realizability are strong, and the device performance is improved.
Example III
In another embodiment of the present invention, an electronic apparatus is provided, including the semiconductor device described above.
The electronic device of the embodiment may be any electronic product or apparatus such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, or any intermediate product including the semiconductor device. The electronic device provided by the embodiment of the invention has better performance due to the use of the semiconductor device.
Although a number of embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various modifications and alterations may be made in the arrangement and/or component parts of the subject matter within the scope of the disclosure, the drawings, and the appended claims. In addition to modifications and variations in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
Providing a substrate, wherein a body region and a drift region extending from the surface of the substrate into the substrate are formed in the substrate, the drift region is of a first conductivity type, and the body region is of a second conductivity type;
Forming a mask layer on the surface of the substrate;
Patterning the mask layer to expose a portion of the drift region and etching the substrate to form a trench within the drift region;
Forming a field oxide layer, wherein the field oxide layer fills the groove, and the top surface of the field oxide layer is higher than the surface of the substrate;
Removing part of the mask layer to enable the rest of the mask layer to be used as a gate dielectric layer, wherein the gate dielectric layer covers part of the surfaces of the body region and part of the drift region, and one side wall of the gate dielectric layer is in contact with the field oxide layer;
and forming a gate electrode layer, wherein the gate electrode layer covers the gate dielectric layer and part of the top surface of the field oxide layer, and the gate dielectric layer and the gate electrode layer form a gate structure.
2. The method of claim 1, wherein the mask layer comprises silicon oxynitride, and wherein forming the mask layer on the surface of the substrate comprises:
And forming the mask layer on the surface of the substrate through a thermal oxidation process in a nitrogen-containing atmosphere.
3. The method according to claim 2, wherein the gas in the nitrogen-containing atmosphere includes at least one of ammonia gas, nitric oxide, and nitrous oxide.
4. The method of manufacturing of claim 1, wherein forming the gate dielectric layer comprises:
Thinning the mask layer to a preset thickness;
And etching and removing part of the mask layer to expose part of the surface of the substrate, so as to form the gate dielectric layer.
5. The method of manufacturing of claim 1, wherein after removing a portion of the mask layer to allow the remaining mask layer to function as the gate dielectric layer, the method further comprises:
And forming a source region and a drain region in the body region and in the drift region, wherein the source region and the drain region are respectively positioned at two sides of the gate structure, and the source region and the drain region have a first conductivity type.
6. The method of manufacturing of claim 1, wherein a well region is also formed in the substrate, the body region and the drift region being located in the well region, the well region having the first conductivity type.
7. The method of claim 1, wherein the field oxide layer comprises a field oxide region and bird's beak regions located on both sides of the field oxide region, the field oxide region having a thickness in the range of 0.5 μm to 0.8 μm.
8. The method of claim 1, wherein the field oxide layer comprises a field oxide region and bird's beak regions located on both sides of the field oxide region, the bird's beak regions having a width in the range of 0.1 μm to 0.5 μm.
9. A semiconductor device, characterized in that it is manufactured by the method according to any one of claims 1-8.
10. An electronic device comprising the semiconductor device according to claim 9.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1145532A (en) * | 1995-06-28 | 1997-03-19 | 现代电子产业株式会社 | Method for fabricating field oxide layer in semiconductor device |
| US5972777A (en) * | 1997-07-23 | 1999-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming isolation by nitrogen implant to reduce bird's beak |
| CN104299984A (en) * | 2013-07-19 | 2015-01-21 | 北大方正集团有限公司 | Semiconductor device and manufacture method thereof |
| CN108511346A (en) * | 2018-03-05 | 2018-09-07 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of LDMOS device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1145532A (en) * | 1995-06-28 | 1997-03-19 | 现代电子产业株式会社 | Method for fabricating field oxide layer in semiconductor device |
| US5972777A (en) * | 1997-07-23 | 1999-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming isolation by nitrogen implant to reduce bird's beak |
| CN104299984A (en) * | 2013-07-19 | 2015-01-21 | 北大方正集团有限公司 | Semiconductor device and manufacture method thereof |
| CN108511346A (en) * | 2018-03-05 | 2018-09-07 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of LDMOS device |
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