CN119317100A - A three-dimensional storage device and a method for forming the same - Google Patents

Abstract

A three-dimensional (3D) memory device is disclosed, which includes: a memory array chip, including: a stack including alternating conductive layers and dielectric layers; a memory structure vertically extending through the stack; wherein the memory structure includes a memory layer located at a sidewall of the memory structure, and a conductive material filled in the memory structure, and the memory structure includes a first side and a second side opposite to the first side; wherein the memory layer includes: a first portion corresponding to a capacitor structure, the first portion including a first material; and a second portion corresponding to a transistor structure, the second portion including a second material different from the first material.

Description

Three-dimensional memory device and forming method thereof

Technical Field

The present disclosure relates generally to the field of semiconductor technology, and more particularly, to a three-dimensional (3D) memory device and a method of forming the same.

Background

Dynamic Random Access Memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell having a capacitor and an array transistor, both of which are typically based on Metal Oxide Semiconductor (MOS) technology. The capacitor may be set to a charged state or a discharged state. These two states are taken to represent two values of bits, which are conventionally referred to as 0 and 1. The DRAM further includes peripheral transistors to form peripheral circuits. Peripheral circuits and array transistors handle data input/output (I/O) and memory cell operations (e.g., write or read).

As DRAM technology moves toward higher density and high capacity, for example, toward a 10nm node, the number of capacitors increases sharply, and the size of the capacitors decreases sharply, so that both the density and the size of the capacitors gradually approach the limit. At small-size nodes, the capacitor manufacturing process is more complex, and the leakage is more remarkable, so that the performance of the DRAM is reduced.

Disclosure of Invention

Embodiments of a three-dimensional memory device and method of forming the same are described in this disclosure.

One aspect of the present disclosure provides a three-dimensional (3D) memory device comprising a memory array chip comprising a stack comprising alternating conductive layers and dielectric layers, a memory structure extending vertically through the stack, wherein the memory structure comprises a memory layer at a sidewall of the memory structure, and a conductive material filled in the memory structure, and the memory structure comprises a first side and a second side opposite the first side, wherein the memory layer comprises a first portion corresponding to a capacitor structure, the first portion comprising a first material, and a second portion corresponding to a transistor structure, the second portion comprising a second material different from the first material.

In some examples, the first material comprises a ferroelectric material and the second material comprises an oxide dielectric material.

In some examples, the first material comprises a crystalline ferroelectric material and the second material comprises an amorphous ferroelectric material.

In some examples, the second portion extends through one of the conductive layers.

In some examples, the 3D memory device further includes a first contact structure in contact with one side of the memory structure and a second contact structure in contact with the conductive layer of the stack.

In some examples, the first contact structure is in contact with the first side of the storage structure and the second portion of the memory layer is closer to the first side than the first portion, wherein the first material is also located on the second side of the storage structure.

In some examples, the first contact structure is in contact with the second side of the storage structure, and the second portion of the memory layer is closer to the second side than the first portion.

In some examples, the memory array chip is provided with a first bonding layer and the 3D memory device further includes a peripheral circuit chip including a second bonding layer, wherein the first bonding layer of the memory array chip is bonded to the second bonding layer of the peripheral circuit chip, and wherein the first contact structure is located on a side of the memory array chip near the peripheral circuit chip when the first contact structure is in contact with the first side of the memory structure and on a side of the memory array chip remote from the peripheral circuit chip when the first contact structure is in contact with the second side of the memory structure.

In some examples, the 3D memory device further includes a peripheral circuit chip including a substrate and a peripheral circuit layer, wherein the memory array chip is formed directly on the peripheral circuit layer, and wherein the first contact structure is located on a side of the memory array chip remote from the peripheral circuit chip.

Another aspect of the present disclosure provides a method of forming a 3D memory device, including forming a memory array chip, including forming a substrate, forming a stack including alternating conductive layers and dielectric layers on the substrate, etching a trench through the stack, the etching stopping on a surface of the substrate, forming a memory layer along sidewalls and a bottom of the trench, and filling conductive material into the trench, wherein the memory layer includes a first portion corresponding to a capacitor structure to be formed, the first portion including a first material, and a second portion corresponding to a transistor structure to be formed, the second portion including a second material different from the first material.

In some examples, forming the memory layer includes depositing the first material, performing planarization to remove the first material on a surface of the stack, etching back the layer of the first material, and depositing the second material in a recess left after etching back the layer of the first material.

In some examples, the depth of the etch back of the layer of the first material spans one of the conductive layers.

In some examples, the first material comprises a ferroelectric material and the second material comprises an oxide dielectric material.

In some examples, the first material comprises a crystalline ferroelectric material and the second material comprises an amorphous ferroelectric material.

In some examples, after filling the conductive material, the method further includes performing a planarization operation to remove excess of the conductive material and the second material on the surface of the stack.

In some examples, the method further includes forming a first contact hole exposing the conductive material and a second contact hole exposing the conductive layer in the stack, forming a spacer layer on sidewalls of the second contact hole, and depositing a barrier layer and filling contact material on sidewalls and bottom of the first contact hole and the second contact hole.

In some examples, the method further includes forming a first bonding layer on the memory array chip, forming a peripheral circuit chip including a second bonding layer, bonding the memory array chip to the peripheral circuit chip by bonding the first bonding layer to the second bonding layer, wherein a first contact structure in contact with the transistor structure is located on a side of the memory array chip near the peripheral circuit chip or on a side of the memory array chip remote from the peripheral circuit chip.

In some examples, the method further includes forming a peripheral circuit chip including a second substrate and a peripheral circuit layer prior to forming the memory array chip, and forming the memory array chip on the peripheral circuit layer, wherein a first contact structure in contact with the transistor structure is located on a side of the memory array chip remote from the peripheral circuit chip.

Another aspect of the present disclosure provides a memory system including a memory device configured to store data, the memory device including a memory array chip including a stack including alternating conductive layers and dielectric layers, a memory structure extending vertically through the stack, wherein the memory structure includes a memory layer located at a sidewall of the memory structure, and a conductive material filled in the memory structure, and the memory structure includes a first side and a second side opposite the first side, wherein the memory layer includes a first portion corresponding to a capacitor structure, the first portion including a first material, and a second portion corresponding to a transistor structure, the second portion including a second material different from the first material, and a memory controller coupled to the memory device and configured to control the memory device.

Other aspects of the present disclosure will be appreciated by those skilled in the art from the description, claims, and drawings of the present disclosure.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

FIG. 1 shows a schematic diagram of a 3D memory device;

FIG. 2 shows a schematic cross-sectional view of a memory array chip according to an embodiment of the disclosure;

FIG. 3 shows a schematic cross-sectional view of a memory array chip according to another embodiment of the present disclosure;

FIG. 4 illustrates a flowchart of a method of forming a memory array chip according to an embodiment of the present disclosure;

FIG. 5 illustrates a flowchart of a method of forming a memory layer in a memory array chip according to an embodiment of the present disclosure;

6A-6L illustrate cross-sectional views of a device structure at various processes in a method of forming a memory array chip, in accordance with an embodiment of the present disclosure;

fig. 7A and 7B illustrate cross-sectional views of a 3D memory device according to an embodiment of the present disclosure;

FIG. 8 illustrates a cross-sectional view of a 3D memory device according to another embodiment of the present disclosure;

Fig. 9 illustrates a block diagram of an exemplary system with a memory device, according to an embodiment of the present disclosure.

Features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Embodiments of the present disclosure will be described with reference to the accompanying drawings.

Detailed Description

While specific constructions and arrangements are discussed, it should be understood that this is done for illustrative purposes only. One skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Generally, the terms may be understood, at least in part, based on the use of context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, at least in part depending on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular usage or a plural usage, depending at least in part on the context. In addition, again, depending at least in part on the context, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the existence of additional factors that are not necessarily explicitly described.

It should be readily understood that "on," "over" and "above" in this disclosure should be interpreted in the broadest manner so that "on" means not only directly on something but also includes on something with an intermediate feature or layer in between, and so that "on" or "above" includes not only the meaning on or over something but also the meaning on or over something without an intermediate feature or layer in between (i.e., directly on something).

Further, spatially relative terms, such as "below," "beneath," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

Fig. 1 shows a schematic diagram of a 3D memory device 100. The 3D memory device 100 may represent an example of a bonded chip, or an example of a monolithically integrated memory device. In the former, components of the 3D memory device 100 (e.g., the memory array layer 104 and the peripheral circuit layer 102) may be formed on different substrates, respectively, and then combined to form a bonded chip. In the latter, the memory array layer 104 and the peripheral circuit layer 102 of the 3D memory device 100 may be integrated together, for example, after the peripheral circuit layer 102 is manufactured, the memory array layer 104 may be manufactured over a dielectric layer of the peripheral circuit layer 102. The 3D memory device 100 may include a substrate 101, a peripheral circuit layer 102 including peripheral circuits, and a memory array layer 104 protecting a memory structure.

The peripheral circuitry (or "control and sense circuitry") may include any suitable digital, analog, and/or mixed signal circuitry for facilitating operation of the memory cell array. For example, the peripheral circuitry may include one or more of page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), input/output (I/O) circuits, charge pumps, voltage sources or generators, current or voltage references, any portion of the functional circuitry described above (e.g., subcircuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). According to some embodiments, peripheral circuitry in peripheral circuitry layer 102 may use Complementary Metal Oxide Semiconductor (CMOS) technology, for example, may be implemented with logic processes (e.g., technology nodes of 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

As shown in fig. 1, the 3D memory device 100 may include a memory array layer 104 including an array of memory cells (memory cell array) that may use transistors as switching and selection devices. In some embodiments, the array of memory cells may comprise an array of DRAM cells. For ease of description, the memory cell array is described in this disclosure using a DRAM cell array as an example. It is understood that the memory cell array is not limited to a DRAM cell array and may include any other suitable type of memory cell array that may use transistors as switching and selection devices, such as a Phase Change Memory (PCM) cell array, a Static Random Access Memory (SRAM) cell array, a Ferroelectric Random Access Memory (FRAM) cell array, a resistive memory cell array, a magnetic memory cell array, a Spin Transfer Torque (STT) memory cell array, to name a few, or any combination thereof.

The memory array layer 104 may be a DRAM device in which the memory cells are provided in the form of an array of DRAM cells. In some embodiments, each DRAM cell includes a capacitor for storing a data bit as a positive or negative charge, and one or more transistors (also referred to as pass transistors) that control (e.g., switch and select) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor, a capacitor (1T 1C) cell. Since the transistor always leaks a small amount of charge, the capacitor slowly discharges, resulting in depletion of the information stored therein. Thus, according to some embodiments, the DRAM cells must be refreshed, for example, by peripheral circuitry in peripheral circuitry layer 102, to retain the data.

At present, the storage density and size of the storage unit of the 1T1C structure are close to the process limit, the electric leakage is obvious, and the holding time is short, so a new storage structure is needed to replace the 1T1C structure to improve the storage density, reduce the electric leakage and improve the storage performance, and meanwhile, the manufacturing flow is simplified.

Note that the x, y, and z axes are included in fig. 1 to further illustrate the spatial relationship of components in 3D memory device 100. The substrate of the 3D memory device may include two lateral surfaces extending laterally in the x-y plane, a top surface on the front side of the wafer on which semiconductor devices may be formed, and a bottom surface on the back side of the wafer opposite the front side. The z-axis is perpendicular to the x-axis and the y-axis.

As used herein, when a substrate is located in the lowest plane of a 3D memory device in the z-direction (a perpendicular direction to the x-y plane, e.g., the thickness direction of the substrate), whether one component (e.g., a layer or device) of the 3D memory device is "above" or "below" another component (e.g., a layer or device) in the z-direction is determined relative to the substrate of the 3D memory device. The same concepts used to describe spatial relationships are applied throughout this disclosure. Furthermore, in the description of the present disclosure, the term "depth" may be used to indicate a distance or length in the z-direction from a top or bottom surface of a reference (e.g., a substrate).

Fig. 2 shows a schematic cross-sectional view of a memory array chip 200 according to an embodiment of the present disclosure. In the embodiment of fig. 2, the memory array chip 200 includes a semiconductor substrate 201, a stack 210 including alternating conductive layers 202 and dielectric layers 204 over the substrate 201, and a memory structure 220 extending vertically through the stack and onto the substrate. In embodiments, the semiconductor substrate 201 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. In some embodiments, the semiconductor substrate 201 may be a doped polysilicon substrate, for example, a P-type doped polysilicon substrate or an N-type doped polysilicon substrate. In an embodiment, the material of the dielectric layer 204 may include an insulating material, which may include at least one of silicon oxide, silicon nitride, doped silicon oxide, organosilicate glass, and an organic insulating material, but is not limited thereto. In an embodiment, the conductive material of the conductive layer 202 may include at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide, for example, but is not limited thereto.

In an embodiment, the storage structure 220 extends vertically in the z-direction through the stack 210 and to the surface of the substrate 201. As shown in fig. 2, the memory structure 220 includes a memory layer on the sidewalls and bottom of the memory structure, and a conductive material 208 filled in the memory structure. For example, the conductive material 208 filled in the memory structure 220 may be polysilicon, but is not limited thereto. Polysilicon is described herein as an example. In an embodiment, the memory layer at the sidewalls and bottom of the memory structure comprises two portions, a first portion 212 corresponding to the final formation of the capacitor structure 242 and a second portion 214 corresponding to the final formation of the transistor structure 241. In the embodiment shown in fig. 2, the second portion 214 comprises a sidewall portion of the memory layer closer to the top of the storage structure 220, i.e. the second portion 214 is further away from the substrate 201 than the first portion 212, and the first portion 212 comprises a sidewall portion and a bottom portion of the memory layer closer to the bottom of the storage structure 220, i.e. the first portion 212 is closer to the substrate 201 than the second portion 214. In an embodiment, the first portion comprises a first material and the second portion comprises a second material, the second material being different from the first material.

In some embodiments, the first material used to form the capacitor structure may comprise a ferroelectric material and the second material used to form the transistor structure may comprise an oxide dielectric material, for example, a high-k dielectric material, such as aluminum oxide or hafnium oxide. In other embodiments, the first material used to form the capacitor structure may comprise a crystalline ferroelectric material, and the second material used to form the transistor structure may comprise an amorphous ferroelectric material.

In the embodiment shown in fig. 2, the second part of the memory layer for forming the transistor structure penetrates one conductive layer 202, and the first part of the memory layer for forming the capacitor structure may penetrate a stack of several conductive layers 202 and dielectric layers 204, so that a structure in which one transistor and a plurality of capacitors are connected in series, i.e., a 3d 1tnc memory structure, can be formed in a vertical direction, thereby improving the memory density. In addition, the ferroelectric material is used as a capacitor medium in the capacitor structure to realize the storage and the reading of data, so that the read-write speed is higher, the data retention is good, the power consumption is low, and the reliability is high, thereby improving the performance of the memory device. In addition, the gate dielectric of the transistor can be formed by adopting a ferroelectric material, so that the switching speed of the transistor is improved, the power consumption is reduced, and the performance of the whole memory device is further greatly improved.

In the embodiment shown in fig. 2, the memory array chip 200 further includes a plurality of contact structures. The contact structure includes a first contact structure 226 contacting one side of the storage structure 220, and a second contact structure 222 contacting the conductive layer 202 of the stack 210. In an embodiment, the first contact structure 226 is in direct contact with the polysilicon on one side of the transistor structure 241 to form the drain contact of the transistor and one electrode plate of each capacitor in series underneath, and the second contact structure 222 is in contact with each conductive layer 202 of the stack 210 to form the gate contact of the transistor and the other electrode plate of each capacitor.

Fig. 3 shows a schematic cross-sectional view of a memory array chip 300 according to another embodiment of the present disclosure. The structure of the memory array chip 300 is substantially similar to the memory array chip 200, except that the locations of the first portions 212 for forming the capacitor structures 242 are inverted upside down from the locations of the second portions 214 for forming the transistor structures 241. Specifically, in the embodiment of fig. 3, the memory layer is located only on the sidewalls of the storage structure 220, and not on the bottom. In an embodiment, the first portion comprises a first material and the second portion comprises a second material, the second material being different from the first material.

In some embodiments, the first material used to form the capacitor structure may comprise a ferroelectric material and the second material used to form the transistor structure may comprise an oxide dielectric material, for example, a high-k dielectric material, such as aluminum oxide or hafnium oxide. In other embodiments, the first material used to form the capacitor structure may comprise a crystalline ferroelectric material, and the second material used to form the transistor structure may comprise an amorphous ferroelectric material.

In the embodiment shown in fig. 3, the second part of the memory layer for forming the transistor structure penetrates one conductive layer 202, while the first part of the memory layer for forming the capacitor structure may penetrate a stack of several conductive layers 202 and dielectric layers 204, thereby enabling to form a structure in which one transistor and a plurality of capacitors are connected in series in the vertical direction, i.e., a 3d 1tnc memory structure.

In the embodiment shown in fig. 3, the memory array chip 300 further includes a plurality of contact structures. The contact structure includes a first contact structure 226 contacting one side of the storage structure 220, and a second contact structure 222 contacting the conductive layer 202 of the stack 210. In an embodiment, the first contact structure 226 is in direct contact with the polysilicon on one side of the transistor structure 241 to form a drain contact of the transistor and one electrode plate of each capacitor in series therewith, and the second contact structure 222 is in contact with each conductive layer 202 of the stack 210 to form a gate contact of the transistor and the other electrode plate of each capacitor.

It should be appreciated that in the embodiment shown in fig. 3, the layers underlying the stack 210 are not semiconductor substrates, but rather, in a subsequent memory device formation process, by removing and replacing the semiconductor substrates with other dielectric layers, and then forming the first contact structures 226 described above in the dielectric layers.

Fig. 4 illustrates a flowchart of a method 400 for forming the memory array chip 200 shown in fig. 2, according to an embodiment of the present disclosure. Fig. 5 illustrates a flowchart of a method 500 of forming a memory layer in a memory array chip 200 according to an embodiment of the present disclosure. Fig. 6A-6L illustrate cross-sectional views of a device at various processes in a method of forming a memory array chip, in accordance with an embodiment of the present disclosure. The process flow illustrated in fig. 4 and 5 is explained below in connection with the cross-sectional views of the device structure illustrated in fig. 6A-6L.

The method 400 of fig. 4 begins at operation 402, where a semiconductor substrate 201 is first provided. As described herein, the semiconductor substrate 201 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. In some embodiments, the semiconductor substrate 101 may be a doped polysilicon substrate, for example, a P-type doped polysilicon substrate or an N-type doped polysilicon substrate.

The method 400 proceeds to operation 404 where a stack 210 of conductive and dielectric layers is formed on the semiconductor substrate 201, as shown in fig. 6A. The stack 210 may be formed by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. The stack 210 includes a plurality of alternating conductive layers 202 and dielectric layers 204, that is, each conductive layer 202 may be sandwiched by two adjacent dielectric layers 204 and each dielectric layer 204 may be sandwiched by two adjacent conductive layers 202, except for the top and bottom layers of the stack 210. As described herein, the material of the dielectric layer 204 may include an insulating material, which may include at least one of silicon oxide, silicon nitride, doped silicon oxide, organosilicate glass, and an organic insulating material.

Next, the method 400 proceeds to operation 406, wherein a trench 502 is formed through the stack 210 extending onto the semiconductor substrate, as shown in fig. 6B. In some embodiments, the process of forming the trench 502 may include forming the trench 502 through the stack 210 and extending to the semiconductor substrate 201 by a dry/wet etching process, thereby exposing a surface of the substrate.

Next, the method 400 proceeds to operation 408, wherein a memory layer is formed along the sidewalls and bottom of the trench 502. As described herein, the memory layer includes two portions, a first portion 212 corresponding to the final formation of capacitor structure 242 and a second portion 214 corresponding to the final formation of transistor structure 241. In an embodiment, the first portion 212 comprises a first material and the second portion 214 comprises a second material that is different from the first material. In some embodiments, the first material used to form the capacitor structure may comprise a ferroelectric material and the second material used to form the transistor structure may comprise an oxide dielectric material, for example, a high-k dielectric material, such as aluminum oxide or hafnium oxide. In other embodiments, the first material used to form the capacitor structure may comprise a crystalline ferroelectric material, and the second material used to form the transistor structure may comprise an amorphous ferroelectric material.

Method 500 provides a method for forming a memory layer. The method 500 begins at operation 502, where a first material 512 for forming a capacitor structure is first deposited on the bottom and sidewalls of the trench 502 formed by operation 406, as shown in fig. 6C. In an embodiment, the first material 512 may be formed in the trench 502 by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. As shown in fig. 6C, the first material 512 covers not only the bottom and sidewalls of the trench 502, but also the top surface of the stack 210. As described herein, the first material 512 used to form the capacitor structure may include a ferroelectric material. In other embodiments, the first material 512 used to form the capacitor structure may comprise a crystalline ferroelectric material.

Next, the method 500 proceeds to operation 504, where a planarization operation is performed to remove the first material on the surface of the stack. As shown in fig. 6D, excess first material located on the surface of the stack 210 may be removed after the deposition of the first material 512 by performing a planarization process such as CMP.

Next, the method 500 proceeds to operation 506, wherein the first material located on the sidewalls of the trench is etched back to a height below the top surface of the stack. As shown in fig. 6E, the first material 512 may be etched back by using a wet etching and/or dry etching process such that the first material 512 is at a lower height on the sidewalls of the trench 502 than the top surface of the stack 210, thereby exposing a portion of the stack 210 at the sidewalls of the trench 502. In some embodiments, the depth of the etch back of the first material 512 is a depth corresponding to the depth of one conductive layer 202.

Next, the method 500 proceeds to operation 508, wherein a second material is deposited in the recess on the sidewall of the trench left by etching back the first material layer. As shown in fig. 6F, a second material 514 may be deposited along the sidewalls of the trench 502, i.e., on the exposed portions of the stack 210, by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. As described herein, the second material 514 is different from the first material 512. In some embodiments, the second material used to form the transistor structure may include an oxide dielectric material, for example, a high-k dielectric material, such as aluminum oxide or hafnium oxide. In other embodiments, the second material used to form the transistor structure may comprise an amorphous ferroelectric material.

Returning to fig. 4, the method 400 proceeds to operation 410, wherein the trench is filled with a conductive material. As shown in fig. 6G, a conductive material 508, such as polysilicon, may be deposited in the trenches by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. In an embodiment, the bottom and sidewalls of the trench at this point have been lined with a memory layer comprising a first material 512 and a second material 514, with polysilicon material formed inside the memory layer.

Next, the method 400 proceeds to operation 412, where a planarization operation is performed to remove excess material on top of the stack. As shown in fig. 6H, excess polysilicon 508 located above the top surface of the stack 210 may be removed by performing a planarization process such as CMP. As shown in fig. 6I, the excess second material 514 located on the top surface of the stack 210 may be further removed by performing a planarization process, such as CMP, so that the top surface of the memory structure formed by the first material 512, the second material 514, and the polysilicon material 508 is level with the top surface of the stack 210.

Finally, the method of forming the memory array chip 200 as described in fig. 2 further includes forming a contact structure. As shown in fig. 6J, a dielectric layer is first deposited on the top surface of the structure shown in fig. 6H, and then openings 528 may be etched into the dielectric layer using wet and/or dry etching processes, the locations of the openings 528 corresponding to the locations where the first and second contact structures are to be formed, respectively. In an embodiment, the first contact structure is in direct contact with the polysilicon on a side proximate to the second material 514 to form a drain contact of the transistor and one electrode plate of each capacitor in series underneath, and the second contact structure is in contact with each conductive layer 202 of the stack 210 to form a gate contact of the transistor and the other electrode plate of each capacitor.

As shown in fig. 6K, a spacer layer 530 may be deposited on the sidewalls of the opening 528 by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. In an embodiment, the spacer layer may comprise an insulating material including silicon oxide, silicon nitride, doped silicon oxide, and the like.

As shown in fig. 6L, a dielectric layer 552 may be deposited on the sidewalls and bottom of the opening 528 lined with the spacer layer 530 by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof, followed by a further deposition of a conductive layer 522 to fill the opening, thereby enabling the simultaneous formation of the first and second contact structures in the same process flow.

Through the process flow, the transistor and the capacitor element of the 1TnC structure of the 3D DRAM memory device are integrally formed at one time by using the same process flow, so that the whole framework of the 3D DRAM memory device and the forming process thereof are greatly simplified, and the process cost is reduced.

Fig. 7A and 7B illustrate cross-sectional views of a 3D memory device according to an embodiment of the present disclosure. As shown in fig. 7A, a 3D memory device 700 is shown that includes a memory array chip 602 and a peripheral circuit chip 604. As described previously, the memory device 700 is formed by bonding, wherein the memory array chip 602 and the peripheral circuit chip 604 may be formed on different substrates, respectively, and then bonded together in a face-to-face manner by flip-chip bonding or the like to form a bonded chip. As shown in fig. 7A, there is a bonding interface 644 between the memory array chip 602 and the peripheral circuit chip 604, through which a large number of interconnects (e.g., bonding contacts) may be formed to make direct, short-distance (e.g., micron-sized) electrical connections between the memory array chip 602 and the peripheral circuit chip 604. According to some embodiments, the bonding interface 644 is vertically formed between the memory array chip 602 and the peripheral circuit chip 604 in the 3D memory device 700, and the memory array chip 602 and the peripheral circuit chip 604 are vertically bonded by bonding (e.g., hybrid bonding). Hybrid bonding, also known as "metal/dielectric hybrid bonding", is a direct bonding technique (e.g., bonding between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) and can achieve both metal-to-metal (e.g., copper-to-copper) bonding and dielectric-to-dielectric (e.g., silicon oxide-to-silicon oxide) bonding. Data transfer between the array of memory cells in the memory array chip 602 and the peripheral circuitry in the peripheral circuit chip 604 may be performed through interconnections (e.g., bond contacts) across the bond interface 644.

In the embodiment shown in fig. 7A, the structure of the memory array chip 602 is similar to that of the memory array chip 200 as shown in fig. 2. Note that since the memory array chip 602 is bonded to the peripheral circuit chip 604 by flip-chip bonding, the bottom of the memory structure shown in fig. 2 becomes the top of the memory device in fig. 7A, and the top of the memory structure shown in fig. 2 becomes the bottom in fig. 7A. The memory array chip 602 includes a stack of alternating conductive and dielectric layers, and the memory structure 220 extending vertically through the stack. The memory structure 220 includes a memory layer on the sidewalls and top of the memory structure, and a conductive material 208 filled in the memory structure. In an embodiment, the memory layer on the sidewalls and top of the memory structure 220 includes two portions, a first portion 212 corresponding to the final formation of the capacitor structure and a second portion 214 corresponding to the final formation of the transistor structure. As shown in fig. 7A, the memory structure 220 includes a first side and a second side opposite the first side, wherein the first side is a side near the peripheral circuit chip and the second side is a side far from the peripheral circuit chip. In an embodiment, the second portion 214 includes a sidewall portion of the memory layer closer to the first side of the memory structure 220 and extends through one conductive layer, i.e., the second portion 214 is closer to the peripheral circuit chip relative to the first portion 212, and the first portion 212 includes a sidewall portion and a top portion of the memory layer closer to the second side of the memory structure 220 and extends through one or more conductive layers, i.e., the first portion 212 is farther from the peripheral circuit chip relative to the second portion 214. . In an embodiment, the first portion comprises a first material and the second portion comprises a second material, the second material being different from the first material.

As shown in fig. 7A, the first contact structure is in direct contact with the polysilicon on the second material 214 side of the memory structure 220 on the first side, thereby extracting the drain of the transistor. The second contact structures are respectively in contact with the conductive layers in the stack. Subsequently, the first contact structure and the second contact structure are electrically connected to peripheral circuits in the peripheral circuit chip 604 by interconnects, bonding contacts, or the like, respectively.

Fig. 7B shows a 3D memory device 720 including a memory array chip 602 and a peripheral circuit chip 604. As described previously, the memory device 700 is formed by bonding, wherein the memory array chip 602 and the peripheral circuit chip 604 may be formed on different substrates, respectively, and then bonded together in a face-to-face manner by flip-chip bonding or the like to form a bonded chip.

The 3D memory device 720 shown in fig. 7B is substantially similar to the 3D memory device 700 shown in fig. 7A, except that the structure of the memory array chip 602 in the 3D memory device 720 is similar to that of the memory array chip 300 as shown in fig. 3. In contrast to the memory array chip 200, the locations of the first portions 212 for forming the capacitor structures 242 are inverted upside down from the locations of the second portions 214 for forming the transistor structures 241, and the memory layer is located only on the sidewalls of the memory structures 220. In an embodiment, the memory structure 220 includes a first side and a second side opposite the first side, wherein the first side is a side near the peripheral circuit chip and the second side is a side far from the peripheral circuit chip. In an embodiment, the first portion 212 includes a sidewall portion of the memory layer closer to the first side of the memory structure 220 and extends through one or more conductive layers, i.e., the first portion 212 is closer to the peripheral circuit chip relative to the second portion 214, and the second portion 214 includes a sidewall portion of the memory layer closer to the second side of the memory structure 220 and extends through one conductive layer, i.e., the second portion 214 is farther from the peripheral circuit chip relative to the first portion 212. . The first portion comprises a first material and the second portion comprises a second material, the second material being different from the first material. As shown in fig. 7B, the first contact structure is in direct contact with the polysilicon on the second side of the second material 214 side of the memory structure 220, thereby extracting the drain of the transistor. The second contact structures are respectively in contact with the conductive layers in the stack.

Fig. 8 illustrates a cross-sectional view of a 3D memory device 800 according to another embodiment of the present disclosure. As shown in fig. 8, the 3D memory device 800 includes a memory array chip 702 and a peripheral circuit chip 704. As previously described, 3D memory device 800 may be a monolithically integrated memory device in which memory array chip 702 and peripheral circuit chip 704 may be integrated together, e.g., memory array chip 702 may be fabricated directly over a dielectric layer of peripheral circuit chip 704 after fabrication of peripheral circuit chip 704.

In the embodiment shown in fig. 8, the structure of the memory array chip 702 is similar to that of the memory array chip 200 as shown in fig. 2. Specifically, the memory array chip 702 includes a stack of alternating conductive and dielectric layers, and the memory structure 220 extending vertically through the stack. The memory structure 220 includes a memory layer on the sidewalls and bottom of the memory structure, and a conductive material 208 filled in the memory structure. In an embodiment, the memory layer at the sidewalls and bottom of the memory structure 220 includes two portions, a first portion 212 corresponding to the final formation of the capacitor structure and a second portion 214 corresponding to the final formation of the transistor structure. As shown in fig. 8, the memory structure 220 includes a first side and a second side opposite the first side, wherein the first side is a side near the peripheral circuit chip and the second side is a side far from the peripheral circuit chip. In an embodiment, the first portion 212 includes a sidewall portion and a bottom portion of the memory layer closer to the first side of the memory structure 220 and extends through one or more conductive layers, i.e., the first portion 212 is closer to the peripheral circuit chip than the second portion 214, and the second portion 214 includes a sidewall portion of the memory layer closer to the second side of the memory structure 220 and extends through one conductive layer, i.e., the second portion 214 is closer to the peripheral circuit chip than the first portion 212. In an embodiment, the first portion comprises a first material and the second portion comprises a second material, the second material being different from the first material. As shown in fig. 8, the first contact structure is in direct contact with the polysilicon on the second side of the second material 214 side of the memory structure 220, thereby extracting the drain of the transistor. The second contact structures are respectively in contact with the conductive layers in the stack.

Fig. 9 illustrates a block diagram of an exemplary system 900 with a memory device, according to an embodiment of the disclosure. The system 900 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming machine, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 9, system 900 may include a host 908 and a memory system 902 having one or more memory devices 904 and a memory controller 906. The host 908 may be a processor (e.g., a Central Processing Unit (CPU)) or a system-on-a-chip (SoC) (e.g., an Application Processor (AP)) of the electronic device. The host 908 may be configured to send data to the storage device 904 or receive data from the storage device 904.

The memory device 904 may be any of the memory devices disclosed herein, such as 3D memory devices 700, 720, and 800. In some embodiments, the memory device 904 includes a memory array chip including a stack including alternating conductive and dielectric layers, a memory structure extending vertically through the stack, wherein the memory structure includes a memory layer at a sidewall of the memory structure, and a conductive material filled in the memory structure, and the memory structure includes a first side and a second side opposite the first side, wherein the memory layer includes a first portion corresponding to a capacitor structure, the first portion including a first material, and a second portion corresponding to a transistor structure, the second portion including a second material different from the first material.

According to some embodiments, a memory controller 906 is coupled to the storage device 904 and the host 908 and is configured to control the storage device 904. The memory controller 906 may manage data stored in the memory device 904 and communicate with the host 908. The memory controller 906 may be configured to control operations of the memory device 904, such as read, write, and refresh operations. The memory controller 906 may also be configured to manage various functions with respect to data stored or to be stored in the memory device 904, including but not limited to refresh and timing control, command/request translation, buffering and scheduling, and power management.

In some implementations, the memory controller 906 may also be configured to determine a maximum storage capacity that the computer system may use, a number of banks, a memory type and speed, a memory particle data depth and data width, and other important parameters. The memory controller 906 may also perform any other suitable functions. The memory controller 906 may communicate with external devices (e.g., the host 908) according to a particular communication protocol. For example, the memory controller 906 may communicate with external devices via at least one of various interface protocols, such as a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a firewire protocol, and the like.

The foregoing description of specific embodiments may be readily modified and/or adapted for use in various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (19)

1. A three-dimensional storage device, comprising: Storage array chips, including: A stack comprising alternating conductive and dielectric layers; a storage structure extending vertically through the stack; The storage structure includes a memory layer located at a sidewall of the storage structure, and a conductive material filled in the storage structure, and the storage structure includes a first side and a second side opposite to the first side; Wherein, the memory layer comprises: corresponding to a first portion of the capacitor structure, the first portion comprising a first material; and Corresponding to a second portion of the transistor structure, the second portion includes a second material different from the first material. 2 . The three-dimensional memory device of claim 1 , wherein the first material comprises a ferroelectric material, and the second material comprises an oxide dielectric material. 3 . The three-dimensional memory device of claim 1 , wherein the first material comprises a crystalline ferroelectric material, and the second material comprises an amorphous ferroelectric material. 4. The three-dimensional memory device according to any one of claims 1 to 3, wherein: The second portion penetrates through one of the conductive layers. 5. The three-dimensional memory device according to claim 1, further comprising: a first contact structure in contact with one side of the storage structure; and The second contact structure contacts the conductive layer of the stack. 6. The three-dimensional memory device of claim 5 , wherein the first contact structure contacts the first side of the memory structure, and the second portion of the memory layer is closer to the first side relative to the first portion, wherein the first material is also located on the second side of the memory structure. 7 . The three-dimensional memory device of claim 5 , wherein the first contact structure contacts the second side of the memory structure, and the second portion of the memory layer is closer to the second side than the first portion. 8. The three-dimensional memory device according to claim 6 or 7, wherein the memory array chip is provided with a first bonding layer, and the three-dimensional memory device further comprises: A peripheral circuit chip including a second bonding layer; The first bonding layer of the memory array chip is bonded to the second bonding layer of the peripheral circuit chip, and Wherein, when the first contact structure contacts the first side of the storage structure, the first contact structure is located on a side of the storage array chip close to the peripheral circuit chip, When the first contact structure contacts the second side of the memory structure, the first contact structure is located on a side of the memory array chip away from the peripheral circuit chip. 9. The three-dimensional memory device according to claim 6, further comprising a peripheral circuit chip, the peripheral circuit chip comprising a substrate and a peripheral circuit layer, wherein the memory array chip is directly formed on the peripheral circuit layer, and Wherein, the first contact structure is located on a side of the memory array chip away from the peripheral circuit chip. 10. A method of forming a three-dimensional memory device, comprising: Forming a storage array chip includes the following steps: forming a substrate; forming a stack comprising alternating conductive and dielectric layers on the substrate; etching a trench through the stack, the etching stopping on a surface of the substrate; forming a memory layer along the sidewalls and bottom of the trench; and filling the groove with a conductive material; Wherein, the memory layer comprises: corresponding to a first portion that will form a capacitor structure, the first portion comprising a first material; and Corresponding to a second portion where a transistor structure will be formed, the second portion includes a second material different from the first material. 11. The method of claim 10, wherein forming the memory layer comprises: depositing the first material; performing planarization to remove the first material on the surface of the stack; etching back the layer of the first material; and The second material is deposited in the recess left after etching back the layer of the first material. 12 . The method of claim 11 , wherein the etch-back of the layer of the first material has a depth spanning across one of the conductive layers. 13. The method of claim 10, wherein the first material comprises a ferroelectric material and the second material comprises an oxide dielectric material. 14. The method of claim 10, wherein the first material comprises a crystalline ferroelectric material and the second material comprises an amorphous ferroelectric material. 15. The method according to claim 11, wherein after filling the conductive material, the method further comprises: A planarization operation is performed to remove excess of the conductive material and the second material on the surface of the stack. 16. The method according to claim 10, further comprising: forming a first contact hole and a second contact hole, wherein the first contact hole exposes the conductive material, and the second contact hole exposes the conductive layer in the stack; forming a spacer layer on a sidewall of the second contact hole; and A barrier layer is deposited on the sidewalls and bottoms of the first contact hole and the second contact hole and filled with a contact material. 17. The method according to claim 10, further comprising: forming a first bonding layer on the memory array chip; forming a peripheral circuit chip, the peripheral circuit chip comprising a second bonding layer; The memory array chip is bonded to the peripheral circuit chip by bonding the first bonding layer to the second bonding layer, The first contact structure in contact with the transistor structure is located on a side of the memory array chip close to the peripheral circuit chip or on a side of the memory array chip far from the peripheral circuit chip. 18. The method according to claim 10, further comprising: forming a peripheral circuit chip before forming the memory array chip, the peripheral circuit chip comprising a second substrate and a peripheral circuit layer; and forming the memory array chip on the peripheral circuit layer, Wherein, the first contact structure in contact with the transistor structure is located on a side of the memory array chip away from the peripheral circuit chip. 19. A storage system comprising: A storage device, the storage device being configured to store data, the storage device comprising: Storage array chips, including: A stack comprising alternating conductive and dielectric layers; a storage structure extending vertically through the stack; The storage structure includes a memory layer located at a sidewall of the storage structure, and a conductive material filled in the storage structure, and the storage structure includes a first side and a second side opposite to the first side; Wherein, the memory layer comprises: corresponding to a first portion of the capacitor structure, the first portion comprising a first material; and corresponding to a second portion of the transistor structure, the second portion comprising a second material different from the first material; and A memory controller is coupled to the memory device and is configured to control the memory device.