CN119311067B - A voltage regulating circuit, a power supply circuit, an integrated circuit and an electronic device - Google Patents
A voltage regulating circuit, a power supply circuit, an integrated circuit and an electronic device Download PDFInfo
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- CN119311067B CN119311067B CN202411864044.9A CN202411864044A CN119311067B CN 119311067 B CN119311067 B CN 119311067B CN 202411864044 A CN202411864044 A CN 202411864044A CN 119311067 B CN119311067 B CN 119311067B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
本申请提供一种电压调整电路、电源电路、集成电路、电子设备。该电压调整电路包括第一放大器和差分电路，第一放大器，被配置为当第一输出电压大于第一参考电压时，通过第一输出端向差分电路输出第一电压；当第一输出电压小于或等于第一参考电压时，通过第一输出端向差分电路输出第二电压；差分电路，被配置为当接收第一电压时，对电流源产生的电流进行调整，拉低第一输出电压；当接收第二电压时，将电流源产生的电流提供给第二输出端。本申请的方案能够在稳压电路的负载发生变化时及时对稳压电路的输出进行限幅，提升电路的可靠性。
The present application provides a voltage regulating circuit, a power supply circuit, an integrated circuit, and an electronic device. The voltage regulating circuit includes a first amplifier and a differential circuit. The first amplifier is configured to output a first voltage to the differential circuit through a first output terminal when the first output voltage is greater than a first reference voltage; when the first output voltage is less than or equal to the first reference voltage, the second voltage is output to the differential circuit through the first output terminal; the differential circuit is configured to adjust the current generated by the current source when receiving the first voltage, and lower the first output voltage; when receiving the second voltage, the current generated by the current source is provided to the second output terminal. The solution of the present application can limit the output of the voltage stabilizing circuit in time when the load of the voltage stabilizing circuit changes, thereby improving the reliability of the circuit.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a voltage adjusting circuit, a power supply circuit, an integrated circuit, and an electronic device.
Background
The voltage stabilizing circuit is a circuit capable of outputting a stabilized voltage, and is widely used in electronic systems. During use of the electronic system, the load of the voltage regulator circuit may change, causing the output voltage of the voltage regulator circuit to rise above the maximum voltage value allowed by the design (i.e., the limited voltage). This may cause damage to the gate device or the like to which the voltage stabilizing circuit is used to supply power, which affects the normal operation of the electronic system and reduces the reliability of the electronic system.
Disclosure of Invention
The embodiment of the application provides a voltage adjusting circuit, a power supply circuit, an integrated circuit and electronic equipment, which can timely limit the output of a voltage stabilizing circuit when the load of the voltage stabilizing circuit changes, and improve the reliability of the circuit.
In a first aspect, a voltage regulation circuit is provided that includes a first amplifier and a differential circuit.
The first amplifier comprises a first input end, a second input end and a first output end;
The second input end is connected with a first reference voltage, and the first reference voltage is an amplitude limiting reference voltage of the voltage stabilizing circuit;
the differential circuit comprises a first amplifier, a second amplifier, a first voltage generation circuit, a second voltage generation circuit and a first voltage generation circuit, wherein the first amplifier is configured to output a first voltage to the differential circuit through a first output end when the first output voltage is larger than a first reference voltage, and output a second voltage to the differential circuit through the first output end when the first output voltage is smaller than or equal to the first reference voltage;
the differential circuit comprises a third input end, a fourth input end and a third output end;
The third input end is connected with the first output end, the fourth input end is connected with the bias voltage, and the third output end is connected with the second output end;
The differential circuit further includes a current source configured to regulate a current generated by the current source to pull down the first output voltage when receiving the first voltage and to provide the current generated by the current source to the second output terminal when receiving the second voltage.
The output voltage of the voltage stabilizing circuit can be changed due to the change of the load, and the voltage regulating circuit provided by the application can be intermittently turned on and off according to the change condition of the load to regulate the dynamic change of the output voltage of the voltage stabilizing circuit, so that the condition that the output voltage of the voltage stabilizing circuit is increased to exceed the limiting voltage due to the rapid change of the load is prevented, the normal operation of the voltage stabilizing circuit is maintained, and the reliability of the circuit is improved.
In one implementation, a differential circuit includes a differential pair and a current mirror. The differential pair comprises a first MOS tube and a second MOS tube, wherein the first MOS tube and the second MOS tube are PMOS tubes.
The grid electrode of the first MOS tube is connected with the first output end, and the drain electrode of the first MOS tube is connected with the reference current branch of the current mirror;
The grid electrode of the second MOS tube is connected with bias voltage, and the drain electrode of the second MOS tube is connected with the mirror image current branch circuit of the current mirror;
The sources of the first MOS tube and the second MOS tube are connected with a current source, the current ratio of the reference current branch to the mirror current branch is 1:N, and N is larger than 1.
In one implementation, the current source includes a third MOS transistor and a capacitor disposed between a gate and a source of the third MOS transistor.
Therefore, the current source can provide instantaneous large current when needed by utilizing the charge-discharge characteristics of the capacitor, and the quiescent current consumption is reduced. In this case, the current source is allowed to supply a smaller current, thereby saving circuit power consumption.
In one implementation, the fourth input is connected to a voltage regulator circuit, and the bias voltage is generated by the voltage regulator circuit.
In one implementation, the voltage regulator circuit includes a fifth input configured to be coupled to the second reference voltage, the fifth input coupled to the second input.
The non-inverting input terminal of the first amplifier can be connected with the reference voltage input terminal of the voltage stabilizing circuit so as to reduce the number of reference voltages and the circuit area so as to reduce the cost.
In one implementation, the first amplifier includes a fourth MOS transistor and a fifth MOS transistor, where a ratio of width to length of the fourth MOS transistor to the fifth MOS transistor is 1:M, and M is greater than 1.
In a second aspect, there is provided a power supply circuit comprising:
the voltage stabilizing circuit is used for generating a first output voltage;
The voltage adjusting circuit in the first aspect or any implementation of the first aspect is connected to the voltage stabilizing circuit, and is configured to adjust the first output voltage when a load of the voltage stabilizing circuit changes.
In one implementation, the voltage stabilizing circuit includes a second amplifier, a feedback circuit, and a drive circuit.
The second amplifier includes a fifth input, a sixth input, and a fourth output.
The fifth input end is connected with the second reference voltage, the feedback circuit is connected between the sixth input end and the output end of the voltage stabilizing circuit, and the driving circuit is connected between the fourth output end and the output end of the voltage stabilizing circuit.
In a third aspect, there is provided an integrated circuit comprising the power supply circuit of the above second aspect.
In a fourth aspect, there is provided an electronic device comprising the integrated circuit of the above third aspect.
Drawings
The drawings that follow are briefly described as used in the description of embodiments of the application:
FIG. 1 is a schematic diagram of a voltage stabilizing circuit according to some embodiments of the present application;
FIG. 2 is a schematic diagram of a voltage adjusting circuit according to some embodiments of the present application;
FIG. 3 is a schematic diagram of another voltage adjustment circuit according to some embodiments of the present application;
fig. 4 is a schematic diagram of a power circuit according to some embodiments of the application.
Detailed Description
In order to more clearly describe the technical solutions in the embodiments of the present application, a specific embodiment of the present application will be described below with reference to the accompanying drawings. The drawings described below are only examples of embodiments of the present application, and it will be apparent to those skilled in the art from this description that other drawings and other embodiments can be made without departing from the spirit and scope of the application.
For simplicity of illustration, the drawings schematically show only portions relevant to the corresponding embodiments, they do not represent the actual structure thereof as a product, and more or fewer structures or components may actually be present. In addition, to facilitate a concise understanding of the drawings, more or less similar structures or components may actually be present in the structure or component depicted in the drawings.
In the present application, ordinal terms such as "first," "second," and the like, are used solely to distinguish between the associated objects and are not to be construed as indicating or implying a relative importance or order between such associated objects unless otherwise expressly specified and defined. Furthermore, ordinal words do not represent the number of associated objects. "plurality" includes two or more, and the like. "/" is used to describe a relationship between associated objects, which represents an or relationship between associated objects. "and/or" is used to describe a relationship between associated objects that includes any combination of relationships between associated objects, e.g., "a and/or b" includes "a alone", "b alone", or "a and b". "one or more" or "at least one" of the plurality of objects refers to any object or any combination of the plurality of objects, such as "one or more of a1, a2, a3" or "at least one of a1, a2, a3" including "a1 alone", "a2 alone", "a 3 alone", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".
In embodiments of the application, "connected" includes direct connection or indirect connection between objects, which may be directly connected via a medium (e.g., a wire, a trace, etc.), or may be indirectly connected via other elements, or may be in internal communication.
A voltage regulator circuit is a circuit capable of outputting a stable voltage, which is commonly used in electronic systems such as various integrated circuits (e.g., chips). In one implementation, a power circuit of an electronic system may include a voltage regulator circuit. Fig. 1 is a schematic diagram of a voltage stabilizing circuit according to an embodiment of the application. As shown in fig. 1, the voltage stabilizing circuit 100 includes an amplifier 110, a feedback circuit 120, and a driving circuit 130. The amplifier 110 includes a non-inverting input terminal (+) and an inverting input terminal (-) and an output terminal OUT1. The non-inverting input (+) of the amplifier 110 is connected to the reference voltage vref0. The feedback circuit 120 is connected between the inverting input of the amplifier 110 and the output REGOUT of the voltage regulator circuit 100. The driving circuit 130 is connected between the output terminal OUT1 and the output terminal REGOUT and connected to the input terminal REGIN of the voltage stabilizing circuit. The feedback circuit 120 may feedback the output voltage VOUT0 of the output terminal VOUT0 to the non-inverting input terminal of the amplifier 110. The amplifier 110 may compare an error between the output voltage vout0 and the reference voltage vref0 and output an error amplified amount. The error amplification amount can be used to control the driving circuit, and the driving circuit can adjust the output voltage vout0, so that the output of the voltage stabilizing circuit 100 is stabilized.
During use of the electronic system, the load of the voltage stabilizing circuit may change as the system application conditions change. Illustratively, the load 140 includes resistive loads RL0, RL1 and capacitive loads CL0, CL1. Assuming that RL0 and CL0 represent resistive and capacitive loads that are unchanged, RL1 and CL1 represent resistive and capacitive loads that may be changed. When the switch RSW is turned from on to off, or the switch CSW is turned under certain conditions, the load current decreases rapidly, and the output voltage vout0 of the voltage stabilizing circuit 100 increases significantly. In one implementation, the loop bandwidth of the voltage regulator circuit 100 is small, which affects the speed of the voltage regulator circuit's response to load changes. For example, the voltage stabilizing circuit 100 cannot rapidly reduce the output current to cope with the reduction of the load. This can result in the voltage stabilizing circuit failing to adjust the output current and voltage in time to cope with the load variation when the load current decreases rapidly, resulting in an increase in the output voltage vout 0. In this case, the output voltage vout0 of the voltage stabilizing circuit may rise to a maximum voltage (i.e., a limited voltage) exceeding the design allowable, which may cause damage to the gate device driven by the load, and the like, which affects the normal operation of the electronic system, and reduces the reliability of the electronic system. The above loads 140 are merely examples, and embodiments of the present application do not limit the number, type, or connection relationship of resistive or capacitive loads.
Based on the above, the embodiments of the present application provide a voltage adjustment circuit and other schemes, which can respond to the load change of the voltage stabilizing circuit in time, and limit the output voltage of the voltage stabilizing circuit, so as to improve the reliability of the circuit.
The following description refers to the accompanying drawings.
Fig. 2 is a schematic diagram of a voltage adjusting circuit according to an embodiment of the application. As shown in fig. 2, the voltage adjusting circuit 200 includes an amplifier 210 and a differential circuit 220, and the voltage VDD is a power supply voltage of the voltage adjusting circuit. The amplifier 210 includes a non-inverting input terminal (+) an inverting input terminal (-) and an output terminal OUT2. The inverting input of the amplifier 210 is coupled to an output of the voltage regulator circuit (e.g., the output REGOUT of the voltage regulator circuit 100) and is configured to receive a first output voltage of the voltage regulator circuit (e.g., the output voltage vout0 of the voltage regulator circuit 100). The non-inverting input of the amplifier 210 is coupled to the reference voltage vref1. The reference voltage vref1 can limit the output voltage of the voltage stabilizing circuit, i.e. the reference voltage vref1 is a clipping reference voltage of the voltage stabilizing circuit. The amplifier 210 is configured to output the first voltage V1 to the differential circuit 220 through the output terminal OUT2 when the output voltage (e.g., the voltage vout 0) of the voltage stabilizing circuit is greater than the reference voltage vref1, and output the second voltage V2 to the differential circuit 220 through the output terminal OUT2 when the output voltage of the voltage stabilizing circuit is less than or equal to the reference voltage vref1.
The differential circuit 220 includes an input terminal IN1, an input terminal VPG, and an output terminal OUT3, and further includes a current source. The input terminal IN1 is connected to the output terminal OUT2, the input terminal VPG is connected to the bias voltage V3, and the output terminal OUT3 is connected to the output terminal REGOUT of the voltage stabilizing circuit. The differential circuit 220 is configured to regulate the current generated by the current source when receiving the first voltage V1 (i.e., when the output voltage of the voltage stabilizing circuit is greater than the reference voltage vref 1), pull down the output voltage of the voltage stabilizing circuit, and provide the current generated by the current source to the output terminal OUT3 when receiving the second voltage V2 (i.e., when the output voltage of the voltage stabilizing circuit is less than or equal to vref 1).
The voltage adjusting circuit 200 compares the actual output voltage of the voltage stabilizing circuit with the first reference voltage by setting the amplifier 210, and when the output voltage of the voltage stabilizing circuit is larger than the first reference voltage, the differential circuit 220 rapidly responds to pull down the output voltage to make the maximum output voltage of the voltage stabilizing circuit smaller than the limiting voltage. When the output voltage of the voltage stabilizing circuit is smaller than or equal to the first reference voltage, a small current flows through the output end REGOUT of the voltage stabilizing circuit through the differential circuit, and the small current does not affect the normal loop operation of the voltage stabilizer. The output voltage of the voltage stabilizing circuit can be changed due to the change of the load, and the voltage regulating circuit provided by the application can be intermittently turned on and off according to the change condition of the load to regulate the dynamic change of the output voltage of the voltage stabilizing circuit, so that the condition that the output voltage of the voltage stabilizing circuit is increased to exceed the limiting voltage due to the rapid change of the load is prevented, the normal operation of the voltage stabilizing circuit is maintained, and the reliability of the circuit is improved.
In one implementation, a differential circuit includes a differential pair and a current mirror. Fig. 3 is a schematic diagram of another voltage adjusting circuit according to an embodiment of the application. As shown in fig. 3, the differential circuit 220 includes a differential pair 221 and a current mirror 222. The differential pair 221 includes a MOS transistor MP1 and a MOS transistor MP2. The MOS tube MP1 and the MOS tube MP2 are PMOS tubes. The gate of the MOS transistor MP1 is connected with the output end OUT2, and the drain of the MOS transistor MP1 is connected with the reference current branch of the current mirror 222. The gate of the MOS transistor MP2 is connected with the bias voltage V3, and the drain of the MOS transistor MP2 is connected with the mirror current branch of the current mirror 222. Sources of the MOS transistors MP1 and MP2 are connected to the current source 223. The ratio of the reference current branch to the mirror current branch of the current mirror 222 is 1:N, and N is greater than 1.
As shown in fig. 3, when the output voltage of the voltage stabilizing circuit is greater than the reference voltage vref1, the amplifier 210 can rapidly pull down the output voltage of the output terminal OUT 2. At this time, the MOS transistor MP1 is turned off and MP2 is turned on. In this case, the current generated by the current source 223 flows into the reference current branch of the current mirror 222 through the drain of the MOS transistor MP 1. The current mirror 222 amplifies the current, and the amplified current flows to the ground line VSS through the mirror current branch of the current mirror 222. Thus, the amplified current pulls the output voltage of the output REGOUT low. Similarly, the amplifier 210 may pull the output voltage of the output terminal OUT2 high when the output voltage of the voltage stabilizing circuit is less than or equal to the reference voltage vref 1. At this time, the MOS tube MP1 is turned off and the MOS tube MP2 is turned on. In this case, the current generated by the current source flows to the output end REGOUT of the voltage stabilizing circuit through the MOS transistor MP 2. The bias voltage V3 can control the current of MP1 to be zero (or close to zero) when the output voltage of the voltage stabilizing circuit does not exceed the output voltage limiting target, and control the current of MP1 to be rapidly increased and the current of MP2 to be rapidly decreased when the output voltage of the voltage stabilizing circuit exceeds the output voltage limiting target.
For example, as shown in fig. 3, the reference current leg of the current mirror 222 may include a MOS transistor MN1 and the mirror current leg may include a MOS transistor MN2. The ratio of the width to length ratio of the MOS tube MN1 to the MOS tube MN2 is 1:N (N is larger than 1), and the ratio of the width to length ratio of the MOS tube MP1 to the MOS tube MP2 is 1:1.
In one implementation, as shown in FIG. 3, current source 223 includes MOS transistor MP0. The MOS tube MP0 is a PMOS tube, the source electrode of the PMOS tube is connected with the power supply voltage VDD, the drain electrode of the PMOS tube is connected with the source electrodes of the MOS tubes MP1 and MP2, and the grid electrode of the PMOS tube is connected with the bias voltage V4. The bias voltage V4 may include, for example, a ground bias voltage generated by an external circuit or a bias voltage generated internally by a voltage stabilizing circuit. Further, the current source 223 may also include a capacitor. The capacitor may be disposed between the gate and the source of the MOS transistor MP0. In this way, the current source 223 can provide instantaneous large current when needed by utilizing the charge-discharge characteristic of the capacitor, so that the quiescent current consumption is reduced. In this case, MOS transistor MP0 is allowed to supply a smaller current, thereby saving circuit power consumption. In one implementation, the differential pair may also be formed by an NMOS transistor, with the addition of a one-stage PMOS to NMOS conversion.
In one implementation, the above bias voltage V3 may be a bias voltage generated internally of the voltage stabilizing circuit or a bias voltage provided by an external circuit. As shown in fig. 1 and 2, the input terminal VPG in fig. 2 may be connected to the voltage stabilizing circuit 100, for receiving the bias voltage V3 generated inside the voltage stabilizing circuit 100. For example, the driving circuit 130 of fig. 1 may include a PMOS transistor MPDR. The gate of the PMOS tube MPDR is connected to the output terminal OUT1 of the voltage stabilizing circuit, the source is connected to the input terminal REGIN, and the drain is connected to the output terminal REGOUT. The input terminal VPG may be connected to the gate of the PMOS tube MPDR, and is configured to receive a control signal of the PMOS tube MPDR.
Further, the application also provides a power supply circuit which comprises a voltage stabilizing circuit and the voltage regulating circuit in any embodiment. Fig. 4 is a schematic structural diagram of a power circuit according to an embodiment of the application. As shown in fig. 4, the power supply circuit 400 includes a voltage stabilizing circuit 410 and a voltage adjusting circuit 420. The voltage stabilizing circuit 410 is configured to generate a first output voltage. The voltage adjusting circuit 420 is connected to the voltage stabilizing circuit 410, and is used for adjusting the first output voltage when the load of the voltage stabilizing circuit 410 changes. In one implementation, voltage regulator circuit 410 may include voltage regulator circuit 100 shown in fig. 1, as described above with respect to related embodiments of voltage regulator circuit 100. The voltage regulation circuit may include the voltage regulation circuit 200 shown in fig. 2 or 3, as described above with reference to the related embodiments of the voltage regulation circuit 200.
In addition, the non-inverting input end of the amplifier in the voltage regulating circuit can be connected with the reference voltage input end of the voltage stabilizing circuit, so that the number of reference voltages is reduced, the circuit area is reduced, and the cost is reduced. For example, the non-inverting input of amplifier 210 of FIG. 3 may be connected to the non-inverting input of amplifier 110 of FIG. 1. In one implementation, the reference voltage vref0 of the voltage regulator circuit may be less than the reference voltage vref1 of the voltage regulator circuit. In this case, the clipping adjustment may be started by artificially adding an appropriate offset voltage VOS to the amplifier of the voltage regulator circuit, so that the voltage adjustment circuit starts clipping adjustment after the output voltage vout0 of the voltage regulator circuit exceeds the vref0+ VOS voltage. For example, the voltage VOS may be provided by changing the size ratio of the input differential pair transistors in the amplifier, for example, the above first amplifier may include a fourth MOS transistor and a fifth MOS transistor, where the ratio of the width to length ratio of the fourth MOS transistor to the fifth MOS transistor is 1:m, and m is greater than 1. Illustratively, in one implementation, the amplifier circuit includes a load tube to which a current mirror is connected, and the voltage VOS may be provided by varying the ratio of the currents of the current mirror reference current leg and the mirror current leg. For example, the output of the first amplifier is connected to a further current mirror, the current mirror having a reference current branch and a mirror current branch with a current ratio of 1:K, K being greater than 1.
For convenience of distinction, the above amplifier 210 may be referred to as a first amplifier, a non-inverting input terminal of the amplifier 210 may be referred to as a first input terminal, an inverting input terminal of the amplifier 210 may be referred to as a second input terminal, and an output terminal OUT2 of the amplifier 210 may be referred to as a first output terminal. The output of the voltage stabilizing circuit may be referred to as a second output. The input terminal IN1 of the differential circuit may be referred to as a third input terminal, the input terminal VPG may be referred to as a fourth input terminal, and the output terminal OUT3 may be referred to as a third output terminal.
The amplifier 110 may be referred to as a second amplifier, a non-inverting input terminal of the amplifier 110 may be referred to as a fifth input terminal, an inverting input terminal of the amplifier 110 may be referred to as a sixth input terminal, and an output terminal OUT1 of the amplifier 110 may be referred to as a fourth output terminal. The reference voltage vref1 may be referred to as a first reference voltage and the reference voltage vref0 may be referred to as a second reference voltage.
MOS tube MP1 can be called a first MOS tube, MOS tube MP2 can be called a second MOS tube, and MOS tube P0 can be called a third MOS tube.
Based on the same or similar technical ideas, the embodiment of the application also provides an integrated circuit, including any one of the power circuits in the above embodiments. Further, the embodiment of the application also provides electronic equipment, which comprises the integrated circuit.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and the parts of a certain embodiment that are not described or depicted in detail may be referred to in the related descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.
Claims (9)
1. A voltage adjusting circuit for adjusting a first output voltage of a voltage stabilizing circuit immediately when the first output voltage exceeds a clip reference voltage to reduce a response delay, the voltage adjusting circuit including a first amplifier and a differential circuit,
The first amplifier comprises a first input end, a second input end and a first output end;
the first input end is connected with a second output end of the voltage stabilizing circuit and is configured to receive a first output voltage of the voltage stabilizing circuit;
the first amplifier is configured to output a first voltage to the differential circuit through the first output terminal when the first output voltage is greater than the first reference voltage; outputting a second voltage to the differential circuit through the first output terminal when the first output voltage is less than or equal to the first reference voltage;
The differential circuit comprises a third input end, a fourth input end and a third output end;
The third input end is connected with the first output end, the fourth input end is connected with bias voltage, and the third output end is connected with the second output end;
The differential circuit further includes a current source configured to adjust a current generated by the current source when receiving the first voltage, pulling down the first output voltage; providing a current generated by the current source to the second output terminal when the second voltage is received;
wherein the differential circuit comprises a differential pair and a current mirror,
The differential pair comprises a first MOS tube and a second MOS tube, the first MOS tube and the second MOS tube are PMOS tubes,
The grid electrode of the first MOS tube is connected with the first output end, and the drain electrode of the first MOS tube is connected with the reference current branch of the current mirror;
the grid electrode of the second MOS tube is connected with bias voltage, and the drain electrode of the second MOS tube is connected with the mirror image current branch circuit of the current mirror;
the sources of the first MOS tube and the second MOS tube are connected with the current source, the current ratio of the reference current branch and the mirror current branch is 1:N, and N is larger than 1.
2. The voltage regulation circuit of claim 1, wherein the current source comprises a third MOS transistor and a capacitor, the capacitor being disposed between a gate and a source of the third MOS transistor.
3. The voltage regulation circuit of claim 1, wherein the fourth input is coupled to the voltage regulator circuit, the bias voltage being generated by the voltage regulator circuit.
4. The voltage regulation circuit of claim 1, wherein the voltage regulator circuit includes a fifth input configured to be coupled to a second reference voltage, the fifth input being coupled to the second input.
5. The voltage regulation circuit of claim 4 wherein the first amplifier comprises a fourth MOS transistor and a fifth MOS transistor, the ratio of the width to length of the fourth MOS transistor to the fifth MOS transistor being 1:M, and M being greater than 1.
6. A power supply circuit, comprising:
the voltage stabilizing circuit is used for generating a first output voltage;
the voltage regulation circuit of any one of claims 1-5, coupled to the voltage regulator circuit, for regulating the first output voltage when a load of the voltage regulator circuit changes.
7. The power supply circuit of claim 6, wherein the voltage stabilizing circuit comprises a second amplifier, a feedback circuit, and a drive circuit,
The second amplifier comprises a fifth input terminal, a sixth input terminal and a fourth output terminal,
The fifth input end is connected with a second reference voltage, the feedback circuit is connected between the sixth input end and the output end of the voltage stabilizing circuit, and the driving circuit is connected between the fourth output end and the output end of the voltage stabilizing circuit.
8. An integrated circuit comprising the power supply circuit of claim 7.
9. An electronic device comprising the integrated circuit of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411864044.9A CN119311067B (en) | 2024-12-18 | 2024-12-18 | A voltage regulating circuit, a power supply circuit, an integrated circuit and an electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202411864044.9A CN119311067B (en) | 2024-12-18 | 2024-12-18 | A voltage regulating circuit, a power supply circuit, an integrated circuit and an electronic device |
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| CN119311067A CN119311067A (en) | 2025-01-14 |
| CN119311067B true CN119311067B (en) | 2025-03-21 |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104460801A (en) * | 2014-11-25 | 2015-03-25 | 无锡中星微电子有限公司 | Voltage regulator |
| CN116610177A (en) * | 2023-04-25 | 2023-08-18 | 合肥奕斯伟计算技术有限公司 | Low-dropout voltage stabilizing circuit, driving method and electronic equipment |
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| CN119311067A (en) | 2025-01-14 |
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