CN119296627A

CN119296627A - SRAM protection circuit, method and chip

Info

Publication number: CN119296627A
Application number: CN202411318117.4A
Authority: CN
Inventors: 张世强; 张腾超; 张祥
Original assignee: Ziguang Tongxin Microelectronics Co Ltd
Current assignee: Ziguang Tongxin Microelectronics Co Ltd
Priority date: 2024-09-20
Filing date: 2024-09-20
Publication date: 2025-01-10

Abstract

The present invention discloses an SRAM protection circuit, method and chip. The SRAM protection circuit includes: an MBIST control circuit, a DFLASH, an ECC generation circuit, a fault address recording circuit, a MUX gating circuit and an OR gate, and also includes: an ECC detection circuit, an MBIST result circuit, a Remap circuit and a fault address comparison circuit; the SRAM storage area includes a first data storage area and a second data storage area. The embodiment of the present invention can comprehensively and accurately detect whether the storage area in the SRAM is invalid based on the ECC detection circuit, the MBIST control circuit, the fault address comparison circuit and the Remap circuit, process the invalid storage area, and replace the permanently invalid storage area for storing data with a blank storage area.

Description

SRAM protection circuit, method and chip

Technical Field

The present invention relates to the field of computer technologies, and in particular, to an SRAM protection circuit, method, and chip.

Background

A Static Random-Access Memory (SRAM) is typically provided inside the chip. The SRAM includes a plurality of memory regions. In the running process of the chip, other modules in the chip can store data into a storage area in the SRAM and can also read the data stored in the storage area in the SRAM. An abnormal situation in the operation of the chip may cause a failure of a memory area in the SRAM. A storage area failure may mean that after data is stored in a storage area, the data stored in the storage area cannot be read normally. In order to ensure the normal operation of the chip, the SRAM arranged in the chip needs to be protected, whether a storage area in the SRAM fails or not is detected in the operation process of the chip, and after the failure of the storage area in the SRAM is detected, the failed storage area is processed.

In the related art, a common SRAM protection scheme is to detect whether there are error data bits in data stored in a storage area in an SRAM through an error correction code (Error Correcting Code, ECC) algorithm, determine that the storage area fails after detecting that there are error data bits in the data stored in the storage area, and correct the error data bits to recover correct data. If the number of the error data bits in the data does not exceed the upper limit of the number corresponding to the ECC algorithm, all the error data bits in the data can be corrected, and correct data can be recovered. If the number of the error data bits in the data exceeds the upper limit of the number corresponding to the ECC algorithm, all the error data bits in the data cannot be corrected, the correct data cannot be recovered, and the invalid storage area cannot be processed. The SRAM protection scheme in the related art can only detect whether the storage area in the SRAM is invalid based on an ECC algorithm, process the invalid storage area, and cannot comprehensively and accurately detect whether the storage area in the SRAM is invalid and process the invalid storage area.

Disclosure of Invention

The invention provides an SRAM protection circuit, an SRAM protection method and an SRAM protection chip, which are used for solving the problem that whether a storage area in an SRAM fails or not cannot be comprehensively and accurately detected by an SRAM protection scheme in the related art and processing the failed storage area.

According to one aspect of the invention, an SRAM protection circuit is provided, which comprises an MBIST control circuit, a DFLASH, an ECC generation circuit, a fault address recording circuit, a MUX strobe circuit and an OR gate, and further comprises an ECC detection circuit, an MBIST result circuit, a Remap circuit and a fault address comparison circuit;

the SRAM storage area comprises a first data storage area and a second data storage area;

The ECC detection circuit detects a failure mode of a first data storage area of the SRAM storage area, stores the detected failure address into the DFLASH, marks the failure address as a low failure address, and triggers the MBIST control circuit to detect the failure condition of the SRAM, when detecting that the failure address has the failure condition of the SRAM, the MBIST control circuit defines the failure address as an MBIST failure address and stores the failure address into the MBIST result circuit;

The Remap circuit reads the DFLASH after reset and at each power-up stage and remaps the failed address marked as a high failed address in the DFLASH to the second data storage area of the SRAM storage area, repairing the permanent failed address.

After receiving a data reading request corresponding to a first data storage area of the SRAM storage area, the ECC detection circuit detects whether a storage area mapped with an address to be read of the data reading request is invalid according to an error correction code stored in the first data storage area, if yes, defines the address to be read as an invalid fault address, stores the invalid fault address into the DFLASH and marks the invalid fault address as a low fault address, and triggers the MBIST control circuit to detect the invalid fault address.

And after receiving detection trigger information corresponding to the failure fault address, the MBIST control circuit writes test data into a storage area mapped with the failure fault address through the MUX gating circuit and the Remap circuit, detects whether the failure fault address has an SRAM failure condition according to the data stored in the storage area mapped with the failure fault address, if so, defines the failure fault address as an MBIST failure fault address, and stores the MBIST failure fault address into the MBIST result circuit.

The failure address comparison circuit reads the MBIST failure address stored in the MBIST result circuit and the failure address stored in the DFLASH, compares whether the MBIST failure address and the failure address are the same, if yes, determines that the failure address stored in the DFLASH is a permanent failure address, and marks the failure address stored in the DFLASH as a high failure address.

According to another aspect of the present invention, there is provided an SRAM protection method, applied to an SRAM protection circuit provided by the present invention, including:

the ECC detection circuit detects a failure mode of a first data storage area of the SRAM storage area, stores the detected failure fault address into DFLASH, marks the detected failure fault address as a low fault address, and triggers the MBIST control circuit to detect;

when detecting that the failure fault address has SRAM failure condition, the MBIST control circuit defines the failure fault address as an MBIST failure fault address and stores the MBIST failure fault address into an MBIST result circuit;

The failure address comparison circuit compares the failure address of the MBIST stored in the MBIST result circuit with the failure address of the DFLASH, if the failure address and the failure address are the same, the failure address stored in the DFLASH is determined to be a permanent failure address, and the failure address is marked as a high failure address;

Remap the circuit reads the DFLASH after reset and at each power-up stage, and remaps the failed address marked as a high failed address in the DFLASH to the second data storage area of the SRAM storage area, repairing the permanent failed address.

The ECC detection circuit detects a failure mode of a first data storage area of the SRAM storage area, stores the detected failure address into DFLASH and marks the failure address as a low failure address, and triggers the MBIST control circuit to detect, and the ECC detection circuit comprises:

After receiving a data reading request corresponding to a first data storage area of an SRAM storage area, an ECC detection circuit detects whether a storage area mapped with an address to be read of the data reading request is invalid according to an error correction code stored in the first data storage area, if so, the address to be read is defined as an invalid fault address, the invalid fault address is stored in DFLASH and marked as a low fault address, and an MBIST control circuit is triggered to detect the invalid fault address.

When detecting that the failure fault address has an SRAM failure condition, the MBIST control circuit defines the failure fault address as an MBIST failure fault address and stores the MBIST failure fault address into an MBIST result circuit, and the MBIST control circuit comprises:

And after receiving detection trigger information corresponding to the failure fault address, the MBIST control circuit writes test data into a storage area mapped with the failure fault address through a MUX gating circuit and a Remap circuit, detects whether the SRAM failure condition exists in the failure fault address according to the data stored in the storage area mapped with the failure fault address, if so, defines the failure fault address as an MBIST failure fault address, and stores the MBIST failure fault address into an MBIST result circuit.

The failure address comparison circuit compares the MBIST failure address stored in the MBIST result circuit with the failure address stored in the DFLASH, if the two are the same, determines the failure address stored in the DFLASH to be a permanent failure address, marks the failure address to be a high failure address, and includes:

And the failure address comparison circuit reads the failure address of the MBIST stored in the MBIST result circuit and the failure address stored in the DFLASH, compares whether the failure address of the MBIST and the failure address are identical, if so, determines that the failure address stored in the DFLASH is a permanent failure address, and marks the failure address stored in the DFLASH as a high failure address.

And the MBIST control circuit detects whether the first data storage area of the SRAM storage area has the SRAM failure condition according to a preset period, and stores the storage address with the SRAM failure condition into the DFLASH and marks the storage address as a high failure address.

According to another aspect of the present invention, a chip is provided, including an SRAM protection circuit according to any one of the embodiments of the present invention.

In the technical scheme of the embodiment of the invention, an ECC detection circuit detects a failure mode of a first data storage area of an SRAM storage area, a detected failure address is stored in DFLASH and marked as a low failure address, and an MBIST control circuit is triggered to detect, when the failure address is detected to have an SRAM failure condition, the MBIST control circuit defines the failure address as an MBIST failure address and stores the failure address into an MBIST result circuit, a failure address comparison circuit compares the MBIST failure address stored in the MBIST result circuit with the failure address stored in DFLASH, if the failure address and the failure address are the same, the failure address stored in DFLASH is determined to be a permanent failure address, the failure address is marked as a high failure address, the Remap circuit reads DFLASH after reset and at each power-up stage, and the failure address marked as the high failure address is remapped to a second data storage area of the SRAM storage area, the permanent failure address is repaired, whether a storage area in a protection scheme in a related technology cannot be fully and accurately detected is solved, the failure detection of the storage area in the related technology is performed, and the failure detection circuit can be used for comprehensively processing the failure storage area of the SRAM storage area based on the failure address, the error detection circuit and the error protection circuit can be used for comprehensively processing the failure area by the SRAM storage area, and the storage area of the SRAM storage area is replaced by the error-free storage area.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an SRAM protection circuit according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of an SRAM according to an embodiment of the present invention.

Fig. 3 is a flowchart of an SRAM protection method according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a chip according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "object," "first," "second," and the like in the description and the claims of the present invention and the above drawings are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural diagram of an SRAM protection circuit according to an embodiment of the present invention. The embodiment can be suitable for protecting the SRAM arranged in the chip, detecting whether the storage area in the SRAM fails in the running process of the chip, and processing the failed storage area after detecting that the storage area in the SRAM fails. As shown in fig. 1, the SRAM protection circuit may specifically include MBIST control circuits 101, DFLASH, ECC generation circuit 103, failure address recording circuit 104, MUX strobe circuit 105, or gate 106, ECC detection circuit 107, MBIST result circuits 108, remap circuit 109, and failure address comparison circuit 110, the structure and function of which are described below.

Wherein the SRAM memory region comprises a first data memory region and a second data memory region.

ECC detection circuit 107 detects the failure mode of the first data storage area of the SRAM storage area, stores the detected failure address into DFLASH and marks the failure address as a low failure address, and triggers MBIST control circuit 101 to detect, when detecting that the failure address has an SRAM failure condition, MBIST control circuit 101 defines the failure address as an MBIST failure address and stores the MBIST failure address into MBIST result circuit 108, failure address comparison circuit 110 compares the MBIST failure address stored in MBIST result circuit 108 with the failure address stored in DFLASH, if the failure address is the same, determines DFLASH that the failure address stored in DFLASH is a permanent failure address, and marks the failure address as a high failure address.

Remap the circuit 109 reads DFLASH after reset and at each power-up phase and remaps the failing address marked as a high failing address in DFLASH to the second data storage area of the SRAM storage area, repairing the permanent failing address.

Optionally, the SRAM protection circuit is disposed in the chip. The chip may be a vehicle gauge chip for vehicle control. An SRAM is arranged in the chip. SRAM memory regions are all memory regions in an SRAM. The SRAM memory region includes a first data memory region and a second data memory region.

Optionally, the first data storage area is a storage area in SRAM for storing data. The SRAM memory region includes a plurality of first data memory regions. Each first data storage area is provided with a mapped storage address. The storage address mapped with the first data storage area may be a number set in advance for uniquely identifying the first data storage area. The memory addresses mapped with the different first data storage areas are not identical.

Optionally, the second data storage area is a blank storage area in the SRAM for replacing the permanently failed first data storage area. The SRAM memory region includes a plurality of second data memory regions. The permanently disabled first data storage area may refer to a first data storage area where the stored data cannot be read normally and the stored data cannot be restored.

Optionally, the ECC generation circuit 103 is connected to a first input terminal of the MUX gating circuit 105, the MBIST control circuit 101 is connected to a second input terminal of the MUX gating circuit 105, an output terminal of the MUX gating circuit 105 is connected to the Remap circuit 109, a first input terminal of the or gate 106 is connected to a periodic enable signal output port, a second input terminal of the or gate 106 is connected to the ECC detection circuit 107, an output terminal of the or gate 106 is connected to a control terminal of the MUX gating circuit 105, the Remap circuit 109 is connected to an SRAM in the chip, the ECC detection circuit 107 and DFLASH, the fault address recording circuit 104, the fault address comparison circuit 110, and the MBIST control circuit 101 are connected to the MBIST result circuit 108, the MBIST result circuit 108 is connected to the fault address comparison circuit 110, and the DFLASH is connected to the fault address comparison circuits 110, remap circuit 109.

Optionally DFLASH is DFLASH to store the failing address, and a flag bit for the failing address. The flag bit is 0 or 1. The flag bit of the storage address may be identification information for characterizing whether the storage area mapped with the storage address is a permanently failed storage area. A permanently failed storage area may refer to a storage area where the stored data cannot be read normally and the stored data cannot be restored. The flag bit of the memory address is 0, indicating that the memory region mapped with the memory address is not a permanently dead memory region. The flag bit of the memory address is 1, indicating that the memory region mapped with the memory address is a permanently dead memory region. The low failure address may be a failed failure address indicating a flag bit of 0. The high failure address may be a failed failure address indicating a flag bit of 1.

Alternatively, MBIST control circuit 101 may be a hardware circuit for detecting whether the first data storage area is failed based on the test data. The ECC generation circuit 103 may be a hardware circuit for generating an error correction code corresponding to data. The failure address recording circuit 104 may be a hardware circuit for storing a storage address mapped to a first data storage area where the stored data cannot be read normally. The MUX gating circuit 105 may be a one-out-of-two selector. The ECC detection circuit 107 may be a hardware circuit for detecting whether the first data storage area is defective or not based on the error correction code, and processing the first data storage area which can correct the defective. MBIST result circuit 108 may be a hardware circuit for storing MBIST failure fault addresses. Remap circuit 109 may be a hardware circuit for managing the first data storage region and the second data storage region, handling permanently failed first data storage region. Fail address comparison circuitry 110 may be a hardware circuit for determining whether the fail address stored in DFLASH 102 is a permanent fail address by comparing the MBIST fail address stored in MBIST result circuitry 108 with the fail address stored in DFLASH 102, and marking the permanent fail address as a high fail address.

Alternatively, the ECC generation circuit 103 may generate an error correction code corresponding to the data to be written through an ECC algorithm after receiving the data to be written and the storage address of the data to be written sent by other modules in the chip, and then send the data to be written, the storage address of the data to be written, and the error correction code corresponding to the data to be written to the MUX gating circuit 105.

Alternatively, other modules in the chip may be software modules or hardware modules provided in the chip other than the SRAM, MBIST control circuits 101, DFLASH, ECC generation circuit 103, fail address recording circuit 104, MUX strobe circuit 105, or gate 106, ECC detection circuit 107, MBIST result circuit 108, remap circuit 109, and fail address comparison circuit 110. The data to be written is the data that needs to be written to the first data storage area in the SRAM. The storage address of the data to be written is a storage address mapped with the first data storage area to which the data to be written needs to be written.

Alternatively, when the periodic enable signal output port and the ECC detection circuit 107 stop outputting the high level to the first input terminal of the or gate 106, the output terminal of the or gate 106 outputs the low level to the port of the control terminal of the MUX gating circuit 105. When the periodic enable signal output port or the ECC detection circuit 107 outputs a high level to the first input terminal of the or gate 106, the output terminal of the or gate 106 outputs a high level to the port of the control terminal of the MUX gating circuit 105.

Optionally, when the output terminal of the or gate 106 outputs a low level to the control terminal of the MUX gating circuit 105, the MUX gating circuit 105 sends the data to be written sent by the ECC generation circuit 103, the storage address of the data to be written, and the error correction code corresponding to the data to be written to the Remap circuit 109. When the output terminal of the or gate 106 outputs a high level to the control terminal of the MUX gating circuit 105, the MUX gating circuit 105 sends the test data sent by the MBIST control circuit 101 and the memory address of the test data to the Remap circuit 109.

Optionally, the Remap circuit 109 writes the data to be written and the error correction code corresponding to the data to be written into the first data storage area mapped with the storage address of the data to be written after receiving the data to be written, the storage address of the data to be written, and the error correction code corresponding to the data to be written.

Optionally, remap circuit 109, after receiving the test data, the memory address of the test data, writes the test data to the first data storage area mapped with the memory address of the test data.

Optionally, after receiving a data read request corresponding to a first data storage area of an SRAM storage area, the ECC detection circuit 107 detects whether a storage area mapped with an address to be read of the data read request fails according to an error correction code stored in the first data storage area, if yes, defines the address to be read as a failure address, stores the failure address into DFLASH and marks the failure address as a low failure address, and triggers the MBIST control circuit 101 to detect the failure address.

Alternatively, the data read request corresponding to the first data storage area of the SRAM storage area may be a request sent by the target module for requesting to read the data stored in the specified first data storage area. The target module may be other modules in any one of the chips. The designated first data storage area may be any one of the first data storage areas. The data read request carries the address to be read. The address to be read is a storage address of the designated first data storage area that the data read request requests to read. The storage area mapped with the address to be read of the data read request is a specified first data storage area that the data read request requests to read.

Optionally, the ECC detection circuit 107 detects whether the storage area mapped with the address to be read of the data read request is invalid according to the error correction code stored in the first data storage area, and comprises the steps that the ECC detection circuit 107 determines the storage area mapped with the address to be read of the data read request according to the address to be read of the data read request, generates the error correction code corresponding to the data stored in the storage area mapped with the address to be read of the data read request through an ECC algorithm, compares whether the generated error correction code is identical with the error correction code stored in the storage area mapped with the address to be read of the data read request, and if the generated error correction code is identical with the error correction code stored in the storage area mapped with the address to be read of the data read request, the ECC detection circuit 107 determines that the storage area mapped with the address to be read of the data read request is not invalid.

Optionally, if the generated error correction code is different from the error correction code stored in the memory area mapped with the address to be read of the data read request, the ECC detection circuit 107 decrypts the error correction code stored in the memory area mapped with the address to be read of the data read request through an ECC algorithm, to obtain the recovered data stored in the memory area mapped with the address to be read of the data read request. Then the ECC detection circuit 107 generates an error correction code corresponding to the restored data stored in the memory area mapped with the address to be read of the data read request by the ECC algorithm, and compares whether the restored error correction code corresponding to the data stored in the memory area mapped with the address to be read of the data read request and the error correction code stored in the memory area mapped with the address to be read of the data read request are identical. If so, it indicates that the recovered data stored in the storage area mapped with the to-be-read address of the data read request is correct data that should be stored in the storage area mapped with the to-be-read address of the data read request, after the ECC detection circuit 107 fails to read the data stored in the storage area mapped with the to-be-read address of the data read request normally, the correct data that should be stored in the storage area mapped with the to-be-read address of the data read request is recovered, the data stored in the storage area mapped with the to-be-read address of the data read request can be corrected, and the invalid storage area is then sent to the target module, and the ECC detection circuit 107 replaces the data stored in the storage area mapped with the to-be-read address of the data read request with the recovered data stored in the storage area mapped with the to-be-read address of the data read request, thereby correcting the invalid storage area, and then sending the recovered data stored in the storage area mapped with the to-be-read address of the data read request to the target module, and recording the fault address of the data read request to be recorded in the fault circuit 104. If not, indicating that the ECC detection circuit 107 cannot normally read the data stored in the storage area mapped with the address to be read of the data read request and cannot recover the data stored in the storage area mapped with the address to be read of the data read request, the ECC detection circuit 107 determines that the storage area mapped with the address to be read of the data read request is invalid.

Alternatively, if the ECC detection circuit 107 determines that the storage area mapped with the address to be read of the data read request is not invalid, the data stored in the storage area mapped with the address to be read of the data read request is read, and then the data stored in the storage area mapped with the address to be read of the data read request is sent to the target module.

Alternatively, if the ECC detection circuit 107 determines that the storage area mapped with the address to be read of the data read request fails, the address to be read is defined as a failed address, the failed address is stored in DFLASH and marked as a low-failure address, and the MBIST control circuit 101 is triggered to detect the failed address. The fail-over address may refer to a memory address mapped with a first data storage area where data cannot be read normally and data cannot be restored, which is detected by the ECC detection circuit 107.

Optionally, storing the failed address in DFLASH and marking it as a low-failure address includes determining that the marking bit of the failed address is 0 and storing the failed address, the marking bit of the failed address in DFLASH 102.

Optionally, triggering MBIST control circuit 101 to detect the failed address includes sending detection trigger information corresponding to the failed address to MBIST control circuit 101, outputting a high level to a second input terminal of or gate 106, so that an output terminal of or gate 106 outputs a high level to a control terminal of MUX gating circuit 105.

Optionally, after defining the address to be read as a failed address, the ECC detection circuit 107 feeds back a read failure prompt message to the target module, and stores the failed address into the failed address recording circuit 104. The reading failure prompt information may be information which is preset and used for representing that the data stored in the storage area cannot be read. The ECC detection circuit 107 sends the read failure notice information to the target module, thereby feeding back the read failure notice information to the target module. The target module can determine that the data stored in the storage area mapped with the address to be read of the data read request cannot be read according to the read failure prompt information.

Alternatively, the detection trigger information corresponding to the failure address may be information for triggering MBIST control circuit 101 to detect whether the failure address has an SRAM failure condition according to test data. And the detection trigger information corresponding to the failure fault address comprises the failure fault address.

Optionally, the ECC detection circuit 107 stops outputting the high level to the second input terminal of the or gate 106 after the duration of outputting the high level to the second input terminal of the or gate 106 reaches the preset duration. The preset time period may be a time period set in advance. In general, MBIST control circuit 101 will complete the process of detecting whether the SRAM failure condition exists at the failure address according to the test data within a preset period of time.

Optionally, after receiving the detection trigger information corresponding to the failure address, MBIST control circuit 101 writes test data into a storage area mapped with the failure address through MUX gating circuits 105 and Remap circuit 109, detects whether the failure address has an SRAM failure condition according to the data stored in the storage area mapped with the failure address, if yes, defines the failure address as an MBIST failure address, and stores the failure address into MBIST result circuit 108.

Optionally, writing test data to the storage area mapped with the failed address through MUX gating circuits 105 and Remap circuit 109 includes MBIST control circuit 101 determining the failed address as a storage address of the test data after receiving detection trigger information corresponding to the failed address, and transmitting the test data and the storage address of the test data to MUX gating circuit 105. The test data may be preset data. The memory address of the test data is a memory address mapped with the first data storage area to which the test data needs to be written. The output of or gate 106 outputs a high level to the control of MUX gating circuit 105, and MUX gating circuit 105 sends test data sent by MBIST control circuit 101, and the memory address of the test data to Remap circuit 109.Remap upon receiving the test data, the memory address of the test data, the circuit 109 writes the test data to a first data storage area mapped with the memory address of the test data. When the test data is written into the first data storage area mapped with the storage address of the test data, the data stored in the first data storage area is covered.

Optionally, MBIST control circuit 101 waits for a target period of time after sending test data and a storage address of the test data to MUX gating circuit 105, so as to determine that the test data is written into a storage area mapped with the failed address, and then detects whether the failed address has an SRAM failure condition according to data stored in the storage area mapped with the failed address. The target time period may be a preset time period. Typically, test data will be written to the first data storage area mapped with the memory address of test data for a target period of time after MBIST control circuit 101 sends the test data, the memory address of the test data, to MUX strobe circuit 105.

Optionally, detecting whether the fail address has an SRAM fail condition according to the data stored in the fail address mapped storage area includes determining a first data storage area mapped to the fail address according to the fail address, reading the data stored in the first data storage area mapped to the fail address, determining whether the data stored in the first data storage area mapped to the fail address is identical to correct test data, if so, indicating that MBIST control circuit 101 can normally read the data stored in the first data storage area mapped to the fail address, if not, determining that the fail address does not have an SRAM fail condition, and if not, indicating that MBIST control circuit 101 cannot normally read the data stored in the first data storage area mapped to the fail address, and if not, determining that the fail address has a fail condition.

Alternatively, if MBIST control circuit 101 determines that the failure address has an SRAM failure condition, then the failure address is defined as an MBIST failure address and stored in MBIST result circuit 108. MBIST failure address may refer to a memory address mapped with the first data memory area where data cannot be read normally detected by MBIST control circuit 101.

Optionally, the failure address comparing circuit 110 reads the MBIST failure address stored in the MBIST result circuit 108 and the failure address stored in DFLASH, compares whether the MBIST failure address and the failure address are the same, if yes, determines that the failure address stored in DFLASH 102 is a permanent failure address, and marks the failure address stored in DFLASH 102 as a high failure address.

Alternatively, failure address comparison circuit 110 may read the MBIST failure address stored in MBIST result circuit 108 and the failure address stored in DFLASH after MBIST control circuit 101 stores the MBIST failure address in MBIST result circuit 108, and compare whether the MBIST failure address and the failure address are the same. If so, the fail address comparison circuit 110 determines DFLASH that the fail address stored in 102 is a permanent fail address, marks DFLASH that the fail address stored in 102 is a high fail address. The permanent failure address may refer to a memory address mapped with the permanently failed first data storage area. Marking the failed address stored in DFLASH to be a high-failure address includes setting a flag bit of the failed address stored in DFLASH to be 1. If not, the failure address comparing circuit 110 determines that the present comparison process is ended.

Alternatively, remap circuitry 109 may read DFLASH after reset and at each power-up stage and remap the failed address marked as a high failed address in DFLASH to the second data storage area of the SRAM storage area, repairing the permanent failed address.

Optionally, remap the circuit 109 remaps the fail address marked as a high fail address in DFLASH to the second data storage area of the SRAM storage area, repairing the permanently fail address includes determining a new first data storage area mapped with the fail address in each second data storage area by Remap the circuit 109 for the fail address marked as a high fail address in DFLASH, establishing a mapping relationship between the fail address and the new first data storage area, processing the permanently fail first data storage area mapped with the fail address, replacing the permanently fail first data storage area with the second data storage area, and repairing the permanently fail address. Determining a new first data storage area mapped with the failing address in each second data storage area includes randomly selecting one of the unused second data storage areas as the new first data storage area mapped with the failing address. The unused second data storage areas are those that have not been mapped to a storage address and have not been used to replace the permanently failed first data storage area.

Optionally, if MBIST control circuit 101 determines that the failed address does not have an SRAM failure condition, it determines that the first data storage area mapped with the failed address is a transient failed first data storage area, and resets the first data storage area mapped with the failed address. The transient failed first data storage area may be a failed first data storage area that has recovered to normal. After storing new data to the transient failed first data storage area, the data stored in the transient failed first data storage area may be read normally. Resetting the first data storage area mapped with the failed address includes clearing all data stored in the first data storage area mapped with the failed address.

Optionally, the periodic enable signal output port outputs a high level to the first input terminal of the or gate 106 according to a preset period, so that the output terminal of the or gate 106 outputs a high level to the control terminal of the MUX gating circuit 105.

Optionally, MBIST control circuit 101 detects whether the first data storage area of the SRAM storage area has an SRAM failure condition according to a preset period, and stores a storage address having the SRAM failure condition into DFLASH and marks the storage address as a high failure address.

Alternatively, the periodic enable signal output port may be a port for outputting a high level to the first input terminal of the or gate 106 at a preset period, so that the output terminal of the or gate 106 outputs a high level to the control terminal of the MUX gate 105. The outputting of the high level to the first input terminal of the or gate 106 according to the preset period may be starting to output the high level to the first input terminal of the or gate 106 at preset time intervals, and stopping outputting the high level to the first input terminal of the or gate 106 after the duration of outputting the high level to the first input terminal of the or gate 106 reaches the specified duration. The preset time interval may be a preset time interval. The specified duration may be a duration set in advance. The preset time interval is greater than the specified duration. In general, MBIST control circuit 101 can complete the operation of detecting whether the SRAM failure condition exists in the first data storage region of the SRAM storage region within a specified period of time. The MBIST control circuit 101 detecting whether the first data storage area of the SRAM storage area has the SRAM failure condition according to the preset period may refer to that the MBIST control circuit 101 performs an operation of detecting whether the first data storage area of the SRAM storage area has the SRAM failure condition once every a preset time interval.

Optionally, detecting whether the first data storage area of the SRAM storage area has an SRAM failure condition includes, for each first data storage area, performing a backup of data stored in the first data storage area, determining a storage address mapped with the first data storage area as a storage address of test data, sending the test data and the storage address of the test data to the MUX gating circuit 105, and detecting whether the first data storage area has the SRAM failure condition according to the test data and the data stored in the first data storage area after determining that the test data is written into the first data storage area.

Optionally, detecting whether the first data storage area has an SRAM failure condition according to the test data and the data stored in the first data storage area includes reading the data stored in the first data storage area, determining whether the data stored in the first data storage area is the same as the correct test data, if so, determining that the first data storage area has no SRAM failure condition if the first data storage area has no failure, if not, determining that the first data storage area has no SRAM failure condition if the first data storage area has failure, and if so, determining that the first data storage area has SRAM failure condition if the first data storage area has failure.

Alternatively, for each first data storage area, if MBIST control circuit 101 determines that the first data storage area does not have an SRAM failure condition, then the data stored in the first data storage area is replaced with the backed-up data, so that the data stored in the first data storage area is restored to the point before the detection process starts.

Optionally, for each first data storage area, if MBIST control circuit 101 determines that the first data storage area has an SRAM failure condition, it determines that a flag bit of a storage address mapped with the first data storage area is 1, and stores the storage address mapped with the first data storage area and a flag bit of the storage address mapped with the first data storage area into DFLASH. Thus, remap circuitry 109 may read DFLASH after reset and at each power-up stage and remap the memory address mapped with the first data storage region into the second data storage region of the SRAM storage region.

Optionally, in a specific example, fig. 2 is a schematic structural diagram of an SRAM according to an embodiment of the present invention. The SRAM includes a plurality of first data storage areas and a plurality of second data storage areas. There is one permanently dead first data storage area in each first data storage area. Remap circuits are used to manage the first and second data storage areas in the SRAM and to handle the permanently disabled first data storage area.

Fig. 3 is a flowchart of an SRAM protection method according to an embodiment of the present invention. The method can be performed by the SRAM protection circuit provided by the embodiment of the invention. As shown in fig. 3, the method in this embodiment specifically includes:

Step 201, an ECC detection circuit detects a failure mode of a first data storage area of the SRAM storage area, stores the detected failure address into DFLASH and marks the detected failure address as a low failure address, and triggers an MBIST control circuit to detect.

Optionally, the ECC detection circuit detects a failure mode of a first data storage area of the SRAM storage area, stores the detected failure address into DFLASH and marks the failure address as a low failure address, and triggers the MBIST control circuit to detect, including that the ECC detection circuit detects whether a storage area mapped with a to-be-read address of the data read request fails according to an error correction code stored in the first data storage area after receiving a data read request corresponding to the first data storage area of the SRAM storage area, if so, the to-be-read address is defined as the failure address, the failure address is stored into DFLASH and marks the failure address as the low failure address, and triggers the MBIST control circuit to detect the failure address.

And 202, when the failure fault address is detected to have the SRAM failure condition, the MBIST control circuit defines the failure fault address as an MBIST failure fault address and stores the MBIST failure fault address into an MBIST result circuit.

Optionally, when detecting that the failure fault address has an SRAM failure condition, the MBIST control circuit defines the failure fault address as an MBIST failure fault address and stores the MBIST failure fault address into an MBIST result circuit, and the MBIST control circuit writes test data into a storage area mapped with the failure fault address through a MUX gating circuit and a Remap circuit after receiving detection trigger information corresponding to the failure fault address, detects whether the failure fault address has an SRAM failure condition according to data stored in the storage area mapped with the failure fault address, if so, defines the failure fault address as an MBIST failure fault address and stores the MBIST failure fault address into the MBIST result circuit.

And 203, comparing the failure address stored in the MBIST result circuit with the failure address stored in DFLASH by a failure address comparison circuit, if the failure address and the failure address are the same, determining the failure address stored in DFLASH as a permanent failure address, and marking the failure address as a high failure address.

Optionally, the failure address comparison circuit compares the MBIST failure address stored in the MBIST result circuit with the failure address stored in the DFLASH, if the two are the same, determines that the failure address stored in the DFLASH is a permanent failure address, marks the failure address as a high failure address, and includes that the failure address comparison circuit reads the MBIST failure address stored in the MBIST result circuit and the failure address stored in the DFLASH, compares whether the MBIST failure address is the same as the failure address, if yes, determines that the failure address stored in the DFLASH is a permanent failure address, marks the failure address stored in the DFLASH as a high failure address.

The circuit in steps 204, remap reads the DFLASH after reset and at each power-up stage, and remaps the failed address marked as a high failed address in the DFLASH to the second data storage area of the SRAM storage area, repairing the permanent failed address.

Optionally, the MBIST control circuit detects whether the first data storage area of the SRAM storage area has the SRAM failure condition according to a preset period, and stores the storage address with the SRAM failure condition into the DFLASH and marks the storage address as a high failure address.

Fig. 4 is a schematic structural diagram of a chip according to an embodiment of the present invention. As shown in fig. 4, the chip 301 includes an SRAM protection circuit 302. The SRAM protection circuit 302 is disposed in the chip 301. The chip 301 may be a vehicle gauge chip for vehicle control.

The SRAM protection circuit 302 includes an MBIST control circuit, DFLASH, ECC generation circuit, failure address recording circuit, MUX strobe circuit, and or gate, and further includes an ECC detection circuit, MBIST result circuit, remap circuit, and failure address comparison circuit.

The SRAM memory region includes a first data memory region and a second data memory region.

The ECC detection circuit detects a failure mode of a first data storage area of the SRAM storage area, stores the detected failure address into the DFLASH, marks the failure address as a low failure address, triggers the MBIST control circuit to detect, when the failure address is detected to have an SRAM failure condition, defines the failure address as an MBIST failure address and stores the MBIST failure address into the MBIST result circuit, and the failure address comparison circuit compares the MBIST failure address stored in the MBIST result circuit with the failure address stored in the DFLASH, and if the failure address and the failure address are the same, determines the failure address stored in the DFLASH as a permanent failure address and marks the failure address as a high failure address.

In the technical scheme of the embodiment of the invention, the SRAM protection circuit arranged in the chip can comprehensively and accurately detect whether the storage area in the SRAM is invalid based on the ECC detection circuit, the MBIST control circuit, the fault address comparison circuit and the Remap circuit, process the invalid storage area and replace the permanently invalid storage area for storing data by the blank storage area.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. an SRAM protection circuit, comprises MBIST control circuit, DFLASH, ECC generation circuit, fault address recording circuit, MUX gating circuit and OR gate, it is characterized in that, also comprises: ECC detection circuit, MBIST result circuit, Remap circuit and fault address comparison circuit;

Wherein, the SRAM storage area includes a first data storage area and a second data storage area;

Described ECC checkout circuit detects the failure mode of the first data storage area of the SRAM storage area, and the failure fault address detected is stored in the described DFLASH and is marked as low fault address, and triggers the described MBIST control circuit to detect; Described MBIST control circuit, when detecting that there is SRAM failure condition in the described failure fault address, defines the described failure fault address as the MBIST failure fault address, and is stored in the described MBIST result circuit; Described fault address comparison circuit compares the described MBIST failure fault address of storing in the described MBIST result circuit with the described failure fault address of storing in the described DFLASH, if both are identical, then determines that the described failure fault address of storing in the described DFLASH is a permanent failure fault address, and described failure fault address is marked as high fault address;

The remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault address marked as a high fault address in the DFLASH to the second data storage area of the SRAM storage area to repair the permanent failed fault address.

2. SRAM protection circuit according to claim 1, it is characterized in that, described ECC detection circuit after receiving the data read request corresponding to the first data storage area of described SRAM storage area, according to the error correction code stored in the first data storage area, detect whether the storage area of the address to be read mapping with described data read request fails, if so, described address to be read is defined as failure fault address, described failure fault address is stored in described DFLASH and is marked as low fault address, and triggers described MBIST control circuit to detect described failure fault address.

3. SRAM protection circuit according to claim 1, it is characterized in that, described mbist control circuit is after receiving the detection trigger information corresponding to described failure fault address, by described MUX gating circuit and described Remap circuit, test data is written to the storage area mapped with described failure fault address, according to the data stored in the storage area mapped with described failure fault address, detect whether described failure fault address has SRAM failure situation, if so, then described failure fault address is defined as mbist failure fault address, and be stored in described mbist result circuit.

4. SRAM protection circuit according to claim 1, it is characterized in that, described fault address comparing circuit reads the described MBIST failure fault address of storing in the described MBIST result circuit and the described failure fault address of storing in the described DFLASH, whether relatively described MBIST failure fault address is identical with the described failure fault address, if so, then determine that the described failure fault address of storing in the described DFLASH is permanent failure fault address, the described failure fault address of storing in the described DFLASH is labeled as high fault address.

5. A SRAM protection method, applied to the SRAM protection circuit as claimed in claim 1, characterized in that it comprises:

The ECC detection circuit detects the failure mode of the first data storage area of the SRAM storage area, stores the detected failure fault address in the DFLASH and marks it as a low fault address, and triggers the MBIST control circuit to perform detection;

When detecting that there is SRAM failure condition in the described failure fault address, the MBIST control circuit defines the described failure fault address as the MBIST failure fault address, and is stored in the MBIST result circuit;

Fault address comparison circuit compares the described MBIST failure fault address stored in the described MBIST result circuit with the described failure fault address stored in the described DFLASH, if both are identical, then determines that the described failure fault address stored in the described DFLASH is a permanent failure fault address, and described failure fault address is marked as high fault address;

The remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault addresses marked as high fault addresses in the DFLASH to the second data storage area of the SRAM storage area to repair the permanent failed fault addresses.

6. SRAM protection method according to claim 5, is characterized in that, ECC detection circuit detects the failure mode of the first data storage area of SRAM storage area, detected failure fault address is stored in DFLASH and is marked as low fault address, and triggers MBIST control circuit to detect, comprising:

After receiving a data read request corresponding to a first data storage area of the SRAM storage area, the ECC detection circuit detects whether the storage area mapped to the address to be read of the data read request is invalid according to the error correction code stored in the first data storage area. If so, the address to be read is defined as a failed fault address, the failed fault address is stored in DFLASH and marked as a low fault address, and the MBIST control circuit is triggered to detect the failed fault address.

7. SRAM protection method according to claim 5, is characterized in that, mbist control circuit is defined as mbist failure address with described failure fault address when detecting there is SRAM failure condition, and is stored to mbist result circuit, comprising:

After receiving the detection trigger information corresponding to the failure fault address, the MBIST control circuit writes the test data to the storage area mapped to the failure fault address through the MUX selection circuit and the Remap circuit, and detects whether the failure fault address has an SRAM failure according to the data stored in the storage area mapped to the failure fault address. If so, the failure fault address is defined as the MBIST failure fault address and stored in the MBIST result circuit.

8. SRAM protection method according to claim 5, it is characterized in that, fault address comparison circuit compares the described MBIST failure fault address of storing in the described MBIST result circuit with the described failure fault address of storing in the described DFLASH, if both are identical, then determine that the described failure fault address of storing in the described DFLASH is permanent failure fault address, described failure fault address is labeled as high fault address, comprising:

A fault address comparison circuit reads the MBIST failure fault address stored in the MBIST result circuit and the failure fault address stored in the DFLASH, compares whether the MBIST failure fault address is the same as the failure fault address, and if so, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address stored in the DFLASH as a high fault address.

9. The SRAM protection method according to claim 5, further comprising:

The MBIST control circuit detects whether there is an SRAM failure in the first data storage area of the SRAM storage area according to a preset cycle, stores the storage address with the SRAM failure in the DFLASH and marks it as a high fault address.

10. A chip, comprising the SRAM protection circuit according to claim 1.