CN119277800A - IGBT structure and semiconductor devices - Google Patents

Abstract

The application discloses an IGBT structure and a semiconductor device, wherein the IGBT structure comprises a substrate, a drift, a collector region of a first conduction type, an active gate, a body region of the first conduction type, a first emitting region of a second conduction type and a virtual gate, the virtual gate extends into the drift region from a second main surface of the substrate to a first main surface of the substrate, the drift region comprises a first column region of the first conduction type and a second column region of the second conduction type, the first column region and the second column region are alternately arranged in the horizontal direction, one end of the active gate, which faces the first main surface, extends into the second column region, and one end of the virtual gate, which faces the first main surface, extends into the first column region. According to the IGBT structure and the semiconductor device, the conduction loss can be remarkably reduced.

Description

IGBT structure and semiconductor device

Technical Field

The application relates to the technical field of semiconductors, in particular to an IGBT structure and a semiconductor device.

Background

The IGBT (Insulated Gate Bipolar Transistor ) is a MOS-bipolar composite Transistor developed on the basis of a power MOSFET (Metal Oxide Semiconductor FIELD EFFECT Transistor ), has the common advantages of a power bipolar Transistor and a power MOSFET, and has different advantages in terms of on-voltage drop and switching, thus becoming a core device in power supply, driving and control circuits.

In order to meet different application scenes, the IGBT is required to realize better balance and switching on and off, and lower conduction loss is required to be realized as much as possible so as to improve the power conversion efficiency.

In the conventional IGBT structure, the carrier flow path of the drift region is generally single, and the problem of larger conduction loss exists.

There is therefore a need for an improvement to at least partially solve the above-mentioned problems.

Disclosure of Invention

The present invention aims to at least partially solve the above-mentioned problems. To this end, an object of the present invention is to propose an IGBT structure with low on-loss. Another object of the present invention is to provide a semiconductor device having the IGBT structure.

The IGBT structure according to the embodiment of the invention comprises:

A base body having a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface being arranged at an interval in a vertical direction;

A drift region disposed between the first main surface and the second main surface;

A collector region of the first conductivity type, the collector region being provided on a side of the drift region facing the first main face, a side of the collector region remote from the drift region constituting at least part of the first main face;

An active gate extending from the second main face towards the first main face into the drift region;

A body region of the first conductivity type, which is arranged on one side of the drift region facing the second main surface and on two sides of the active gate in the horizontal direction;

a first emitter region of a second conductivity type, the first emitter region being provided on a side of the body region facing the second main face, a side of the first emitter region remote from the body region constituting part of the second main face;

A dummy gate extending from the second main face into the drift region toward the first main face;

wherein the drift region includes first column regions of a first conductivity type and second column regions of a second conductivity type, the first column regions and the second column regions being alternately arranged in a horizontal direction;

The active gate extends into the second column region toward an end of the first main surface, and the dummy gate extends into the first column region toward an end of the first main surface.

Optionally, the IGBT structure further includes a second emitter region of the first conductivity type, the second emitter region being disposed in the first emitter region, and a side of the second emitter region remote from the first main surface constitutes at least a portion of the second main surface.

Optionally, the IGBT structure further includes:

the insulating layer is arranged on the second main surface, and a contact hole is formed in a part of the insulating layer corresponding to the second emission area;

An emitter metal arranged on one side of the insulating layer away from the second main surface and in the contact hole, wherein the emitter metal is in contact with the second emitter region;

And a collector metal provided on the first main surface.

Optionally, the dummy gate includes a first gate trench extending from the second main surface to the first main surface into the first pillar region, a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench;

the first polysilicon gate is in contact with the emitter metal.

Optionally, the dummy gate includes a first gate trench extending from the second main surface to the first main surface into the first pillar region, a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench;

the first polysilicon gate is a floating gate.

Optionally, the IGBT structure further includes a doped region of the second conductivity type, the doped region being located on both sides of the virtual gate in the horizontal direction and being in contact with the first emitter region, and a side of the doped region remote from the first main surface constitutes at least part of the second main surface.

Optionally, the IGBT structure further includes a field stop region of the second conductivity type, the field stop region being provided between the collector region and the drift region.

Optionally, the active gate includes a second gate trench extending from the second main surface to the first main surface into the second column region, a second gate dielectric layer located on an inner surface of the second gate trench, and a second polysilicon gate located on a side of the second gate dielectric layer away from the inner surface of the second gate trench.

Optionally, the first conductivity type is P-type;

The second conductivity type is N-type.

The semiconductor device according to the embodiment of the invention comprises the IGBT structure.

According to the IGBT structure and the semiconductor device, the drift region comprises the first column regions and the second column regions of the first conductivity type and the second conductivity type which are alternately arranged in the horizontal direction, the arrangement of the first column regions and the second column regions can increase the current path of current carriers, improve the injection efficiency of unbalanced current carriers, reduce the conduction voltage drop of the drift region, and the arrangement of the virtual gate can enhance the current carrier storage effect in the first column regions, further reduce the conduction voltage drop in the first column regions, and further remarkably reduce the conduction loss.

Drawings

The following drawings are included to provide an understanding of the application and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the application and their description to explain the principles and apparatus of the application. In the drawings of which there are shown,

Fig. 1 is a schematic cross-sectional view of an IGBT structure according to an embodiment of the application;

Fig. 2 is a schematic diagram of an IGBT structure according to an embodiment of the application;

Fig. 3 to 9 are schematic cross-sectional views at respective steps of a method of manufacturing an IGBT structure according to an embodiment of the application.

Reference numerals illustrate:

10-substrate, 11-first pillars, 12-second pillars, 13-first gate trenches, 14-second gate trenches, 15-second doped regions;

100-substrate, 101-first main surface, 102-second main surface, 110-drift region, 111-first column region, 112-second column region, 120-collector region, 130-active gate, 140-body region, 150-first emitter region, 160-dummy gate, 170-second emitter region, 180-doped region, 190-field stop region;

200-insulating layers, 210-contact holes;

300-emitter metal;

400-collector metal.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the application may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the application.

It should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. In this way, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the application should not be limited to the specific shapes shown herein, but rather include deviations in shapes that result, for example, from manufacturing. Thus, the illustrations shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of a device and are not intended to limit the scope of the application.

An IGBT structure according to an embodiment of the invention is exemplarily described with reference to fig. 1 and 2. In the following description, N and P represent conductivity types of semiconductors. Next, description will be given of the case where the first conductivity type is P-type and the second conductivity type is N-type.

The IGBT structure mainly includes a body 100, a drift region 110, a collector region 120 of a first conductivity type, an active gate 130, a body region 140 of a first conductivity type, a first emitter region 150 of a second conductivity type, and a dummy gate 160.

The substrate 100 has a first main surface 101 and a second main surface 102 on the opposite side of the first main surface 101, and the first main surface 101 and the second main surface 102 are arranged at intervals in the vertical direction (i.e., in the up-down direction in fig. 1).

The drift region 110 is arranged between the first main face 101 and the second main face 102. The drift region 110 determines the saturation voltage drop and voltage level of the IGBT and is the main area affecting the switching speed of the IGBT.

The collector region 120 of the first conductivity type is provided on the side of the drift region 110 facing the first main face 101, the side of the collector region 120 facing away from the drift region 110 constituting at least part of the first main face 101.

The active gate 130 extends from the second main face 102 into the first main face 101 into the drift region 110. The active gate 130 is a gate structure that actually plays a controlling role in the IGBT and is capable of forming a conductive channel. When a gate voltage is applied to the active gate 130, a conductive channel can be formed around the active gate 130 so that electrons and holes can move in the channel, thereby controlling the turn-on and turn-off of the IGBT.

The body region 140 of the first conductivity type is provided on a side of the drift region 110 facing the second main surface 102, and on both sides of the active gate 130 in the horizontal direction (i.e., in the left-right direction in fig. 1).

The first emitting region 150 of the second conductivity type is disposed on a side of the body region 140 facing the second main surface 102, and a side of the first emitting region 150 remote from the body region 140 constitutes part of the second main surface 102. Illustratively, the first emissive region 150 is also referred to as a source region.

The dummy gate 160 extends from the second main surface 102 into the first main surface 101 into the drift region 110. Dummy gate 160 is a gate structure that is present in an IGBT structure but does not directly participate in conduction, and typically does not form a conduction channel. For example, the dummy gate 160 may also be referred to as a dummy gate.

In the present embodiment, the drift region 110 includes first column regions 111 of the first conductivity type and second column regions 112 of the second conductivity type, and the first column regions 111 and the second column regions 112 (i.e., P column regions and N column regions) are alternately arranged in the horizontal direction, that is, the drift region 110 forms a super junction structure. The active gate 130 extends into the second column region 112 towards one end of the first main face 101 and the dummy gate 160 extends into the first column region 111 towards one end of the first main face 101.

In one aspect, the drift region 110 includes the first column regions 111 and the second column regions 112 alternately arranged to achieve an increase in the carrier flow path, specifically, referring to fig. 2, in addition to the carrier (e.g., hole) entering the second column regions 112 in the downward-upward direction, as shown at a in fig. 2, the carrier (e.g., hole) may enter the second column regions 112 in the horizontal direction from the first column regions 111, and the carrier (e.g., electron) in the second column regions 112 may also enter the first column regions 111 in the horizontal direction. Whereas for conventional IGBT structures, the drift region 110 is typically entirely of the second conductivity type, carriers (e.g., holes) can only enter the second column region 112 in a bottom-up direction. Therefore, the IGBT structure of this embodiment effectively increases the unbalanced carrier flow path, improves the unbalanced carrier injection efficiency, enhances the conductance modulation effect, reduces the conduction voltage drop of the drift region 110, and further reduces the conduction loss.

On the other hand, the drift region 110 forms a cell structure in which the first column regions 111 and the second column regions 112 alternate in the horizontal direction, and in the cut-off state, the first column regions 111 and the second column regions 112 constituting the super junction structure are in a fully depleted state, the electric field distribution in the space charge region is approximately rectangular (as shown at B in fig. 2), the entire drift region 110 is more uniform when subjected to a voltage, and each portion can effectively share the voltage, so that the forward withstand voltage capability of the IGBT structure can be effectively improved.

In addition, since the dummy gate 160 extends into the first pillar region 111 toward one end of the first main surface 101, when the IGBT structure is turned on, no electron channel is generated at the dummy gate 160, and a path of holes reaching the emitter region through the first pillar region 111 is blocked (as shown at C in fig. 2), so that a carrier storage effect in the first pillar region 111 is enhanced, an unbalanced carrier number in the drift region 110 can be effectively enhanced, a conduction voltage drop of the first pillar region 111 can be further reduced, and a conduction loss can be further reduced.

Further, referring to fig. 1, the igbt structure further includes a second emitter region 170 of the first conductivity type, the second emitter region 170 being provided in the first emitter region 150, a side of the second emitter region 170 remote from the first main surface 101 constituting at least part of the second main surface 102. The second emitter region 170 is configured to effectively reduce on-resistance and increase switching speed. Illustratively, the doping concentration of the second emitter region 170 is higher than the doping concentration of the body region 140.

Further, referring to fig. 1, the igbt structure further includes an insulating layer 200, an emitter metal 300, and a collector metal 400.

The insulating layer 200 is disposed on the second main surface 102, and a portion of the insulating layer 200 corresponding to the second emission region 170 is provided with a contact hole 210. The insulating layer 200 covers the side of the active gate 130 away from the first main surface 101, the side of the dummy gate 160 away from the first main surface 101, and the side of the first emission region 150 away from the first main surface 101 on the second main surface 102. The bottom of the contact hole 210 exposes the second emitter region 170. The insulating layer 200 is also illustratively an interlayer dielectric layer, which may be a silicon dioxide layer.

The emitter metal 300 is disposed on a side of the insulating layer 200 away from the second main surface 102, and is disposed in the contact hole 210, and the emitter metal 300 contacts the second emitter region 170 to form a conductive connection. Collector metal 400 is provided on first main surface 101 and contacts collector region 120 to form a conductive connection. The emitter metal 300 and the collector metal 400 are used to achieve electrical extraction of the second emitter region 170 and the collector region 120, respectively.

Further, the dummy gate 160 includes a first gate trench extending from the second main surface 102 into the first main surface 101 into the first pillar region 111, a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench. The active gate 130 includes a second gate trench extending from the second main surface 102 into the first main surface 101 into the second column region 112, a second gate dielectric layer located on an inner surface of the second gate trench, and a second polysilicon gate located on a side of the second gate dielectric layer remote from the inner surface of the second gate trench.

The first polysilicon gate is in contact with the emitter metal 300 (specific contact locations are not shown), i.e., the dummy gate 160 is shorted to the emitter. By shorting dummy gate 160 to the emitter, dummy gate 160 and the emitter can be made to have the same properties and be negatively charged, and when a large amount of holes pass through second column region 112 and body region 140, a portion of the holes can be attracted to transfer to dummy gate 160 (as shown at D in fig. 2), thereby reducing the number of holes flowing under the first emitter, i.e., reducing the number of holes flowing in the channel, and reducing the risk of latch-up during high current conditions.

In other embodiments, the first polysilicon gate in the dummy gate 160 may be a floating gate, i.e., the first polysilicon gate is a gate that is not directly electrically connected to an external circuit. It is surrounded by insulating layers (i.e., the first gate dielectric layer and insulating layer 200) in a "floating" state and is not directly connected to a fixed potential point such as power or ground.

Further, referring to fig. 1, the igbt structure further includes a doped region 180 of the second conductivity type, the doped region 180 being located at both sides of the dummy gate 160 in the horizontal direction and being in contact with the first emission region 150, a side of the doped region 180 remote from the first main surface 101 constituting at least part of the second main surface 102. Specifically, in the present embodiment, the body region 140 is disposed on the side of the second column region 112 facing the second main surface 102 and is located on both sides of the active gate 130 in the horizontal direction, and a portion of the first pillar 11 on the side of the dummy gate 160 facing the active gate 130 is also used to implement the function of the body region 140. The doped region 180 located at the side of the dummy gate 160 facing the active gate 130 contacts the first emitter region 150 and is used to implement the function of the first emitter region 150, and the doped region 180 located at the side of the dummy gate 160 facing away from the active gate 130 may act as a barrier to limit movement of holes so as to enhance the carrier storage effect. In this embodiment, the doped region 180 located at the side of the dummy gate 160 facing the active gate 130 may also be in contact with the second emitter region 170.

In other embodiments, the first emitter regions 150 may be disposed only on both sides of the active gate 130, and the doped regions 180 may not be disposed on both sides of the dummy gate 160, with the side of the first pillar regions 111 remote from the first main face 101 constituting part of the second main face 102.

Further, referring to fig. 1, the igbt structure further includes a Field Stop (Field Stop) region 190 of the second conductivity type, the Field Stop region 190 being provided between the collector region 120 and the drift region 110, the Field Stop region 190 having a higher doping concentration than the drift region 110. The main function of the field stop region 190 is to terminate the electric field in the IGBT off state, preventing the electric field from penetrating into the collector region 120, thereby improving the withstand voltage capability of the device. When a high voltage is applied, the field stop region 190 is able to withstand a portion of the electric field such that the electric field gradually weakens before reaching the collector region 120, avoiding breakdown of the collector region 120. The field stop region 190 may also reduce the duration and amplitude of the tail current by adjusting the carrier distribution and extraction speed. The reduction of the tail current helps to reduce the turn-off loss.

A method of manufacturing the semiconductor device shown in fig. 1 is described below with reference to fig. 3 to 9.

First, referring to fig. 3, a substrate 10 of a second conductivity type is provided.

Then, referring to fig. 4, in forming the first pillars 11 and the second pillars 12 alternately arranged on the substrate 10, the first pillars 11 and the second pillars 12 are respectively of the first conductivity type and the second conductivity type. Specifically, a trench may be etched in the substrate 10 at a position corresponding to the first pillar 11, and then the trench may be filled with a material of the first conductivity type to form the first pillar 11. The substrate 10 remaining after etching forms the second pillars 12.

Then, referring to fig. 5, first and second gate trenches are etched on the first and second pillars 11 and 12, respectively.

Then, referring to fig. 6, dummy gate 160 and active gate 130 are formed in first gate trench 13 and second gate trench 14, respectively. Specifically, a first gate oxide layer and a second gate oxide layer may be formed on the inner surfaces of the first gate trench 13 and the second gate trench 14, respectively, by a thermal oxidation process, and then polysilicon is deposited in the first gate trench 13 and the second gate trench 14, respectively, to form a first polysilicon gate and a second polysilicon gate, respectively.

Then, referring to fig. 7, first doping ions of the first conductivity type are implanted at both sides of the upper active gate 130 of the second column 12 to form a first doping region, and then doping ions of the second conductivity type are implanted at both sides of the upper dummy gate 160 of the first column 11 and the upper portion of the first doping region together to form a second doping region 15. A portion of the first column 11 and a portion of the second column 12 into which the dopant ions are not implanted are a first column region 111 and a second column region 112, respectively, and a portion of the first doped region between the second column region 112 and the second doped region 15 is a body region 140. A portion of the first pillar region 111 on the side of the first pillar region 111 facing the active gate 130 also performs the function of the body region 140.

Then, referring to fig. 8, an insulating layer 200 is formed on the first emission region 150, the active gate 130 and the dummy gate 160, and a contact hole 210 is etched in the insulating layer 200, and then a first conductive type of dopant ions are implanted into the contact hole 210 to form a second emission region 170 in the second doped region 15, portions of the second doped region 15 on both sides of the active gate 130, which are not doped with the dopant ions, constitute the first emission region 150, and portions of the second doped region 15 on both sides of the dummy gate 160, which are not doped with the dopant ions, constitute the doped region 180.

Then, referring to fig. 9, a metal is deposited on the upper portion of the insulating layer 200 and in the contact hole 210 to form an emitter metal 300. A field stop region 190, a collector region 120, and a collector metal 400 are sequentially formed on the lower sides of the first and second column regions 111 and 112.

The application also provides a semiconductor device, which comprises the IGBT structure. The semiconductor device may be a power semiconductor device.

Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the above illustrative embodiments are merely illustrative and are not intended to limit the scope of the present application thereto. Various changes and modifications may be made therein by one of ordinary skill in the art without departing from the scope and spirit of the application. All such changes and modifications are intended to be included within the scope of the present application as set forth in the appended claims.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, e.g., the division of the elements is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another device, or some features may be omitted or not performed.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in order to streamline the application and aid in understanding one or more of the various inventive aspects, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of the application. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.

It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be combined in any combination, except combinations where the features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims (10)

1. An IGBT structure, comprising: A substrate (100), the substrate (100) having a first main surface (101) and a second main surface (102) on the opposite side of the first main surface (101), the first main surface (101) and the second main surface (102) being arranged at an interval in the vertical direction; A drift region (110), wherein the drift region (110) is disposed between the first main surface (101) and the second main surface (102); A collector region (120) of a first conductivity type, the collector region (120) being arranged on a side of the drift region (110) facing the first main surface (101), and a side of the collector region (120) away from the drift region (110) constituting at least a portion of the first main surface (101); an active gate (130), the active gate (130) extending from the second main surface (102) toward the first main surface (101) into the drift region (110); A body region (140) of a first conductivity type, the body region (140) being arranged on a side of the drift region (110) facing the second main surface (102) and located on both sides of the active gate (130) in a horizontal direction; a first emitter region (150) of a second conductivity type, the first emitter region (150) being arranged on a side of the body region (140) facing the second main surface (102), and a side of the first emitter region (150) away from the body region (140) constituting a portion of the second main surface (102); a virtual gate (160), the virtual gate (160) extending from the second main surface (102) toward the first main surface (101) into the drift region (110); The drift region (110) comprises a first column region (111) of a first conductivity type and a second column region (112) of a second conductivity type, and the first column region (111) and the second column region (112) are alternately arranged in a horizontal direction; One end of the active gate (130) facing the first main surface (101) extends into the second column region (112), and one end of the dummy gate (160) facing the first main surface (101) extends into the first column region (111). 2. The IGBT structure according to claim 1, characterized in that: The IGBT structure further comprises a second emitter region (170) of the first conductivity type, wherein the second emitter region (170) is arranged in the first emitter region (150), and a side of the second emitter region (170) away from the first main surface (101) constitutes at least a part of the second main surface (102). 3. The IGBT structure according to claim 2, characterized in that: The IGBT structure further includes: An insulating layer (200), the insulating layer (200) being disposed on the second main surface (102), and a contact hole (210) being disposed in a portion of the insulating layer (200) corresponding to the second emission region (170); an emitter metal (300), the emitter metal (300) being disposed on a side of the insulating layer (200) away from the second main surface (102) and disposed in the contact hole (210), the emitter metal (300) being in contact with the second emitter region (170); A collector metal (400), wherein the collector metal (400) is provided on the first main surface (101). 4. The IGBT structure according to claim 3, characterized in that: The virtual gate (160) comprises a first gate trench extending from the second main surface (102) to the first main surface (101) to the first column region (111), a first gate dielectric layer located on the inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench; The first polysilicon gate is in contact with the emitter metal (300). 5. The IGBT structure according to claim 1, characterized in that: The virtual gate (160) comprises a first gate trench extending from the second main surface (102) to the first main surface (101) to the first column region (111), a first gate dielectric layer located on the inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench; The virtual gate (160) is a floating gate. 6. The IGBT structure according to claim 1, characterized in that: The IGBT structure further comprises a doped region (180) of a second conductivity type, wherein the doped region (180) is located on both sides of the virtual gate (160) in a horizontal direction and is in contact with the first emitter region (150), and a side of the doped region (180) away from the first main surface (101) constitutes at least a portion of the second main surface (102). 7. The IGBT structure according to claim 1, characterized in that: The IGBT structure further comprises a field stop region (190) of the second conductivity type, wherein the field stop region (190) is arranged between the collector region (120) and the drift region (110). 8. The IGBT structure according to claim 1, characterized in that: The active gate (130) comprises a second gate trench extending from the second main surface (102) to the first main surface (101) to the second column region (112), a second gate dielectric layer located on the inner surface of the second gate trench, and a second polysilicon gate located on a side of the second gate dielectric layer away from the inner surface of the second gate trench. 9. The IGBT structure according to any one of claims 1 to 8, characterized in that: The first conductivity type is P type; The second conductivity type is N type. 10. A semiconductor device, characterized by comprising the IGBT structure according to any one of claims 1 to 9.