CN119275214B - Characterization device for corrosion process monitoring - Google Patents
Characterization device for corrosion process monitoring Download PDFInfo
- Publication number
- CN119275214B CN119275214B CN202411808777.0A CN202411808777A CN119275214B CN 119275214 B CN119275214 B CN 119275214B CN 202411808777 A CN202411808777 A CN 202411808777A CN 119275214 B CN119275214 B CN 119275214B
- Authority
- CN
- China
- Prior art keywords
- cathode
- anode
- polysilicon
- metal
- oxide dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
本发明提出一种用于腐蚀工艺监控的表征器件，属于半导体技术领域。表征器件包括衬底、场氧介质层、栅氧介质层、金属前介质层、阳极多晶硅、阴极多晶硅、阳极接触孔、阴极接触孔、阳极金属、阴极金属、阳极、阴极，还包括划分的第一有源区、第二有源区、第三有源区、场区，有源区上设置的阳极多晶硅和阴极多晶硅互不相连，且分别由阳极金属和阴极金属引出，通过对阳极和阴极进行电压扫描测试，可表征集成电路工艺制造过程中多晶硅残余和场区腐蚀问题，从而指导工艺技术优化开发。提升集成电路的可靠性。同时，在引出端口采用多晶硅连接，增加了腐蚀工艺的复杂度，从另一个维度上进一步表征工艺的稳定性。
The present invention proposes a characterization device for monitoring corrosion process, which belongs to the field of semiconductor technology. The characterization device includes a substrate, a field oxide dielectric layer, a gate oxide dielectric layer, a metal pre-dielectric layer, anode polysilicon, cathode polysilicon, anode contact hole, cathode contact hole, anode metal, cathode metal, anode, cathode, and also includes a divided first active area, a second active area, a third active area, and a field area. The anode polysilicon and cathode polysilicon arranged on the active area are not connected to each other, and are respectively led out by the anode metal and the cathode metal. By performing a voltage scanning test on the anode and the cathode, the polysilicon residue and field area corrosion problems in the integrated circuit process manufacturing process can be characterized, thereby guiding the optimization and development of process technology. Improve the reliability of integrated circuits. At the same time, the use of polysilicon connection at the lead-out port increases the complexity of the corrosion process, and further characterizes the stability of the process from another dimension.
Description
Technical Field
The invention relates to a semiconductor technology, in particular to a characterization device for corrosion process monitoring.
Background
Integrated circuits are used as the core of information technology and are the key foundation for the development of various strategic emerging industries. With the rapid growth of the integrated circuit industry, integrated circuit reliability presents a significant challenge. Reliability of integrated circuits is involved in many areas including design, fabrication, packaging, and testing. In the development of new technologies, the reliability of each new module and its interaction with other modules is critical and affects the reliability of the product. Defects such as scratches, stains, scribe stress, photolithographic defects, corrosion defects, etc. on the surface of the silicon wafer during the process are present and have a significant impact on the average lifetime of the integrated circuit. Thin polysilicon is transparent to visible light during integrated circuit fabrication, so polysilicon residues are not easily found, well-in-wafer uniformity is insufficient during processing associated with insufficient overpolish time, and some designs have recessed localized areas that are difficult to clean, which can lead to polysilicon residues in the integrated circuit, causing abnormal and damaging circuit operation. For an integrated circuit to function properly and with high reliability, the manufacturing process of the integrated circuit must be monitored and characterized. The present invention therefore proposes a characterization device for corrosion process monitoring for characterizing the effect of a corrosion process.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a characterization device for corrosion process monitoring aiming at the reliability problem of the integrated circuit.
The technical scheme adopted by the invention for solving the technical problems is as follows:
The characterization device comprises a substrate, a field oxygen dielectric layer, a gate oxygen dielectric layer, a pre-metal dielectric layer, anode polysilicon, cathode polysilicon, an anode contact hole, a cathode contact hole, anode metal, cathode metal, an anode and a cathode;
Four field oxide dielectric layers are uniformly arranged above the substrate at intervals, and gate oxide dielectric layers are arranged at three gaps of the four field oxide dielectric layers, so that the field oxide dielectric layers and the gate oxide dielectric layers are alternately distributed; seen from the overlooking direction of the characterization device, the area provided with the field oxide dielectric layer is divided into a field area, and the area of three gate oxide dielectric layers spaced in the middle of the field oxide dielectric layer is divided into a first active area, a second active area and a third active area;
The anode polysilicon and the cathode polysilicon are in a long strip shape and are uniformly and alternately staggered on the upper surfaces of the gate oxide dielectric layer and the field oxide dielectric layer, the long sides of the anode polysilicon and the cathode polysilicon are perpendicular to the long sides of the field oxide dielectric layer and the gate oxide dielectric layer when the characterization device is seen from the overlooking direction, the long sides of the anode polysilicon and the cathode polysilicon cross all the field oxide dielectric layers and the gate oxide dielectric layer, and the short sides of the anode polysilicon and the cathode polysilicon are arranged on the upper surfaces of the two edge field oxide dielectric layers; the anode polysilicon and the cathode polysilicon are arranged on the upper surfaces of the field oxide dielectric layer and the gate oxide dielectric layer, the upper surfaces of the field oxide dielectric layer and the gate oxide dielectric layer are not covered by the anode polysilicon and the cathode polysilicon, the anode metal and the cathode metal are arranged on the upper surfaces of the metal front dielectric layer, the anode metal and the cathode metal are respectively arranged right above the two edge field oxide dielectric layers when viewed from the overlooking direction of the characterization device, the long side directions of the anode metal and the cathode metal are parallel to the long side direction of the field oxide dielectric layer, the anode contact hole is arranged at the edge of the anode metal, which is close to the short side, of the Fang Yangji polysilicon, the anode metal and the anode polysilicon are isolated by the metal front dielectric layer and are connected and led out by the anode contact hole to form an anode, the cathode contact hole is arranged at the edge of the cathode polysilicon, which is close to the short side, of the cathode metal is isolated by the metal front dielectric layer and is led out by the cathode contact hole to form a cathode.
Further, the anode polysilicon and the cathode polysilicon are arranged at intervals, are not connected with each other, and are at least two.
Further, the long sides of the anode polysilicon and the cathode polysilicon are not aligned with the field oxide dielectric layer when viewed from the top view of the characterization device.
The invention also provides another characterization device for corrosion process monitoring, which comprises a substrate, a field oxygen dielectric layer, a gate oxygen dielectric layer, anode polysilicon, cathode polysilicon, an anode, a cathode, anode second polysilicon and cathode second polysilicon;
Four field oxide dielectric layers are uniformly arranged above the substrate at intervals, gate oxide dielectric layers are arranged at three gaps of the four field oxide dielectric layers, so that the field oxide dielectric layers and the gate oxide dielectric layers are alternately distributed, the area provided with the field oxide dielectric layers is divided into field areas when seen from the overlooking direction of the characterization device, the area provided with the three gate oxide dielectric layers at intervals among the field oxide dielectric layers is divided into a first active area, a second active area and a third active area, the anode polysilicon and the cathode polysilicon are in strip shapes and are alternately staggered and arranged on the upper surfaces of the gate oxide dielectric layers and the upper surfaces of the gate oxide dielectric layers, the long sides of the anode polysilicon and the cathode polysilicon are perpendicular to the long sides of the field oxide dielectric layers and the gate oxide dielectric layers when seen from the overlooking direction of the characterization device, the long sides of the anode polysilicon and the cathode polysilicon cross all the field oxide dielectric layers and the gate oxide dielectric layers, the short sides of the anode polysilicon and the cathode polysilicon are arranged on the upper surfaces of the two edge field oxide dielectric layers, the anode polysilicon and the cathode polysilicon are respectively arranged on the upper surfaces of the two edge field oxide dielectric layers, the anode polysilicon and the cathode polysilicon are not connected with the second polysilicon, and the long sides of the anode polysilicon and the cathode polysilicon are not connected with the anode polysilicon and the cathode polysilicon are led out, and the anode polysilicon and the cathode polysilicon are not connected with the second polysilicon, and the anode polysilicon and the cathode polysilicon is not connected with the anode polysilicon and the second polysilicon.
Further, the anode polysilicon and the cathode polysilicon are arranged at intervals, are not connected with each other, and are at least two.
Further, the long sides of the anode polysilicon and the cathode polysilicon are not aligned with the field oxide dielectric layer when viewed from the top view of the characterization device.
The invention also provides another characterization device for corrosion process monitoring, which comprises a substrate, a field oxygen dielectric layer, a gate oxygen dielectric layer, a pre-metal dielectric layer, anode metal, cathode metal, anode second metal, cathode second metal, an anode and a cathode;
Four field oxide dielectric layers are uniformly arranged above the substrate at intervals, grid oxide dielectric layers are arranged at three gaps of the four field oxide dielectric layers, so that the field oxide dielectric layers and the grid oxide dielectric layers are alternately distributed, the area provided with the field oxide dielectric layers is divided into a field area when seen from the overlooking direction of the characterization device, the area of the three grid oxide dielectric layers at intervals among the field oxide dielectric layers is divided into a first active area, a second active area and a third active area, metal front dielectric layers are arranged on the upper surfaces of the field oxide dielectric layers and the grid oxide dielectric layers, anode metal, cathode metal, anode second metal and cathode second metal are arranged on the surfaces of the metal front dielectric layers, the anode second metal and the cathode second metal are uniformly staggered and distributed on the surfaces of the metal front dielectric layers, the long sides of the anode second metal and the cathode second metal are perpendicular to the long sides of the field oxide dielectric layers and the grid oxide dielectric layers when seen from the overlooking direction of the characterization device, the long sides of the anode second metal and the cathode second metal cross all the field oxide dielectric layers and the grid oxide dielectric layers, the short sides of the anode second metal and the cathode second metal are arranged on the edges of the two field oxide dielectric layers, the anode second metal and the cathode metal are not parallel to the anode metal and the cathode metal are led out of the two metal front surfaces of the anode metal and the cathode metal.
Further, the anode second metal and the cathode second metal are arranged at intervals and are not connected with each other, the anode second metal is at least two, and the cathode second metal is at least two.
Further, the long sides of the anode second metal and the cathode second metal are not aligned with the field oxide dielectric layer when viewed from the top view of the characterization device.
The characterization device for corrosion process monitoring has the beneficial effects that the characterization device for corrosion process monitoring is provided with the plurality of active areas which are not connected with each other, the active areas are isolated by the field, the anode polysilicon and the cathode polysilicon are arranged on the active areas and the field at intervals, and a certain interval exists between the anode polysilicon and the cathode polysilicon and is used for characterizing the problems of polysilicon residue and field corrosion in the integrated circuit process manufacturing process, so that the optimization development of process technology is guided, and the reliability of an integrated circuit is improved. Meanwhile, the extraction ports are connected by polysilicon, so that the complexity of the corrosion process is increased, and the stability of the process is further characterized in another dimension.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 is a perspective view of a structure for corrosion process monitoring in accordance with a first embodiment of the present invention.
Fig. 2 is a top view of a structure for corrosion process monitoring in accordance with a first embodiment of the present invention.
Fig. 3 is a sectional view taken along the direction A1-A2 in fig. 2.
Fig. 4 is a sectional view taken along the direction B1-B2 in fig. 2.
Fig. 5 is a sectional view taken along the direction C1-C2 in fig. 2.
Fig. 6 is a sectional view taken along the direction D1-D2 in fig. 2.
Fig. 7 is a sectional view taken along the direction E1-E2 in fig. 2.
Fig. 8 is a cross-sectional view taken along the direction F1-F2 in fig. 2.
Fig. 9 is a perspective view of a structure for corrosion process monitoring in accordance with a second embodiment of the present invention.
Fig. 10 is a perspective view of a structure for corrosion process monitoring in accordance with a third embodiment of the present invention.
The reference numerals illustrate 11-substrate, 21-field oxide dielectric layer, 22-gate oxide dielectric layer, 23-pre-metal dielectric layer, 101-first active region, 102-second active region, 103-third active region, 201-field region, 31-anode polysilicon, 32-cathode polysilicon, 33-anode second polysilicon, 34-cathode second polysilicon, 41-anode contact hole, 42-cathode contact hole, 51-anode metal, 52-cathode metal, 53-anode second metal, 54-cathode second metal, 301-anode, 302-cathode.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
The invention provides a characterization device for corrosion process monitoring, and a longitudinal three-dimensional structure schematic diagram is shown in fig. 1, wherein the characterization device comprises a substrate 11, a field oxygen dielectric layer 21, a gate oxygen dielectric layer 22, a pre-metal dielectric layer 23, anode polysilicon 31, cathode polysilicon 32, an anode contact hole 41, a cathode contact hole 42, anode metal 51, cathode metal 52, an anode 301 and a cathode 302.
Four field oxide dielectric layers 21 are uniformly arranged above the substrate 11 at intervals, and gate oxide dielectric layers 22 are arranged at three gaps of the four field oxide dielectric layers 21, so that the field oxide dielectric layers 21 and the gate oxide dielectric layers 22 are alternately distributed. As shown in fig. 2, the region where the field oxide dielectric layer 21 is provided is divided into a field region 201 as viewed from the top view of the characterization device, and the region of three gate oxide dielectric layers spaced apart in the middle of the field oxide dielectric layer 21 is divided into a first active region 101, a second active region 102, and a third active region 103. The anode polysilicon 31 and the cathode polysilicon 32 are in a long strip shape and are uniformly and alternately staggered on the upper surfaces of the gate oxide dielectric layer 22 and the field oxide dielectric layer 21, the long sides of the anode polysilicon 31 and the cathode polysilicon 32 are perpendicular to the long sides of the field oxide dielectric layer 21 and the gate oxide dielectric layer 22 when viewed from the overlooking direction of the characterization device, the long sides of the anode polysilicon 31 and the cathode polysilicon 32 cross all the field oxide dielectric layer 21 and the gate oxide dielectric layer 22 and are not in line with the field oxide dielectric layer, and the short sides of the anode polysilicon 31 and the cathode polysilicon 32 are arranged on the upper surfaces of the two edge field oxide dielectric layers 21. The upper surfaces of the anode polysilicon 31 and the cathode polysilicon 32, and the upper surfaces of the field oxide dielectric layer 21 and the gate oxide dielectric layer 22 not covered by the anode polysilicon 31 and the cathode polysilicon 32 are provided with a metal front dielectric layer 23. The anode metal 51 and the cathode metal 52 are disposed on the upper surface of the metal front dielectric layer 23, and the anode metal 51 and the cathode metal 52 are disposed directly above the two fringe field oxide dielectric layers 21, respectively, and the long side directions of the anode metal 51 and the cathode metal 52 are parallel to the long side direction of the field oxide dielectric layers 21, as viewed from the top view of the characterization device. The anode contact hole 41 is provided below the anode metal 51 at the edge of the anode polysilicon 31 near the short side. The anode metal 51 and the anode polysilicon 31 are isolated by the metal front dielectric layer 23 and are led out through the anode contact hole 41, so as to form an anode 301. The cathode contact hole 42 is arranged at the edge of the cathode polysilicon 32 below the cathode metal 52 near the short side, the cathode metal 52 and the cathode polysilicon 32 are isolated by the metal front dielectric layer 23, and are connected and led out through the cathode contact hole 42 to form a cathode 302.
As can be seen from a top view of the characterization device, the characterization device is divided into four areas, namely a first active area 101, a second active area 102, a third active area 103 and a field area 201, wherein the first active area 101, the second active area 102 and the third active area 103 respectively characterize different device active areas in process integration, and the field area 201 characterizes isolation areas among different devices.
The anode polysilicon 31 and the cathode polysilicon 32 cross the first active region 101, the second active region 102 and the third active region 103, the short sides of the anode polysilicon 31 and the cathode polysilicon 32 overlap the field region 201, the anode contact hole 41 and the cathode contact hole 42 are disposed on the field region 201, the anode metal 51 and the cathode metal 52 are disposed on the field region 201, the anode metal 51 connects the anode polysilicon 31 together through the anode contact hole 41, the cathode metal 52 connects the cathode polysilicon 32 together through the cathode contact hole 42, and the anode polysilicon 31 and the cathode polysilicon 32 are not connected to each other.
In one embodiment of the present invention, the anode polysilicon 31 and the cathode polysilicon 32 are arranged at intervals, and are not connected to each other, and the number of the anode polysilicon 31 and the cathode polysilicon 32 is at least 2.
In one embodiment of the present invention, the plurality of active regions are not connected to each other, and the plurality of active regions are separated by field regions 201, and the number of active regions is at least 2, for testing the polycrystalline residual structure in the process.
In one embodiment of the present invention, the anode contact hole 41 and the cathode contact hole 42 are both disposed on the field region 201, the anode metal 51 leads the anode polysilicon 31 out by using the anode contact hole 41, and the cathode metal 52 leads the cathode polysilicon 32 out by using the cathode contact hole 42.
In one embodiment of the present invention, the anode metal 51 and the cathode metal 52 are respectively used as an anode 301 and a cathode 302 of the monitoring structure for voltage bias test after the monitoring structure is subjected to flow sheet.
Fig. 3 is a cross-sectional view taken along the direction A1-A2 in the embodiment of fig. 2, where the device includes a first active region 101 and a field region 201, where a field oxide dielectric layer 21 is disposed on the field region, a gate oxide dielectric layer 22 is disposed on the substrate 11 in the area of the first active region 101, and an anode polysilicon 31 and a cathode polysilicon 32 are arranged on the upper surface of the gate oxide dielectric layer 22 at intervals, and adjacent anode polysilicon 31 and cathode polysilicon 32 are isolated by a pre-metal dielectric layer 23.
Fig. 4 is a cross-sectional view taken along the direction B1-B2 of the embodiment of fig. 2, in which a field region 201 of the device is formed, a field oxide dielectric layer 21 is disposed on a substrate 11, and anode polysilicon 31 and cathode polysilicon 32 are arranged on the upper surface of the field oxide dielectric layer 21 at intervals, and adjacent anode polysilicon 31 and cathode polysilicon 32 are isolated by a pre-metal dielectric layer 23.
Fig. 5 is a cross-sectional view taken along the direction C1-C2 in the embodiment of fig. 2, wherein the direction is the field region 201 of the device, the field oxide dielectric layer 21 is disposed on the substrate 11, a plurality of cathode polysilicon 32 are arranged on the upper surface of the field oxide dielectric layer 21 at intervals, and the cathode polysilicon 32 is led out through the cathode contact hole 42 and the cathode metal 52 to form the cathode 302 of the device.
Fig. 6 is a cross-sectional view taken along the direction D1-D2 in the embodiment of fig. 2, in which the device has a first active region 101, a second active region 102 and a third active region 103 spaced apart from each other by a field region 201, a field oxide dielectric layer 21 is disposed in the field region 201, a gate oxide dielectric layer 22 is disposed in the first active region 101, the second active region 102 and the third active region 103, and an anode metal 51 and a cathode metal 52 are disposed on the surface of the pre-metal dielectric layer 23.
Fig. 7 is a cross-sectional view taken along the direction E1-E2 in the embodiment of fig. 2, where the device includes a first active region 101, a second active region 102, a third active region 103, and a field region 201, a field oxide dielectric layer 21 is disposed in the field region 201, gate oxide dielectric layers 22 are disposed in the first active region 101, the second active region 102, and the third active region 103, surfaces of the field oxide dielectric layer 21 and the gate oxide dielectric layer 22 cover an anode polysilicon 31, and the anode polysilicon 31 is led out through an anode contact hole 41 and an anode metal 51 to form an anode. The anode metal 51 and the anode polysilicon 31 are isolated by the pre-metal dielectric layer 23.
Fig. 8 is a cross-sectional view taken along the direction F1-F2 in the embodiment of fig. 2, where the device includes a first active region 101, a second active region 102, a third active region 103, and a field region 201, a field oxide dielectric layer 21 is disposed in the field region 201, gate oxide dielectric layers 22 are disposed in the first active region 101, the second active region 102, and the third active region 103, surfaces of the field oxide dielectric layer 21 and the gate oxide dielectric layer 22 cover cathode polysilicon 32, and the cathode polysilicon 32 is led out through a cathode contact hole 42 and a cathode metal 52 to form a cathode. The cathode metal 52 and the cathode polysilicon 32 are isolated by the pre-metal dielectric layer 23.
Example 2
Fig. 9 is a schematic view of a longitudinal three-dimensional structure for an etch process monitoring structure according to a second embodiment of the present invention, the characterization device comprising a substrate 11, a field oxide dielectric layer 21, a gate oxide dielectric layer 22, an anode polysilicon 31, a cathode polysilicon 32, an anode 301, a cathode 302, an anode second polysilicon 33, and a cathode second polysilicon 34.
Four field oxide dielectric layers 21 are uniformly arranged above the substrate 11 at intervals, and gate oxide dielectric layers 22 are arranged at three gaps of the four field oxide dielectric layers 21, so that the field oxide dielectric layers 21 and the gate oxide dielectric layers 22 are alternately distributed. Viewed from the top view direction of the characterization device, the region where the field oxide dielectric layer 21 is arranged is divided into a field region 201, and the regions of three gate oxide dielectric layers spaced in the middle of the field oxide dielectric layer 21 are divided into a first active region 101, a second active region 102 and a third active region 103. The anode polysilicon 31 and the cathode polysilicon 32 are in a long strip shape and are alternately staggered on the upper surfaces of the gate oxide dielectric layer 22 and the field oxide dielectric layer 21, the long sides of the anode polysilicon 31 and the cathode polysilicon 32 are perpendicular to the long sides of the field oxide dielectric layer 21 and the gate oxide dielectric layer 22 when seen from the overlooking direction of the characterization device, the long sides of the anode polysilicon 31 and the cathode polysilicon 32 cross all the field oxide dielectric layer 21 and the gate oxide dielectric layer 22 and are not in line with the field oxide dielectric layer, and the short sides of the anode polysilicon 31 and the cathode polysilicon 32 are arranged on the upper surfaces of the two edge field oxide dielectric layers 21. The anode second polysilicon 33 and the cathode second polysilicon 34 are respectively arranged on the upper surfaces of the two fringe field oxygen medium layers 21, the long side directions of the anode second polysilicon 33 and the cathode second polysilicon 34 are parallel to the long side direction of the field oxygen medium layer 21, the anode second polysilicon 33 is connected with the anode polysilicon 31 to be led out to form an anode 301, and the anode second polysilicon 33 is not connected with the cathode polysilicon 32. The cathode second polysilicon 34 is led out from the cathode polysilicon 32 to form a cathode 302, and the cathode second polysilicon 34 is disconnected from the anode polysilicon 31.
As can be seen from a top view of the characterization device, the characterization device is divided into four areas, namely a first active area 101, a second active area 102, a third active area 103 and a field area 201, wherein the first active area 101, the second active area 102 and the third active area 103 respectively characterize different device active areas in process integration, and the field area 201 characterizes isolation areas among different devices.
The anode polysilicon 31 and the cathode polysilicon 32 cross the first active region 101, the second active region 102 and the third active region 103, the short sides of the anode polysilicon 31 and the cathode polysilicon 32 overlap the field region 201, the anode polysilicon 31 and the cathode polysilicon 32 are not connected to each other, and the anode second polysilicon 33 and the cathode second polysilicon 34 are disposed on the field region 201.
Compared with embodiment 1, the embodiment does not need a contact hole and a metal structure, and the design is simpler. The anode second polysilicon 33 and the cathode second polysilicon 34 which are structurally arranged increase the influence of the etching process on the first active region 101 and the third active region 103 from the width direction, so that the complexity of the etching process is increased, and the accuracy of process monitoring is also increased.
Example 3
Fig. 10 is a schematic view of a longitudinal three-dimensional structure for an etch process monitoring structure according to a third embodiment of the present invention, the characterization device includes a substrate 11, a field oxide dielectric layer 21, a gate oxide dielectric layer 22, a pre-metal dielectric layer 23, an anode metal 51, a cathode metal 52, an anode second metal 53, a cathode second metal 54, an anode 301, and a cathode 302.
Four field oxide dielectric layers 21 are uniformly arranged above the substrate 11 at intervals, and gate oxide dielectric layers 22 are arranged at three gaps of the four field oxide dielectric layers 21, so that the field oxide dielectric layers 21 and the gate oxide dielectric layers 22 are alternately distributed. The field region 201 is divided by the region where the field oxide dielectric layer 21 is provided, and the region of the three gate oxide dielectric layers 22 spaced apart from each other in the middle of the field oxide dielectric layer 21 is divided into the first active region 101, the second active region 102, and the third active region 103 as viewed in the top view of the device. The upper surfaces of the field oxide dielectric layer 21 and the gate oxide dielectric layer 22 are provided with a metal front dielectric layer 23, and an anode metal 51, a cathode metal 52, an anode second metal 53 and a cathode second metal 54 are arranged on the surface of the metal front dielectric layer 23. The surfaces of the metal front dielectric layers 23 are uniformly and alternately staggered by the anode second metal 53 and the cathode second metal 54, the long sides of the anode second metal 53 and the cathode second metal 54 are perpendicular to the long sides of the field oxide dielectric layers 21 and the gate oxide dielectric layers 22 when seen from the overlooking direction of the characterization device, the long sides of the anode second metal 53 and the cathode second metal 54 cross all the field oxide dielectric layers 21 and the gate oxide dielectric layers 22 and are not aligned with the field oxide dielectric layers 21, and the short sides of the anode second metal 53 and the cathode second metal 54 are arranged on the upper surfaces of the two edge field oxide dielectric layers 21. The anode metal 51 and the cathode metal 52 are respectively arranged right above the two edge field oxide dielectric layers 21, and the long side directions of the anode metal 51 and the cathode metal 52 are parallel to the long side direction of the field oxide dielectric layers 21. The anode metal 51 is connected with the anode second metal 53 to form an anode 301, the anode metal 51 is not connected with the cathode second metal 54, the cathode metal 52 is connected with the cathode second metal 54 to form a cathode 302, and the cathode metal 52 is not connected with the anode second metal 53.
In contrast to example 1, this example replaces the anode polysilicon 31 and the cathode polysilicon 32 with the anode second metal 53 and the cathode second metal 54, respectively, for monitoring the metal etching process during the process manufacturing. The structure is a metal structure, the structural design and the process manufacturing are simple, and the process manufacturing cost is low.
It will be understood that the application has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the application without departing from the essential scope thereof. Therefore, it is intended that the application not be limited to the particular embodiment disclosed, but that the application will include all embodiments falling within the scope of the appended claims.
Claims (9)
1. The characterization device for corrosion process monitoring is characterized by comprising a substrate (11), a field oxygen dielectric layer (21), a gate oxygen dielectric layer (22), a pre-metal dielectric layer (23), anode polysilicon (31), cathode polysilicon (32), an anode contact hole (41), a cathode contact hole (42), anode metal (51), cathode metal (52), an anode (301) and a cathode (302);
Four field oxide dielectric layers (21) are uniformly arranged above the substrate (11) at intervals, grid oxide dielectric layers (22) are arranged at three gaps of the four field oxide dielectric layers (21) to enable the field oxide dielectric layers (21) and the grid oxide dielectric layers (22) to be distributed alternately, a region provided with the field oxide dielectric layers (21) is divided into field regions (201) when seen from the overlooking direction of the characterization device, and the region of the three grid oxide dielectric layers (22) at intervals in the middle of the field oxide dielectric layers (21) is divided into a first active region (101), a second active region (102) and a third active region (103);
The anode polysilicon (31) and the cathode polysilicon (32) are in strip shapes and are uniformly and alternately arranged on the upper surfaces of the gate oxide dielectric layer (22) and the field oxide dielectric layer (21) in a staggered manner, the long sides of the anode polysilicon (31) and the cathode polysilicon (32) are perpendicular to the long sides of the field oxide dielectric layer (21) and the gate oxide dielectric layer (22) when viewed from the overlooking direction of the characterization device, the long sides of the anode polysilicon (31) and the cathode polysilicon (32) cross all the field oxide dielectric layer (21) and the gate oxide dielectric layer (22), the short sides of the anode polysilicon (31) and the cathode polysilicon (32) are arranged on the upper surfaces of the two edge field oxide dielectric layers (21), the upper surfaces of the anode polysilicon (31) and the cathode polysilicon (32) and the upper surfaces of the field oxide dielectric layer (21) and the gate oxide dielectric layer (22) are not covered by the metal front dielectric layer (23), the anode metal (51) and the cathode metal (52) are arranged on the upper surfaces of the metal front dielectric layer (23), the characterization device and the anode metal (51) and the cathode polysilicon (32) are respectively arranged on the upper surfaces of the two edge field oxide dielectric layers (21) when viewed from the overlooking direction, the anode metal (51) and the cathode metal (52) are parallel to the long side direction of the field oxygen medium layer (21), the anode contact hole (41) is arranged at the edge of the anode polysilicon below the anode metal (51) close to the short side, the anode metal (51) and the anode polysilicon (31) are isolated through the metal front medium layer (23) and are connected and led out through the anode contact hole (41) to form an anode (301), the cathode contact hole (42) is arranged at the edge of the cathode polysilicon below the cathode metal (52) close to the short side, and the cathode metal (52) and the cathode polysilicon (32) are isolated through the metal front medium layer (23) and are connected and led out through the cathode contact hole (42) to form a cathode (302).
2. The characterization device for corrosion process monitoring according to claim 1, wherein the anode polysilicon (31) and the cathode polysilicon (32) are arranged at intervals, and are not connected to each other, and the anode polysilicon (31) is at least two, and the cathode polysilicon (32) is at least two.
3. Characterization device for corrosion process monitoring according to claim 1 or 2, characterized in that the long sides of the anode polysilicon (31) and the cathode polysilicon (32) are not flush with the field oxide dielectric layer (21) as seen in top view of the characterization device.
4. A characterization device for corrosion process monitoring, characterized in that the characterization device comprises a substrate (11), a field oxide dielectric layer (21), a gate oxide dielectric layer (22), anode polysilicon (31), cathode polysilicon (32), an anode (301), a cathode (302), an anode second polysilicon (33) and a cathode second polysilicon (34);
four field oxide dielectric layers (21) are uniformly arranged above a substrate (11) at intervals, gate oxide dielectric layers (22) are arranged at three gaps of the four field oxide dielectric layers (21) to enable the field oxide dielectric layers (21) and the gate oxide dielectric layers (22) to be alternately distributed, the area provided with the field oxide dielectric layers (21) is divided into field areas (201) when viewed from the overlooking direction of a characterization device, the area of the three gate oxide dielectric layers (22) at intervals in the middle of the field oxide dielectric layers (21) is divided into a first active area (101), a second active area (102) and a third active area (103), anode polycrystalline silicon (31) and cathode polycrystalline silicon (32) are in a strip shape, and are alternately staggered on the upper surfaces of the gate oxide dielectric layers (22) and the field oxide dielectric layers (21), the long sides of the anode polycrystalline silicon (31) and the cathode polycrystalline silicon (32) are perpendicular to the long sides of the field oxide dielectric layers (21) and the gate oxide dielectric layers (22), the anode polycrystalline silicon (31) and the cathode polycrystalline silicon (32) are transversely arranged on the long sides of the field oxide dielectric layers (21) and the edges of the cathode polycrystalline silicon (32) respectively, the long side direction of the anode second polysilicon (33) and the cathode second polysilicon (34) are parallel to the long side direction of the field oxygen medium layer (21), the anode second polysilicon (33) is connected with the anode polysilicon (31) to be led out to form an anode (301), the anode second polysilicon (33) is not connected with the cathode polysilicon (32), the cathode second polysilicon (34) is connected with the cathode polysilicon (32) to be led out to form a cathode (302), and the cathode second polysilicon (34) is not connected with the anode polysilicon (31).
5. The characterization device for corrosion process monitoring according to claim 4, wherein the anode polysilicon (31) and the cathode polysilicon (32) are arranged at intervals, and are not connected to each other, and the anode polysilicon (31) is at least two, and the cathode polysilicon (32) is at least two.
6. The characterization device for corrosion process monitoring according to claim 4 or 5, wherein the long sides of the anode polysilicon (31) and the cathode polysilicon (32) are not aligned with the field oxide dielectric layer (21) as seen in a top view of the characterization device.
7. A characterization device for corrosion process monitoring, characterized in that the characterization device comprises a substrate (11), a field oxygen dielectric layer (21), a gate oxygen dielectric layer (22), a pre-metal dielectric layer (23), anode metal (51), cathode metal (52), anode second metal (53), cathode second metal (54), an anode (301) and a cathode (302);
Four field oxide dielectric layers (21) are uniformly arranged above a substrate (11) at intervals, gate oxide dielectric layers (22) are arranged at three gaps of the four field oxide dielectric layers (21) to enable the field oxide dielectric layers (21) and the gate oxide dielectric layers (22) to be alternately distributed, the area provided with the field oxide dielectric layers (21) is divided into field areas (201) when seen from the overlooking direction of a characterization device, the area of the three gate oxide dielectric layers (22) at intervals in the middle of the field oxide dielectric layers (21) is divided into a first active area (101), a second active area (102) and a third active area (103), a metal front dielectric layer (23) is arranged on the upper surfaces of the field oxide dielectric layers (21) and the gate oxide dielectric layers (22), an anode metal (51), a cathode metal (52), an anode second metal (53) and a cathode second metal (54) are arranged on the surface of the metal front dielectric layer (23), the anode second metal (53) and the cathode second metal (54) are uniformly staggered, seen from the overlooking direction of the characterization device, all sides of the anode second metal (53) and the gate oxide second metal layers (21) and the cathode second metal (54) are vertically distributed across the long sides of the gate oxide dielectric layers (22) and all of the metal front dielectric layers (22), the anode metal (51) and the cathode metal (52) are respectively arranged right above the two fringe field oxygen medium layers (21), the long side directions of the anode metal (51) and the cathode metal (52) are parallel to the long side direction of the field oxygen medium layers (21), the anode metal (51) is connected with the anode second metal (53) to form an anode (301), the anode metal (51) is not connected with the cathode second metal (54), the cathode metal (52) is connected with the cathode second metal (54) to form a cathode (302), and the cathode metal (52) is not connected with the anode second metal (53).
8. The characterization device for corrosion process monitoring according to claim 7, wherein the anode second metal (53) and the cathode second metal (54) are arranged at intervals, and are not connected to each other, wherein the anode second metal (53) is at least two, and the cathode second metal (54) is at least two.
9. The characterization device for corrosion process monitoring according to claim 7 or 8, wherein the long sides of the anode second metal (53) and the cathode second metal (54) are not flush with the field oxide dielectric layer (21) as seen in top view of the characterization device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411808777.0A CN119275214B (en) | 2024-12-10 | 2024-12-10 | Characterization device for corrosion process monitoring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411808777.0A CN119275214B (en) | 2024-12-10 | 2024-12-10 | Characterization device for corrosion process monitoring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN119275214A CN119275214A (en) | 2025-01-07 |
| CN119275214B true CN119275214B (en) | 2025-02-25 |
Family
ID=94115710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411808777.0A Active CN119275214B (en) | 2024-12-10 | 2024-12-10 | Characterization device for corrosion process monitoring |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119275214B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871855A (en) * | 2012-12-17 | 2014-06-18 | 北大方正集团有限公司 | Preparation method of integrated circuit dual gate oxide |
| CN104377190A (en) * | 2013-08-14 | 2015-02-25 | 北大方正集团有限公司 | Device for monitoring alignment error of polycrystalline silicon layer photoetching in integrated circuit technique |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028324A (en) * | 1997-03-07 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | Test structures for monitoring gate oxide defect densities and the plasma antenna effect |
| TW466658B (en) * | 2000-06-28 | 2001-12-01 | Mosel Vitelic Inc | Method to form the identification device of mask ROM |
| AU2003304218A1 (en) * | 2002-11-20 | 2005-01-04 | Reveo, Inc. | Method and system for fabricating multi layer devices on a substrate |
| KR20120081679A (en) * | 2011-01-12 | 2012-07-20 | 에스케이하이닉스 주식회사 | Test pattern for monitoring surface resistance of cell junction |
| CN106356313B (en) * | 2016-11-04 | 2018-12-14 | 东南大学 | The test method of landscape insulation bar double-pole-type transistor interfacial state and 5 port devices |
| US10796973B2 (en) * | 2018-11-09 | 2020-10-06 | Globalfoundries Inc. | Test structures connected with the lowest metallization levels in an interconnect structure |
| KR102499041B1 (en) * | 2019-01-10 | 2023-02-14 | 삼성전자주식회사 | Method of forming semiconductor device |
| CN110411937B (en) * | 2019-07-03 | 2021-04-20 | 北京科技大学 | A Corrosion Monitoring System for Monitoring Environmental Corrosion and Material Corrosion Rates |
-
2024
- 2024-12-10 CN CN202411808777.0A patent/CN119275214B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871855A (en) * | 2012-12-17 | 2014-06-18 | 北大方正集团有限公司 | Preparation method of integrated circuit dual gate oxide |
| CN104377190A (en) * | 2013-08-14 | 2015-02-25 | 北大方正集团有限公司 | Device for monitoring alignment error of polycrystalline silicon layer photoetching in integrated circuit technique |
Also Published As
| Publication number | Publication date |
|---|---|
| CN119275214A (en) | 2025-01-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8242499B2 (en) | Method of producing semiconductor device and SOQ (Silicon On Quartz) substrate used in the method | |
| US8865482B2 (en) | Method of detecting the circular uniformity of the semiconductor circular contact holes | |
| US9269639B2 (en) | Method of detecting and measuring contact alignment shift relative to gate structures in a semicondcutor device | |
| US6521910B1 (en) | Structure of a test key for monitoring salicide residue | |
| US6649986B1 (en) | Semiconductor device with structure for die or dice crack detection | |
| CN101295624A (en) | Defect detecting structure, and production method and detection method thereof | |
| CN119275214B (en) | Characterization device for corrosion process monitoring | |
| KR20070105201A (en) | Method for detecting bottom defects of semiconductor substrate | |
| CN112185838B (en) | Method for manufacturing test structure | |
| US20090212794A1 (en) | Test key for semiconductor structure | |
| US20030040132A1 (en) | Evaluation method for evaluating insulating film, evaluation device therefor and method for manufacturing evaluation device | |
| US7528076B2 (en) | Method for manufacturing gate oxide layer with different thicknesses | |
| CN113192931B (en) | Residual polysilicon monitoring structure, structure layout, method and semiconductor device | |
| KR100787745B1 (en) | PCM test pattern for semiconductor manufacturing | |
| CN115602561B (en) | Structure size measuring method and reference pattern for wafer manufacturing process | |
| US6414334B2 (en) | Semi-conductor device with test element group for evaluation of interlayer dielectric and process for producing the same | |
| TW202034487A (en) | Semiconductor structure, manufacturing method thereof and method for detecting short circuit thereof | |
| CN222146223U (en) | A semiconductor structure | |
| CN218996657U (en) | Fin residue test structure in FinFET process monitoring | |
| CN221708710U (en) | Test structure | |
| TWI855283B (en) | Manufacturing method of semiconductor structure | |
| US8507378B2 (en) | Method and structure for self aligned contact for integrated circuits | |
| JP4087289B2 (en) | Semiconductor device and inspection method thereof | |
| CN116544131A (en) | Method for manufacturing test element group, test element group and test method thereof | |
| JP2024141840A (en) | Semiconductor device, semiconductor device manufacturing method, and semiconductor device inspection method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |