Photomask verification method based on photomask manufacturing error effect
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a photomask verification method based on a photomask manufacturing error effect.
Background
The Mask Error Enhancement Factor (MEEF) quantitatively represents the extent to which feature size errors on a mask affect pattern feature size errors in a photoresist. When the MEEF value is large, the line width of the mask needs to be strictly controlled, and a position having a large MEEF value is likely to be problematic in exposure to light, thereby forming a dead pixel. In conventional Optical Proximity Correction (OPC) procedures, only control of profile curves is of concern, and basic design checking, profile checking and Mask Rule Checking (MRC) control is of insufficient concern for potentially dangerous areas where MEEF is large. The quality control measurement pattern of the photomask is mainly a regular one-dimensional pattern, and the correction of the photomask gradually approaches the limit manufacturing size of the photomask along with the increase of complexity of the layout, so that the position with larger MEEF is required to be timely simulated and found out while the outline is concerned, the more reasonable photomask inspection rule is redefined, the defect that bridging is actually generated due to photomask errors is avoided, and meanwhile, if the whole layout is simulated, the data size is too large, the situation of more errors possibly exists, and the judgment is difficult. In summary, a photomask verification method based on a photomask manufacturing error effect needs to be provided, which can accurately simulate and find a real risk hot spot, define a more reasonable photomask inspection rule, and avoid the occurrence of potential risk defects of the photomask.
Disclosure of Invention
The invention provides a photomask verification method based on photomask manufacturing error effect, which is used for introducing MEEF factors into photomask verification, simulating and screening areas with larger MEEF values near the minimum photoetching value and the photomask manufacturing limit size, predicting potential risks, re-determining photomask inspection specifications, avoiding bridging defects caused by photomask errors, reducing simulation range, and accurately simulating and finding out real risk hot spots.
The invention provides a photomask verification method based on a photomask manufacturing error effect, which comprises the following steps of S1, providing a design pattern, screening a region with a design size smaller than a minimum design size plus a first preset value based on the design pattern as a Target inspection region, S2, conducting OPC correction on the design pattern based on a photomask inspection standard to obtain a corrected pattern, S3, screening a region with a size within a range from a rule limit of a photomask manufacturing size to a second preset value or above based on the corrected pattern based on the Target inspection region, S4, conducting simulation on the POST OPC inspection region to obtain a simulation graph, conducting MEEF analysis, selecting a region with a MEEF value exceeding the MEEF preset value as a MEEF inspection region, and S5, determining a new photomask inspection standard for the MEEF inspection region. By simulating and screening the area with larger MEEF value near the minimum design size and the mask manufacturing limit size, the simulation range is reduced, the risk hot spot can be more accurately determined, and the mask manufacturing error exists in the area with larger MEEF, so that the actual data of the wafer is directly affected. In these areas, the mask inspection rules are redetermined for the MEEF inspection area, taking into account the effects of errors.
In step S1, the first predetermined value is selected according to the minimum design size, where the minimum design size is a minimum size requirement for the design pattern size, and the design pattern satisfying the minimum design size is provided.
In step S1, the minimum design dimensions include a line width minimum design dimension, a pitch minimum design dimension, a corner-to-line minimum design dimension, and a corner-to-corner minimum design dimension, so that hot spots easily occur in a narrow space, defects easily occur in a photolithography process, and more realistic risk hot spots are determined.
In step S1, the first predetermined value is 10% of the minimum design size. And (3) focusing on the area near the minimum design size to screen the Target checking area, so as to reduce the range for subsequent simulation and improve the simulation accuracy.
In step S2, the OPC verification includes Table-driven OPC and Model-based OPC verification, and a corrected pattern is obtained after verification, and a subsequent POST OPC check area definition is performed according to the corrected pattern.
In step S3, the second predetermined value is increased by 20% based on the mask manufacturing dimension rule limit. In the areas near the mask making limit, the risk of bridging is most likely to be found, and the POST OPC inspection area is screened near the mask making limit size.
In step S4, the MEEF predetermined value is 4, and in the area with a larger MEEF value, the error in mask fabrication is amplified during exposure, which is prone to problems and forms a dead pixel.
The mask inspection standard is a bridging verification standard used for OPC correction, and the bridging verification standard is selected according to the minimum design size.
In step S5, the new mask inspection standard is defined as new mask inspection standard=minimum design size- (minimum design size-mask inspection standard) ×50%, and by resetting the stricter mask inspection standard, variation in the manufacturing process is reduced, defective product rate is reduced, and reliability of the product is improved. Compared with the prior art, the method has the advantages that the MEEF factor is introduced into the photomask for verification, and a more reasonable photomask inspection rule is redefined based on the larger MEEF position, so that bridging defects caused by photomask errors are avoided. Meanwhile, areas with larger MEEF values are simulated and screened near the minimum design size and the mask manufacturing limit size, the possible potential risks are predicted, the simulation of the whole layout is not needed, the simulation range is reduced, the data size is smaller, the error conditions are fewer, and more real risk hot spots can be found easily.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a flowchart of a mask verification method based on mask manufacturing error effects according to the present invention;
FIG. 2 is a schematic diagram of a design graphic pattern;
FIG. 3 is a diagram of the screening of the Target inspection area S1;
FIG. 4 is a diagram of S2 after OPC correction;
FIG. 5 is a diagram showing the POST-screening POST OPC inspection area of S3;
FIG. 6 is a schematic diagram of the graph after S4 simulation;
fig. 7 is a schematic diagram of confirming the MEEF check area in S5.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others.
The embodiment provides a photomask verification method based on a photomask manufacturing error effect, and fig. 1 is a flowchart of the photomask verification method based on the photomask manufacturing error effect, and the embodiment takes a design pattern pitch minimum design size of 60nm as an example, and specifically includes the following steps that S1, a design pattern is provided, the design pattern is shown in fig. 2, a region with the design size smaller than the minimum design size plus a first preset value is screened as a Target checking region based on the design pattern, the first preset value is selected according to the minimum design size, and the minimum design size is the minimum size requirement on the design pattern size. The minimum design dimensions include a line width minimum design dimension, a pitch minimum design dimension, a corner-to-line minimum design dimension, and a corner-to-corner minimum design dimension, the first predetermined value is 10% of the minimum design dimension, in this embodiment, for a pitch minimum design dimension of 60nm, the first predetermined value is 6, and a region with a pitch of less than 66nm is defined as a Target inspection region, as shown in the region within the broken line in fig. 3.
S2, based on a photomask inspection standard, OPC correction is carried out on the design pattern to obtain a corrected pattern, wherein the OPC correction comprises Table-driven OPC and Model-based OPC, the corrected pattern is obtained after correction, and the corrected pattern is like a shadow part in FIG. 4;
S3, screening an area with the size in the range from the limit of the mask manufacturing size rule to a second preset value to be used as a POST OPC inspection area based on the Target inspection area, wherein the second preset value is 20% based on the limit of the mask manufacturing size rule, the second preset value is 48nm based on the mask manufacturing limit rule with the middle distance of 40nm in the embodiment, and the area with the screening interval of 40-48 nm is the POST OPC inspection area based on the screened Target inspection area.
S4, performing simulation on the POST OPC inspection area to obtain a simulation graph and performing MEEF analysis, and selecting an area with the MEEF value exceeding a MEEF preset value as the MEEF inspection area, wherein the simulation graph is shown as a dotted line part in FIG. 6, and specifically, the MEEF preset value is 4, as indicated by an arrow in FIG. 6. Through twice region screening, the simulation range is reduced, the simulation data volume is reduced, the probability of error occurrence is reduced, a more accurate simulation result is obtained, and more accurate risk hot spots are screened.
S5, determining a new photomask inspection standard for the screened MEEF inspection area, wherein the wafer actual data is directly affected due to photomask manufacturing errors in the area with the larger MEEF. Therefore, in the areas, the influence of errors is fully considered, a new photomask inspection standard is required to be determined, OPC correction is carried out on the design pattern based on the new photomask inspection standard to obtain a new corrected pattern, wherein the new photomask inspection standard is that the new photomask inspection standard=minimum design size- (minimum design size-photomask inspection standard) is 50%, the photomask inspection standard is a bridging verification standard used for OPC correction, and the bridging verification standard is selected according to the minimum design size. As shown in fig. 7, in this embodiment, the minimum design size of the pitch is 60nm, the mask inspection standard is selected to be 56nm, if the MEEF value of the analog pattern at the position is larger, a new mask inspection standard needs to be determined, the new mask inspection standard is updated to be 60- (60-56) ×50% =58 nm, and the new standard needs to be corrected by 58nm, so that errors in the manufacturing process are reduced, the defective product rate is reduced, and the reliability and consistency of the product are improved. It should be understood that the use of certain conventional english terms or letters for clarity of description herein is for illustrative purposes only and is not intended to be limiting or limiting with respect to the particular use or interpretation of the terms of chinese language or specific letters which are possible. It should also be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.