CN119254375A - A clock synchronization system, method and vehicle electronic equipment based on FPGA - Google Patents
A clock synchronization system, method and vehicle electronic equipment based on FPGA Download PDFInfo
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Abstract
The invention provides a clock synchronization system based on an FPGA (field programmable gate array), which comprises an analog-to-digital converter ADC (analog-to-digital converter) and a phase discriminator, wherein the phase discriminator is used for determining a first phase difference signal between a first local clock and a second local clock of a slave node, the ADC is used for converting the first phase difference signal into a second phase difference signal, the slave node is used for determining time deviation according to the second phase difference signal, a first time stamp sent by a synchronization message from a master node, a second time stamp sent by the synchronization message to the slave node, a third time stamp sent by the slave node and a fourth time stamp sent by the delay request message to the master node, so that the phase discriminator and the ADC are used for determining the phase difference between the master node and the slave node, the determination accuracy of the time deviation can be improved by taking the phase difference into consideration when the time deviation is determined, and the synchronization accuracy between the master node and the slave node is further improved, a specific network and software configuration are not needed, and cost and complexity are reduced.
Description
Technical Field
The present invention relates to the field of clock synchronization networks, and in particular, to a clock synchronization system and method based on an FPGA, and a vehicle electronic device.
Background
The 1588v2 protocol, the IEEE 1588-2008 standard, provides time synchronization accuracy on the sub-microsecond level. This high-precision time synchronization plays an important role in the fields of telecommunications, financial transactions, power systems, industrial automation, and the like.
At present, an IEEE 1588 protocol can be combined with a Beidou satellite navigation system to form an IEEE 1588 Beidou satellite time server. The IEEE 1588 protocol may also make an important contribution in clock synchronization for industrial internet of things. It can be used not only in traditional wired networks, but also in wireless network clock synchronization. The protocol plays an important role in the industrial application fields of WLAN, optical data centers, smart grids and the like.
However, the existing time synchronization schemes have the following typical problems:
1. Complexity and cost implementing high precision time protocol (PTP, precision Time Protocol) may require specific network hardware and software configurations, increasing the complexity and cost of the system.
2. The synchronization precision of the existing scheme is mostly in the sub microsecond and sub nanosecond level, and the synchronization precision is low.
Based on this, a clock synchronization method and system are needed to reduce the complexity and cost of the time synchronization system and improve the synchronization accuracy.
Disclosure of Invention
Aiming at the problems existing in the prior art, the embodiment of the invention provides a clock synchronization system and method based on an FPGA and vehicle electronic equipment, so as to solve or partially solve the technical problems of low synchronization precision and high cost of the clock synchronization system in the prior art.
In a first aspect of the invention, a field programmable gate array (FPGA, field Programmable GATE ARRAY) based clock synchronization system is provided, the system comprising a master node and a slave node, the master node comprising an analog-to-digital converter ADC and a phase discriminator, wherein,
The phase discriminator is used for determining a first phase difference signal between a first local clock of the master node and a second local clock of the slave node, wherein the first phase difference signal is a voltage analog signal;
the analog-to-digital converter ADC is used for converting the first phase difference signal into a second phase difference signal, wherein the second phase difference signal is a voltage digital signal;
The slave node is configured to receive a synchronization message sent by the master node, send a delay request message to the master node, determine a time offset between the first local clock and the second local clock according to the second phase difference signal, a first time stamp sent by the synchronization message from the master node, a second time stamp sent by the synchronization message to the slave node, a third time stamp sent by the delay request message from the slave node, and a fourth time stamp sent by the delay request message to the master node, and adjust the time stamp of the second local clock according to the time offset, so that the slave node and the master node keep synchronous.
In the above scheme, the slave node is specifically configured to:
Determining a true phase difference between the first local clock and the second local clock from the second phase difference signal, a maximum value that the ADC can output, and a maximum phase difference that the phase discriminator can measure;
Determining the real moment when the delay request message reaches the master node according to the real phase difference, the fourth timestamp and the clock period of the second local clock;
And determining the time deviation according to a first time stamp sent by the synchronous message from the master node, a second time stamp when the synchronous message arrives at the slave node, a third time stamp sent by the delay request message from the slave node and the real time when the delay request message arrives at the master node.
In the above scheme, the slave node is specifically configured to:
According to the formula Determining a true phase difference between the first local clock and the second local clock, wherein,
The saidFor the second phase difference signal, theFor the maximum value that the ADC can output, theFor the maximum phase difference measurable by the phase discriminator.
In the above scheme, the slave node is specifically configured to:
According to the formula Determining the real moment when the delay request message reaches the master nodeWherein the saidFor the fourth timestamp, the phase is the true phase difference, and the T is a clock period of the second local clock.
In the above scheme, the phase difference calculating module is specifically configured to:
According to the formula Determining the time offsetWherein, the method comprises the steps of,
The saidFor the first time stamp, theFor the second time stamp, theFor the third timestamp, theAnd the real moment when the delay request message reaches the master node is the real moment.
In the above scheme, the slave node is specifically configured to:
Acquiring a time stamp of the first local clock;
Determining a sum of the time stamp of the first local clock and the time offset as a time stamp of the second local clock.
In a second aspect of the present invention, there is provided an FPGA-based clock synchronization method applied to the FPGA-based clock synchronization system of any one of the first aspect, the method including:
Determining a first phase difference signal between a first local clock of a master node and a second local clock of the slave node by using a phase discriminator, wherein the first phase difference signal is a voltage analog signal;
Converting the first phase difference signal into a second phase difference signal by using an analog-to-digital converter ADC, wherein the second phase difference signal is a voltage digital signal;
and determining the time deviation of the first local clock and the second local clock by using the slave node according to the second phase difference signal, a first time stamp sent by the synchronous message from the master node, a second time stamp sent by the synchronous message to the slave node, a third time stamp sent by the delay request message from the node and a fourth time stamp sent by the delay request message to the master node, and adjusting the time stamp of the second local clock according to the time deviation so as to keep the slave node and the master node synchronous.
In the above solution, the determining, by the slave node, the time offset between the first local clock and the second local clock according to the second phase difference signal, a first time stamp sent by a synchronization message from the master node, a second time stamp when the synchronization message arrives at the slave node, a third time stamp sent by a delay request message from the slave node, and a fourth time stamp when the delay request message arrives at the master node, includes:
Determining a true phase difference between the first local clock and the second local clock from the second phase difference signal, a maximum value that the ADC can output, and a maximum phase difference that the phase discriminator can measure;
Determining the real moment when the delay request message reaches the master node according to the real phase difference, the fourth timestamp and the clock period of the second local clock;
And determining the time deviation according to a first time stamp sent by the synchronous message from the master node, a second time stamp when the synchronous message reaches the slave node, a third time stamp when the slave node sends a response message and the real moment when the delay request message reaches the master node.
In the above solution, the determining the true phase difference between the first local clock and the second local clock according to the second phase difference signal, the maximum value that can be output by the ADC, and the maximum phase difference that can be measured by the phase discriminator includes:
According to the formula Determining a true phase difference between the first local clock and the second local clock, wherein,
The saidFor the second phase difference signal, theFor the maximum value that the ADC can output, theFor the maximum phase difference measurable by the phase discriminator.
A third aspect of the invention provides a vehicle electronic device comprising the FPGA-based clock synchronization system of any of the first aspects.
The invention provides a clock synchronization system, a method and vehicle electronic equipment based on an FPGA (field programmable gate array), which comprises a master node and a slave node, wherein the master node comprises an analog-to-digital converter ADC (analog-to-digital converter) and a phase discriminator, the phase discriminator is used for determining a first phase difference signal between a first local clock of the master node and a second local clock of the slave node, the first phase difference signal is a voltage analog signal, the analog-to-digital converter ADC is used for converting the first phase difference signal into the second phase difference signal, the second phase difference signal is a voltage digital signal, the slave node is used for receiving a synchronous message sent by the master node and sending a delay request message to the master node, according to the second phase difference signal, a first time stamp sent by the synchronous message from the master node, a second time stamp sent by the synchronous message to the slave node, a third time stamp sent by the delay request message from the slave node and a fourth time stamp sent by the delay request message to the master node, the slave node, the accuracy of the phase difference request message can be further improved by the aid of the fact that the phase difference between the first time stamp and the second local clock of the slave node is determined, the time stamp and the slave node can be further improved, and the accuracy of the phase difference between the first time stamp and the slave node can be further improved by determining the phase difference between the first time stamp and the slave node according to the time delay request message, no specific network and associated software configuration is required, thus reducing cost and complexity.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of a master-slave node message exchange process in an IEEE 1588 protocol according to an embodiment of the invention;
FIG. 2 shows a schematic diagram of an FPGA-based clock synchronization system architecture according to one embodiment of the invention;
FIG. 3 illustrates a schematic diagram of a master node according to one embodiment of the invention;
FIG. 4 illustrates a schematic diagram of a slave node according to one embodiment of the invention;
FIG. 5 illustrates a schematic diagram of clock transfer between a master node and a slave node according to one embodiment of the invention;
FIG. 6 illustrates a schematic diagram of a clock relationship between a master node and a slave node according to one embodiment of the invention;
FIG. 7 shows a flow diagram of an FPGA-based clock synchronization method according to one embodiment of the invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In order to better understand the technical solution of the present invention, the IEEE 1588 protocol standard is first introduced. In the 1588 protocol standard, a master node 1 and a slave node 2 are specified, and the master node 1 and the slave node 2 are synchronized based on the IEEE 1588 protocol standard. The 1588 protocol, which is known as the precision clock synchronization protocol standard for network measurement and control systems, basically has the function that all clocks in a distributed network remain synchronized with the most accurate clock, and defines an accurate time protocol PTP (precision Time Protocol). 5 types of PTP messages are defined in the IEEE 1588 protocol, namely a synchronization message (Sync), a Follow-up message (follow_up), a Delay request message (delay_req), a Delay response message (delay_resp) and a Management message (Management).
The first 4 messages are mainly used for time stamp exchange, a specific time stamp exchange process schematic diagram is shown in fig. 1, and a message transceiving flow is as follows:
1. the MASTER node 1 (MASTER) periodically sends out a synchronization Sync message and records the first timestamp of the Sync message leaving the MASTER node 1 ;
2. The master node 1 will first timestampEncapsulated in a follow_up message, sent to SLAVE node 2 (SLAVE);
3. Slave node 2 records a second timestamp of the Sync message reaching slave node 2 ;
4. Issuing a Delay request message delay_req from node 2 and recording a corresponding third timestamp;
5. The master node 1 records a fourth timestamp when the delay_req message arrives at the master node 1;
6. The master node 1 sends out a message carrying a fourth timestampIs a delayed request response message delay_resp to slave node 2.
However, in the message exchange process, when the master node 1 and the slave node 2 are not synchronized, the time stamp of the second local clock of the slave node 2 is offset from the time stamp of the first local clock of the master node 1 by a time offset due to the propagation path. The synchronization process is to calculate the time deviation, so as to adjust the time stamp of the second local clock of the slave node 2 according to the time deviation, thereby achieving the purpose of master-slave node synchronization. The purpose of the time stamp synchronization is to achieve a relative synchronization of the time stamp of the second local clock of the slave node 2 with the time stamp of the first local clock of the master node 1.
Based on this, the invention provides a clock synchronization system based on an FPGA, as shown in fig. 2, the system comprises a master node 1 and a slave node 2, the master node 1 comprises an analog-to-digital converter ADC, a phase discriminator 11 and a first FPGA chip, the slave node 2 comprises a second FPGA chip, wherein,
A phase discriminator 11 for determining a first phase difference signal between a first local clock of a master node 1 and a second local clock of the slave node, the first phase difference signal being a voltage analog signal;
The analog-to-digital converter ADC is used for converting the first phase difference signal into a second phase difference signal, wherein the second phase difference signal is a voltage digital signal;
The slave node 2 is configured to receive a synchronization message sent by the master node, send a delay request message to the master node, determine a time offset between the first local clock and the second local clock according to the second phase difference signal, a first time stamp sent by the master node by the synchronization message, a second time stamp sent by the slave node by the synchronization message, a third time stamp sent by the slave node by the delay request message, and a fourth time stamp sent by the master node by the delay request message, and adjust a time stamp of the second local clock according to the time offset, so that the slave node and the master node keep synchronous.
Specifically, referring to fig. 2, the master node 1 and the slave node 2 may use the same PCB circuit board, each of which is mounted with an FPGA chip, and the master node 1 and the slave node 2 are phase-locked loop (PLL, phase Locked Loop) circuits. When the circuit design is carried out, a jumper device can be arranged on the hardware circuit boards to determine the master-slave relationship of the two hardware circuit boards, so that the master node 1 and the slave node 2 are determined. In order to ensure the symmetry between the links of the master node 1 and the slave node 2, the lengths of the clock transceiving path and the PTP message transceiving path of the PCB should be ensured to be consistent by using a serpentine line.
The master node 1 and the slave node 2 both comprise debugging interfaces Quick USB, and the upper computer can respectively debug and solidify programs of the first FPGA chip and the second FPGA chip through the Quick USB interfaces.
In order to eliminate the frequency drift of the crystal oscillator and the influence of the frequency deviation, the slave node 2 does not use the local crystal oscillator, but directly uses the clock signal transmitted from the master node 1 as the clock of the time stamp. That is, the master node 1 and the slave node 2 use the same source clock.
The first FPGA chip may refer to fig. 3, and includes a master node clock synchronization protocol module 31, a first transmit buffer module 32, a first receive buffer module 33, a first local clock module 34, an a/D control module 35, and a phase measurement control module 36, where,
The master node clock synchronization protocol module 31 is used for controlling the sending and receiving of the message;
The first transmitting buffer module 32 is configured to transmit the communication message in the master node clock synchronization protocol module 31 in a manchester encoding manner;
The first receiving buffer module 33 is configured to decode a corresponding communication packet from the receiving path;
the first local clock module 34 is configured to maintain a first local clock of the master node 1;
the a/D control module 35 is configured to send a signal conversion control instruction to the analog-to-digital converter ADC;
the phase measurement control module 36 is configured to send a phase measurement instruction to the phase discriminator 11.
Specifically, the phase discriminator 11 is provided with two independent input ports, one for receiving the clock signal of the first local clock of the master node 1 and the other for receiving the clock signal of the second local clock of the slave node 2. When the first local clock of the master node 1 is triggered, the phase measurement control module 36 sends a phase measurement instruction to the phase discriminator 11, the phase discriminator 11 detects rising edges or falling edges of the clock signal of the first local clock and the clock signal of the second local clock, when the edge of the first local clock arrives, if the edge of the second local clock immediately follows the first local clock, the phase deviation is considered to be smaller, and if the edge of the second local clock is considered to be advanced or delayed relative to the edge of the first local clock, the phase deviation is considered to be larger, and at this time, the first phase difference signal is output, and at this time, the first phase difference signal is a voltage analog signal.
The a/D control module 35 then sends a signal conversion control instruction to the analog-to-digital converter ADC, which converts the first phase difference signal into a second phase difference signal based on the signal conversion control instruction, the second phase difference signal being a voltage digital signal. That is, the ADC is used to convert an analog signal into a voltage digital signal.
The structure of the second FPGA chip may refer to fig. 4, and the second FPGA chip includes a slave node clock synchronization protocol module 41, a second transmit buffer module 42, a second receive buffer module 43, and a second local clock module 44, where,
The slave node clock synchronization protocol module 41 is used for controlling the sending and receiving of the message;
the second transmitting buffer module 42 is configured to transmit the communication packet in the slave node clock synchronization protocol module 41 in a manchester encoding manner;
the second receiving buffer module 43 is configured to decode a corresponding communication packet from the receiving path;
the second local clock module 44 is configured to maintain a second local clock of the slave node 2.
The second FPGA chip further comprises a phase difference calculation module 45 and a time offset calculation module 46, wherein,
A phase difference calculation module 45 for determining a true phase difference between the first local clock and the second local clock based on the second phase difference signal, the maximum value that the ADC can output, and the maximum phase difference that the phase discriminator 11 can measure;
the time deviation calculating module 46 is configured to determine a real time when the delay request packet arrives at the master node 1 according to the real phase difference, the fourth timestamp and the clock period of the second local clock;
The time deviation is determined according to a first time stamp sent by the synchronous message from the master node 1, a second time stamp of the synchronous message reaching the slave node 2, a third time stamp of the delay request message sent by the slave node 2 and the real moment of the delay request message reaching the master node 1.
Further, referring to fig. 5, in fig. 5, clk1 is a crystal oscillator clock of the master node, so when a message is sent out from the transmitting end Tx1 of the master node 1 and reaches the receiving end Rx2 of the slave node 2, the clock of the slave node 2 should be a Clk2 clock, and a phase difference is generated between Clk2 and Clk1 due to a propagation path with a certain distance between the master node 1 and the slave node 2.
After the slave node 2 feeds back the message to the receiving end Rx1 of the master node 1 via the transmitting end Tx2 under the Clk2 clock, a Clk3 clock is generated. A phase difference is again created between Clk3 and Clk2. The schematic waveforms of Clk1, clk2 and Clk3 can be referred to fig. 6. Referring to fig. 2, master_clk in fig. 2 includes Clk1 and Clk3, and slave_clk includes Clk2.
In fig. 6, it can be seen that there is a Phase difference Phase between Clk1 and Clk 3.
Mapping into FIG. 1, for the first timestampIn the sense that it is possible to provide,Refers to the moment when the synchronous message is sent out from the master node 1, the trigger clock is Clk1, and the timestamp clock is the first local clock Clk1 of the master node 1, thusIs accurate. For the second time stampIn the sense that it is possible to provide,Is the time when the synchronous message arrives at the slave node 2, the trigger clock is Clk2, and the timestamp clock is the second local clock Clk2 of the slave node 2, thusIs accurate. For the third timestampIn the sense that it is possible to provide,Is the time when the delay request message is sent out from the node 2, the trigger clock is Clk2, and the timestamp clock is the second local clock Clk2 of the node 2, soIs accurate. For the fourth timestampIn the sense that it is possible to provide,Is the time when the delayed request message reaches the master node 1, the trigger clock is Clk3, and the timestamp clock is the first local clock Clk1 of the master node 1, thusIs error-prone.
As can be seen from fig. 6, the real time instantShould be atBefore arriving. Therefore, in order to ensure that the master node 1 and the slave node 2 achieve accurate synchronization, it is necessary to eliminate the influence of the phase difference between the first local clock and the second local clock on the synchronization accuracy. Then in one embodiment, the phase difference calculation module 45 is specifically configured to:
According to the formula Determining a true phase difference phase between the first local clock and the second local clock, wherein,
As a second phase difference signal,Is the maximum value that can be output by the ADC,Is the maximum phase difference measurable by the phase discriminator.
The maximum value that the ADC can output needs to be determined according to the resolution of the ADC, for example, if the resolution of the ADC is 12 bits, the maximum value that the ADC can output is 4096. The maximum phase difference measurable by the phase discriminator 11 is typicallyRadians or 360 degrees.
After the true phase difference is determined, the phase difference calculation module 45 is further configured to:
According to the formula Determining the real moment when the delay request message reaches the master node 1Wherein, the method comprises the steps of,For the fourth timestamp, phase is the true phase difference, and T is the clock period of the second local clock.
Real moment when delay request message reaches master node 1After the determination, the phase difference calculation module 45 is further configured to:
According to the formula Determining time biasWherein, the method comprises the steps of,
As a result of the first time stamp,As a result of the second time stamp,As a result of the third time stamp,The real moment when the delay request message reaches the master node 1.
After the time offset is determined, the slave node 2 may update the timestamp of the second local clock according to the time offset, including:
Acquiring a time stamp of a first local clock;
the sum of the time stamp and the time offset of the first local clock is determined as the time stamp of the second local clock.
The phase discriminator and the ADC are utilized to determine the phase difference between the master node and the slave node, and the phase difference is taken into consideration when the time deviation is determined, so that the time deviation determination precision can be improved, the precision can reach the nano second level, and the synchronization precision between the master node and the slave node is further improved.
Based on the same inventive concept as the previous embodiment, the present invention further provides an FPGA-based clock synchronization method, which is applied to the above mentioned FPGA-based clock synchronization system, as shown in fig. 7, and the method includes the following steps:
S710, determining a first phase difference signal between a first local clock of a master node and a second local clock of a slave node by using a phase discriminator, wherein the first phase difference signal is a voltage analog signal.
The phase discriminator is provided with two independent input ports, one for receiving the clock signal of the first local clock of the master node and the other for receiving the clock signal of the second local clock of the slave node. When the first local clock of the master node is triggered, the phase measurement control module sends a phase measurement instruction to the phase discriminator, the phase discriminator detects rising edges or falling edges of clock signals of the first local clock and clock signals of the second local clock, when the edges of the first local clock come, if the edges of the second local clock immediately follow the first local clock, the phase deviation is considered to be smaller, and if the edges of the second local clock are advanced or delayed relative to the edges of the first local clock, the phase deviation is considered to be larger, and at the moment, the first phase difference signal is output, and at the moment, the first phase difference signal is a voltage analog signal.
S711, converting the first phase difference signal into a second phase difference signal by using an ADC, wherein the second phase difference signal is a voltage digital signal.
And then the A/D control module sends a signal conversion control instruction to the analog-to-digital converter ADC, and the ADC converts the first phase difference signal into a second phase difference signal based on the signal conversion control instruction, wherein the second phase difference signal is a voltage digital signal. That is, the ADC is used to convert an analog signal into a voltage digital signal.
And S712, determining the time deviation of the first local clock and the second local clock by using the slave node according to the second phase difference signal, a first time stamp sent by the synchronous message from the master node, a second time stamp sent by the synchronous message to the slave node, a third time stamp sent by the delay request message from the slave node and a fourth time stamp sent by the delay request message to the master node, and adjusting the time stamp of the second local clock according to the time deviation so as to keep the slave node and the master node synchronous.
After the master node acquires the second phase difference signal fed back by the ADC, the second phase difference signal is sent to the slave node, and the slave node can determine the time deviation of the first local clock and the second local clock according to the second phase difference signal, the first time stamp sent by the synchronous message from the master node, the second time stamp sent by the synchronous message to the slave node, the third time stamp sent by the slave node to delay the request message and the fourth time stamp sent by the delay request message to the master node.
In one embodiment, determining the time offset of the first local clock and the second local clock by the slave node according to the second phase difference signal, a first time stamp of the synchronization message sent from the master node, a second time stamp of the synchronization message arriving at the slave node, a third time stamp of the response message sent from the slave node, and a fourth time stamp of the delay request message arriving at the master node, includes:
Determining a true phase difference between the first local clock and the second local clock based on the second phase difference signal, the maximum value that the ADC can output, and the maximum phase difference that the phase discriminator can measure;
Determining the real moment when the delay request message reaches the master node according to the real phase difference, the fourth time stamp and the clock period of the second local clock;
And determining the time deviation according to the first time stamp sent by the synchronous message from the master node, the second time stamp of the synchronous message reaching the slave node, the third time stamp of the response message sent by the slave node and the real time when the delay request message reaches the master node.
In one embodiment, determining the true phase difference between the first local clock and the second local clock from the second phase difference signal, the maximum value that the ADC can output, and the maximum phase difference that the phase discriminator can measure, comprises:
According to the formula Determining a true phase difference phase between the first local clock and the second local clock, wherein,
As a second phase difference signal,Is the maximum value that can be output by the ADC,Is the maximum phase difference measurable by the phase discriminator.
In one embodiment, determining the actual time when the delayed request message arrives at the master node according to the actual phase difference, the fourth timestamp and the clock period of the second local clock includes:
According to the formula Determining real time when delay request message reaches master nodeWherein, the method comprises the steps of,For the fourth timestamp, phase is the true phase difference, and T is the clock period of the second local clock.
In one embodiment, determining the time offset according to a first time stamp sent by the synchronization message from the master node, a second time stamp of the synchronization message reaching the slave node, a third time stamp of the response message sent by the slave node, and a real time of the delay request message reaching the master node includes:
According to the formula Determining time biasWherein, the method comprises the steps of,
As a result of the first time stamp,As a result of the second time stamp,As a result of the third time stamp,The real moment when the delay request message reaches the master node.
In one embodiment, after the time offset is determined, the method further comprises:
Acquiring a time stamp of a first local clock;
the sum of the time stamp and the time offset of the first local clock is determined as the time stamp of the second local clock.
The invention also provides a vehicle electronic device, which comprises the FPGA-based clock synchronization system, and the specific structure and the implementation principle of the system can be correspondingly described with reference to the above, so that the description is omitted here.
Through one or more embodiments of the present invention, the present invention has the following benefits or advantages:
The invention provides a clock synchronization system, a clock synchronization method and vehicle electronic equipment based on an FPGA (field programmable gate array), wherein the system comprises a master node and a slave node, the master node comprises an analog-to-digital converter ADC (analog-to-digital converter) and a phase discriminator, the phase discriminator is used for determining a first phase difference signal between a first local clock of the master node and a second local clock of the slave node, the first phase difference signal is a voltage analog signal, the analog-to-digital converter ADC is used for converting the first phase difference signal into the second phase difference signal, the second phase difference signal is a voltage digital signal, the slave node is used for receiving a synchronous message sent by the master node and sending a delay request message to the master node, and according to the second phase difference signal, a first time stamp sent by the synchronous message from the master node, a second time stamp sent by the synchronous message to the slave node, a third time stamp sent by the delay request message from the slave node and a fourth time stamp sent by the delay request message to the slave node, the slave node and the second time stamp sent by the delay request message to the slave node are determined, and the slave node and the second time stamp is kept to be different from the master node to the local clock. Therefore, the phase difference between the master node and the slave node is determined by the phase discriminator and the ADC, and the phase difference is taken into consideration when the time deviation is determined, so that the determination accuracy of the time deviation can be improved, the accuracy can reach the nano second level, and the synchronization accuracy between the master node and the slave node is further improved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
The above description is not intended to limit the scope of the invention, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the invention.
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