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CN119252189A - Display Panel - Google Patents

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Publication number
CN119252189A
CN119252189A CN202310810718.6A CN202310810718A CN119252189A CN 119252189 A CN119252189 A CN 119252189A CN 202310810718 A CN202310810718 A CN 202310810718A CN 119252189 A CN119252189 A CN 119252189A
Authority
CN
China
Prior art keywords
transistor
signal
drain
source
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310810718.6A
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Chinese (zh)
Inventor
孙飞翔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN202310810718.6A priority Critical patent/CN119252189A/en
Priority to PCT/CN2023/134006 priority patent/WO2025007480A1/en
Publication of CN119252189A publication Critical patent/CN119252189A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请提供一种显示面板，包括：多个级联的栅极驱动单元以及像素驱动电路。栅极驱动单元包括：输入控制模块，用于在显示扫描时段输出驱动信号；补偿侦测控制模块，用于在扫描空白时段输出补偿侦测驱动信号；以及输出模块，与输入控制模块以及补偿侦测控制模块连接，用于在显示扫描时段响应于驱动信号以输出显示扫描信号，并在扫描空白时段响应于补偿侦测驱动信号以输出补偿侦测扫描信号；像素驱动电路与栅极驱动单元连接，用于在显示扫描时段接收显示扫描信号，并在扫描空白时段接收补偿侦测扫描信号。

The present application provides a display panel, comprising: a plurality of cascaded gate drive units and a pixel drive circuit. The gate drive unit comprises: an input control module, which is used to output a drive signal during a display scan period; a compensation detection control module, which is used to output a compensation detection drive signal during a scan blank period; and an output module, which is connected to the input control module and the compensation detection control module, and is used to respond to the drive signal during the display scan period to output a display scan signal, and respond to the compensation detection drive signal during the scan blank period to output a compensation detection scan signal; the pixel drive circuit is connected to the gate drive unit, and is used to receive a display scan signal during the display scan period, and receive a compensation detection scan signal during the scan blank period.

Description

Display panel
Technical Field
The application relates to the technical field of display, in particular to a display panel.
Background
Currently, display panels are widely used in different fields, such as intelligent mobile terminals, notebooks, and augmented reality displays. However, the display panel has a problem in that display brightness is not uniform during display.
Therefore, how to improve the brightness unevenness of the display panel is a technical problem to be solved.
Disclosure of Invention
The application aims to provide a display panel so as to solve the problem of uneven brightness display of the display panel.
In a first aspect, the present application provides a display panel, a frame time of which includes a display scan period and a scan blank period, the display panel comprising:
A plurality of cascaded gate driving units, the gate driving units comprising:
An input control module for outputting a driving signal during the display scan period;
a compensation detection control module for outputting a compensation detection driving signal during the scanning blank period, and
An output module connected with the input control module and the compensation detection control module for responding to the driving signal to output a display scanning signal in the display scanning period and responding to the compensation detection driving signal in the scanning blank period to output a compensation detection scanning signal, and
And the pixel driving circuit is connected with the grid driving unit and is used for receiving the display scanning signal in the display scanning period and receiving the compensation detection scanning signal in the scanning blank period.
The application has the beneficial effects that as the compensation detection control module is additionally arranged, the output module is connected with the input control module and the compensation detection control module. The output module responds to the driving signal to output a display scanning signal in a display scanning period, and responds to the compensation detection driving signal to output a compensation detection scanning signal in a scanning blank period. The pixel driving circuit is used for receiving a display scanning signal in a display scanning period and receiving a compensation detection scanning signal in a scanning blank period. With this design, the pixel driving circuit receives the display scan signal to provide conditions for the display panel to display, and receives the compensation detection scan signal to provide conditions for the random compensation detection during the blanking period. The compensation of the pixel driving circuit is realized while the display is realized in one frame time, so that the problem of uneven brightness display of the display panel in the display process is solved.
Drawings
FIG. 1 is a schematic diagram of a display panel according to some embodiments of the present application;
FIG. 2 is a schematic diagram of a pixel driving circuit according to some embodiments of the present application;
FIG. 3 is a schematic diagram of a gate driving circuit according to some embodiments of the present application;
FIG. 4 is a circuit diagram of a (3 n-1) th stage gate driving unit GOA (3 n-1) according to some embodiments of the present application;
fig. 5 is a driving timing diagram of a gate driving circuit according to some embodiments of the application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
Referring to fig. 1 to 5, fig. 1 is a schematic diagram of a display panel according to some embodiments of the present application, fig. 2 is a schematic diagram of a pixel driving circuit according to some embodiments of the present application, fig. 3 is a schematic diagram of a gate driving circuit according to some embodiments of the present application, fig. 4 is a circuit schematic diagram of a (3 n-1) -th stage gate driving unit GOA (3 n-1) according to some embodiments of the present application, and fig. 5 is a driving timing diagram of the gate driving circuit according to some embodiments of the present application.
The display panel 100 is an organic light emitting diode display panel, but the display panel 100 is not limited thereto, and may be a liquid crystal display panel, a micro light emitting diode display panel, a sub-millimeter light emitting diode display panel, or a quantum dot display panel.
Referring to fig. 1, the display panel 100 includes a display area 100a and a non-display area 100b disposed around the display area 100 a. The display panel 100 includes a pixel driving circuit 200 located in the display area 100a, and the pixel driving circuit 200 is connected to the data signal line DL and the scanning signal line GL.
The display panel 100 further includes a gate driving circuit 20, and the gate driving circuit 20 is disposed in the non-display area 100b. The gate driving circuit 20 includes a first gate driving circuit 201 and a second gate driving circuit 202, and the first gate driving circuit 201 and the second gate driving circuit 202 are respectively located at opposite sides of the display area 100 a.
It is understood that the gate driving circuit 20 may be located at only one side of the display area 100a. At least a portion of the gate driving circuit 20 may also be disposed in the display region 100a.
Referring to fig. 2, the pixel driving circuit 200 includes a data writing transistor K1, a driving transistor DT, a compensation control transistor K2, and a storage capacitor Cst.
Wherein the driving transistor DT includes an N-type transistor. The data writing transistor K1 and the compensation control transistor K2 comprise P-type transistors, so that the size of the data writing transistor K1 and the size of the compensation control transistor K2 are reduced conveniently, the charging requirement of the data writing transistor K1 is met, and the display panel is convenient to realize high-frequency driving. In addition, the sizes of the data writing transistor K1 and the compensation control transistor K2 are reduced, so that the occupied area of the pixel driving circuit is reduced, the number of the pixel driving circuit and the number of pixels are increased, and the requirement of the display panel for realizing high-resolution display is met.
It is understood that the data writing transistor K1 and the compensation control transistor K2 may also include N-type transistors. In the case where the data writing transistor K1 and the compensation control transistor K2 each include an N-type transistor, since the charging current of the N-type transistor is small, the charging time for the N-type transistor needs to be increased, and the increase in the charging time causes a limitation to an increase in the driving frequency of the display panel. In addition, in order to achieve a better charging effect on the N-type transistor, it is necessary to increase the ratio of the channel width to the channel length of the N-type transistor, and the increase in the ratio causes a limitation in increasing the resolution of the display panel.
The gate of the data writing transistor K1 is connected to the scanning signal line GL, one of the source and the drain of the data writing transistor K1 is connected to the data signal line DL, and the other of the source and the drain of the data writing transistor K1 is connected to the gate of the driving transistor DT.
One of the source and the drain of the driving transistor DT receives the first power signal VDD, and the other of the source and the drain of the driving transistor DT receives the second power signal VSS. The first power signal VDD is a high level signal, and the second power signal VSS is a low level signal.
The gate of the compensation control transistor K2 is connected to a compensation control signal line (not shown) located in the display area 100a, one of the source and the drain of the compensation control transistor K2 is connected to the other of the source and the drain of the driving transistor DT and receives the second power signal VSS, and the other of the source and the drain of the compensation control transistor K2 is connected to the detection chip 30.
The storage capacitor Cst is connected between the other of the source and the drain of the data writing transistor K1 and the other of the source and the drain of the driving transistor DT.
The light emitting device OLED is connected between the other of the source and the drain of the driving transistor DT and the second power source signal VSS.
Referring to fig. 3, the gate driving circuit 20 includes a plurality of gate driving units. The plurality of gate driving units include a first stage gate driving unit GOA (1), a second stage gate driving unit GOA (2), a third stage gate driving unit GOA (3), and a (3 n-1) th stage gate driving unit GOA (3 n-1), where n is an integer greater than or equal to 2.
The plurality of gate driving units are cascaded. Each stage of gate driving unit outputs a stage signal to the gate driving unit of the lower stage. Specifically, the first stage gate driving unit GOA (1) receives the start signal STV and outputs the first stage transmission signal ST (1) to the second stage gate driving unit GOA (2). The second stage gate driving unit GOA (2) receives the first stage pass signal ST (1) and outputs a second stage pass signal ST (2). The third stage gate driving unit GOA (3) receives the second stage transmission signal ST (2) and outputs a third stage transmission signal ST (3). The (3 n-1) th stage gate driving unit GOA (3 n-1) receives the (3 n-2) th stage transmission signal ST (3 n-2) and outputs the (3 n-1) th stage transmission signal ST (3 n-1).
Each stage of gate driving units is connected to the first clock signal line CKL1 to receive the first clock signal CK1. Each stage of gate driving units is connected to the second clock signal line CKL2 to receive the second clock signal CK2. Each stage of gate driving units is connected to a Reset signal line Reset to receive an output control signal RE. Each stage of gate driving units is connected to the switching control signal line CKBL for receiving the switching control signal CKB. Each stage of gate driving units is connected to the first level signal line VL to receive a first level VGL, which is a low level signal. Each stage of gate driving units is connected to the second level signal line VL to receive the second level VGH, which is a high level signal. The (3 n-2) -th stage gate driving unit (not shown) is connected to the first compensation detection selection signal line LSPL to receive the first compensation detection selection signal LP1, for example, the first stage gate driving unit GOA (1) receives the first compensation detection selection signal LP1. The (3 n-1) -th stage gate driving unit GOA (3 n-1) is connected to the second compensation detection selection signal line LSPL to receive the second compensation detection selection signal LP2, e.g., the second stage gate driving unit GOA (2) receives the second compensation detection selection signal LP2. The (3 n) -th stage gate driving unit (not shown) is connected to the third compensation detection selection signal line LSPL to receive the third compensation detection selection signal LP3, for example, the third stage gate driving unit GOA (3) receives the third compensation detection selection signal LP3.
The output terminal of the first stage gate driving unit GOA (1) is connected to the first scanning signal line GL 1. The output terminal of the second stage gate driving unit GOA (2) is connected to the second scanning signal line GL 2. An output terminal of the third stage gate driving unit GOA (3) is connected to the third scanning signal line GL 3. The output terminal of the (3 n-1) th stage gate driving unit GOA (3 n-1) is connected to the (3 n-1) th scanning signal line GL (3 n-1).
Referring to fig. 5, a frame time of the display panel 100 includes a display scan period S1 and a scan blank period S2, and the scan blank period S2 is located between the display scan periods S1 of two adjacent frames. For example, when the refresh rate of the display panel 100 is 120Hz, the frame time is 8.3ms, the time corresponding to the display scan period S1 is 8ms, and the time corresponding to the scan blank period S2 is 0.3ms.
In the display scanning period S1, the gate driving circuit 20 sequentially outputs the display scanning signal WR1 to the multi-row pixel driving circuit 200. The data writing transistor K1 is turned on in response to the display scanning signal WR1, and stores the display data signal transmitted by the data signal line DL in the storage capacitor Cst for display.
In the scanning blank period S2, one gate driving unit GOA of all the gate driving units in the gate driving circuit 20 is randomly controlled to output the compensation detection scanning signal WR2. The data writing transistor K1 receiving the compensation detection scanning signal WR2 is turned on in response to the compensation detection scanning signal WR2, the compensation control transistor K2 is also turned on, and the detection chip 30 detects an initial threshold voltage of the driving transistor DT. After the detection of the initial threshold voltage is completed, the initial threshold voltage of the driving transistor DT is externally compensated, so that the display panel has a problem of uneven brightness display in the display process.
Therefore, the gate driving circuit 20 is used for outputting the display scanning signal WR1 in the display scanning period S1, and can also randomly control one gate driving unit GOA in the gate driving circuit 20 to output the compensation detection scanning signal WR2 in the scanning blank period S2 so as to detect the initial threshold voltage of the driving transistor DT, which is beneficial to realizing display in one frame time and simultaneously facilitating external compensation of the driving voltage of the driving transistor DT, thereby improving the problem of uneven brightness display of the display panel in the display process.
In addition, since the data writing transistor K1 is a P-type transistor, the data writing transistor K1 is turned on when the display scanning signal WR1 and the compensation detection scanning signal WR2 are both low level signals.
The following describes the display scan signal WR1 (3 n-1) and the compensation detection scan signal WR2 (3 n-1) of the (3 n-1) th stage gate driving unit GOA (3 n-1) outputting the low level. The other gate driving units GOA in the gate driving circuit 20 can be analogized, and the present application will not be described in detail.
Referring to fig. 4, the (3 n-1) th gate driving unit GOA (3 n-1) includes an input control module 11, a level transmission module 12, a compensation detection control module 13, an output module 14, a switching module 15, and a pull-down module 18.
The input control module 11 is configured to output driving signals including a first driving signal P and a second driving signal D during the display scan period S1.
Specifically, the input control module 11 includes a thirteenth transistor T3 and a fourteenth transistor T4. The gate of the thirteenth transistor T3 receives the first clock signal CK1, one of the source and the drain of the thirteenth transistor T3 receives the pre-stage transfer signal ST (3 n-2), and the other of the source and the drain of the thirteenth transistor T3 outputs the second driving signal D. The gate of the fourteenth transistor T4 receives the first clock signal CK1, one of the source and the drain of the fourteenth transistor T4 receives the first level VGL, and the other of the source and the drain of the fourteenth transistor T4 outputs the first driving signal P.
Among them, the previous stage transmission signal ST (3 n-2) is a stage transmission signal outputted from the gate driving unit of the (3 n-2) th stage, but is not limited thereto. When n is equal to 1, one of the source and the drain of the thirteenth transistor T3 receives the start signal STV.
The cascade module 12 is connected with the input control module 11. The gradation module 12 is for outputting the present gradation signal ST (3 n-1) in response to the driving signal in the display scan period S1. The present level transmission signal ST (3 n-1) includes a high level present level transmission signal and a low level present level transmission signal smaller than the high level present level transmission signal.
The cascode module 12 includes a fourth transistor T10 and a fifth transistor T9. The gate of the fourth transistor T10 receives the first driving signal P, and one of the source and the drain of the fourth transistor T10 receives the second level VGH. The gate of the fifth transistor T9 receives the second driving signal D, and one of the source and the drain of the fifth transistor T9 receives the first level VGL. The other of the source and the drain of the fifth transistor T9 is connected to the other of the source and the drain of the fourth transistor T10. Wherein the other of the source and the drain of the fourth transistor T10 outputs a high level present level signaling. The other of the source and the drain of the fifth transistor T9 outputs a low-level current-level hierarchical signal.
Accordingly, the cascode module 12 selectively outputs one of the second level VGH and the first level VGL according to the second driving signal D and the first driving signal P. The level transmission module 12 outputs the second level VGH as a high level current level transmission signal according to the first driving signal P. The level transmission module 12 outputs the first level VGL as a low level current level transmission signal according to the second driving signal D.
The gate driving unit GOA (3 n-1) of the (3 n-1) th stage further includes a third capacitor C3, where the third capacitor C3 is used to stabilize the voltage value of the first driving signal P, so as to ensure that the other of the source and the drain of the fourth transistor T10 can stably output the high-level current stage signal.
The first electrode of the third capacitor C3 receives the first driving signal P, and the second electrode of the third capacitor C3 receives the second level VGH. Specifically, the third capacitor C3 is connected between the gate of the fourth transistor T10 and the second level VGH.
The compensation detection control module 13 is configured to output a compensation detection driving signal during the scanning blank period S2. Specifically, the compensation detection control module 13 includes a detection selection circuit 131 and a detection control circuit 132.
The detection selection circuit 131 is configured to output a detection selection control signal in response to the pre-gradation signal ST (3 n-2) and the compensation detection selection signal in the display scan period S1.
Further, the pre-stage transmission signal ST (3 n-2) includes a low-level pre-stage transmission signal and a high-level pre-stage transmission signal larger than the low-level pre-stage transmission signal. The detection selection circuit 131 is used for responding to the low-level pre-stage transmission signal and the low-level compensation detection selection signal in the display scanning period S1 to output a detection selection control signal.
Specifically, the detection selection circuit 131 includes a first transistor T18. In the display scan period S1, the gate of the first transistor T18 receives the compensation detection selection signal. For example, for the (3 n-1) th stage gate driving unit GOA (3 n-1), the gate of the first transistor T18 receives the second compensation detection selection signal LP2. One of the source and the drain of the first transistor T18 receives the pre-stage pass signal ST (3 n-2), and the other of the source and the drain of the first transistor T18 outputs the detection selection control signal M.
When the pre-stage signal ST (3 n-2) is at a low level, the second compensation detection selection signal LP2 is also controlled to be at a low level, so that the first transistor T18 outputs a detection selection control signal at a low level.
It should be noted that, for the second stage gate driving unit GOA (2), the first transistor T18 also receives the second compensation detection selection signal LP2. For the first stage gate driving unit GOA (1) and the (3 n-2) th stage gate driving unit, the first transistor T18 receives the first compensation detection selection signal LP1. For the third stage gate driving unit GOA (3) and the (3 n) th stage gate driving unit, the first transistor T18 receives the third compensation detection selection signal LP3. Therefore, the adjacent three-stage gate driving units GOA respectively receive the first, second and third compensating detection selection signals LP1, LP2 and LP3, but are not limited thereto.
The detection control circuit 132 is connected to the detection selection circuit 131 and the output module 14. The detection control circuit 132 is configured to output a compensation detection driving signal in response to the detection selection control signal and the output control signal RE in the scanning blank period S2.
Specifically, the detection control circuit 132 includes a second transistor T19, a first capacitor C4, and a third transistor T20.
In the display scan period S1, the gate of the second transistor T19 receives the detection selection control signal, and one of the source and the drain of the second transistor receives the first level VGL.
The first capacitor C4 is used for storing the detection selection control signal M output by the detection selection circuit 131 in the display scan period S1. In the display scan period S1, the first electrode of the first capacitor C4 receives the detection selection control signal M, and the second electrode of the first capacitor C4 receives the first level VGL.
Specifically, the first capacitor C4 is connected to the gate of the second transistor T19 and one of the source and the drain of the second transistor T19.
One of a source and a drain of the third transistor T20 is connected to the other of the source and the drain of the second transistor T19. In the scan blank period S2, the gate of the third transistor T20 receives the output control signal RE, and the other of the source and the drain of the third transistor outputs the compensation detection driving signal.
The output module 14 is connected with the input control module 11 and the compensation detection control module 13. The output module 14 is used for responding to the driving signal to output the display scanning signal WR1 (3 n-1) in the display scanning period S1 and responding to the compensation detection driving signal to output the compensation detection scanning signal WR2 (3 n-1) in the scanning blank period S2.
Wherein the display scan signal WR1 (3 n-1) includes an active display scan signal and an inactive display scan signal. The data writing transistor K1 is turned on after receiving the valid display scan signal, and the data writing transistor K1 is turned off after receiving the invalid display scan signal.
The output module 14 includes a sixth transistor T24 and a seventh transistor T25. In the display scan period S1, the gate of the sixth transistor T24 receives the first driving signal P, one of the source and the drain of the sixth transistor T24 receives the second level VGH, and the other of the source and the drain of the sixth transistor T24 outputs the inactive display scan signal. In the display scan period S1, the gate of the seventh transistor T25 receives the second driving signal D, one of the source and the drain of the seventh transistor T25 receives the first level VGL, and the other of the source and the drain of the seventh transistor T25 outputs an effective display scan signal.
Since the second level VGH is a high level, the inactive-display scan signal is a high level signal. The first level VGL is a low level, and the effective display scan signal is a low level signal.
In the scan blank period S2, the seventh transistor T25 receives the compensation detection driving signal, one of the source and the drain of the seventh transistor T25 receives the first level VGL, and the other of the source and the drain of the seventh transistor T25 outputs the compensation detection scanning signal WR2 (3 n-1). Since the first level VGL is a low level signal, the offset detection scanning signal WR2 (3 n-1) is also a low level signal.
In some embodiments, the (3 n-1) th stage gate driving unit GOA (3 n-1) further includes a fifth capacitor C5, the fifth capacitor C5 being used to stabilize the voltage value of the first driving signal P. The first electrode of the fifth capacitor C5 receives the first driving signal P, and the second electrode of the fifth capacitor C5 receives the second level VGH.
Specifically, the fifth capacitor C5 is connected between the second level VGH and the gate of the sixth transistor T24.
In some embodiments, the (3 n-1) th stage gate driving unit GOA (3 n-1) further includes a switching module 15 connected between the input control module 11 and the output module 14. The switching module 15 is configured to connect the input control module 11 and the output module 14 during the display scan period S1, and is configured to disconnect the input control module 11 and the output module 14 during the scan blanking period S2.
The switching module 15 includes an eleventh transistor T22 and a twelfth transistor T21. The gate of the eleventh transistor T22 receives the switching control signal CKB, and the source and the drain of the eleventh transistor T22 are connected between the gate of the sixth transistor T24 and the input control module 11. The gate of the twelfth transistor T21 receives the switching control signal CKB, and the source and the drain of the twelfth transistor T21 are connected between the gate of the seventh transistor T25 and the input control module 11. The eleventh transistor T22 is turned on and transmits the first driving signal P in the display scan period S1, and is turned off in the scan blank period S2. The twelfth transistor T21 is turned on and transmits the second driving signal D in the display scan period S1 and is turned off in the scan blank period S2.
Specifically, the gate of the eleventh transistor T22 receives the switching control signal CKB, one of the source and the drain of the eleventh transistor T22 is connected to the other of the source and the drain of the fourteenth transistor T4, and the other of the source and the drain of the eleventh transistor T22 is connected to the gate of the sixth transistor T24. The gate of the twelfth transistor T21 receives the switching control signal CKB, one of the source and the drain of the twelfth transistor T21 is connected to the other of the source and the drain of the thirteenth transistor T3, and the other of the source and the drain of the twelfth transistor T21 is connected to the gate of the seventh transistor T25 and the other of the source and the drain of the third transistor T20.
In some embodiments, the (3 n-1) th stage gate driving unit GOA (3 n-1) further includes a first feedback module 21 and a pull-down module 18 connected to the first feedback module 21. The first feedback module 21 receives the first driving signal P and outputs a feedback signal. The pull-down module 18 receives the feedback signal and outputs a pull-down signal Q1 to pull down the second driving signal D.
The pull-down module 18 includes an eighth transistor T16. In the display scan period S1, one of the gate of the eighth transistor T16 and the source and drain of the eighth transistor T16 receives the feedback signal, the other of the source and drain of the eighth transistor T16 outputs the pull-down signal Q1 to the gate of the seventh transistor T25, and the pull-down signal Q1 pulls down the second driving signal D to ensure that the seventh transistor T25 stably outputs the effective display scan signal in the display scan period S1.
The pull-down module 18 further includes a fifteenth transistor T14 and a sixteenth transistor T15. The gate of the fifteenth transistor T14 receives the first clock signal CK1, and one of the source and the drain of the fifteenth transistor T14 receives the pre-stage transmission signal ST (3 n-2). The gate of the sixteenth transistor T15 receives the first level VGL, and the source and the drain of the fifteenth transistor T14 are connected between the other of the source and the drain of the fifteenth transistor T14 and the gate of the eighth transistor T16.
The first feedback module 21 includes a ninth transistor T1, a tenth transistor T2, and a second capacitor C1. In the display scan period S1, the gate of the ninth transistor T1 receives the first driving signal P, and one of the source and the drain of the ninth transistor T1 receives the second level VGH. In the display scan period S1, one of the source and the drain of the tenth transistor T2 receives the second clock signal CK2. The first electrode of the second capacitor C1 is connected to the other of the source and the drain of the ninth transistor T1 and the other of the source and the drain of the tenth transistor T2. The second electrode of the second capacitor C1 is connected to the gate of the tenth transistor T2 and the gate of the eighth transistor T16.
The (3 n-1) -th stage gate driving unit GOA (3 n-1) further comprises a second feedback module 22, wherein the second feedback module 22 receives the first driving signal P, the second driving signal D and the first clock signal CK1. In the display scan period S1, the potentials of the second feedback module 22 for controlling the first driving signal P and the second driving signal are opposite.
Specifically, the second feedback module 22 includes a seventeenth transistor T51 and an eighteenth transistor T52. Gates of the seventeenth transistor T51 and the eighteenth transistor T52 receive the second driving signal D. One of the source and the drain of the eighteenth transistor T52 receives the first clock signal CK1, one of the source and the drain of the eighteenth transistor T52 is connected to one of the source and the drain of the seventeenth transistor T51, and the other of the source and the drain of the seventeenth transistor T51 receives the first driving signal P1.
The (3 n-1) th stage gate driving unit GOA (3 n-1) further includes a third feedback module 26, and the third feedback module 26 receives the second driving signal D, the first driving signal P, and the second level VGH. The third feedback module 26 is configured to pull up the first driving signal P according to the second driving signal D. The third feedback module 26 includes a nineteenth transistor T8, a gate of the nineteenth transistor T8 receiving the second driving signal D, one of a source and a drain of the nineteenth transistor T8 receiving the second level VGH, and the other of the source and the drain of the nineteenth transistor T8 receiving the first driving signal P.
The (3 n-1) -th stage gate driving unit GOA (3 n-1) further includes a fourth feedback module 16, and the fourth feedback module 16 receives the second driving signal D, the first driving signal P, and the second level VGH. The fourth feedback module 16 includes a twentieth transistor T26, a gate of the twentieth transistor T26 receiving the second driving signal D, one of a source and a drain of the twentieth transistor T26 receiving the second level VGH, and the other of the source and the drain of the twentieth transistor T26 receiving the first driving signal P.
The (3 n-1) th stage gate driving unit GOA (3 n-1) further includes a first voltage stabilizing module 23. The first voltage stabilizing module 23 includes a twenty-first transistor T6 and a fourth capacitor C2. The gate of the twenty-first transistor T6 is connected to the first electrode of the fourth capacitor C2, one of the source and the drain of the twenty-first transistor T6 receives the second clock signal CK2, and the other of the source and the drain of the twenty-first transistor T6 is connected to the second electrode of the fourth capacitor C2.
The (3 n-1) -th stage gate driving unit GOA (3 n-1) further includes a second voltage stabilizing module 24, wherein the second voltage stabilizing module 24 includes a twenty-second transistor T11, a gate of the twenty-second transistor T11 receives the first level VGL, and a source and a drain of the twenty-second transistor T11 are connected between the gate of the twenty-first transistor T6 and the other one of the source and the drain of the fourteenth transistor T4.
The (3 n-1) th stage gate driving unit GOA (3 n-1) further includes a third voltage stabilizing module 25. The third voltage stabilizing module 25 includes a thirteenth transistor T7, a gate of the thirteenth transistor T7 receives the second clock signal CK2, and a source and a drain of the thirteenth transistor T7 are connected between the gate of the fourth transistor T10 and the other of the source and the drain of the twenty-first transistor T6.
The (3 n-1) -th stage gate driving unit GOA (3 n-1) further includes a fourth voltage stabilizing module 19, the fourth voltage stabilizing module 19 includes a twenty-fourth transistor T12, a gate of the twenty-fourth transistor T12 receives the first level VGL, and a source and a drain of the twenty-fourth transistor T12 are connected between the gate of the fifth transistor T9 and the other one of the source and the drain of the thirteenth transistor T3.
The (3 n-1) -th stage gate driving unit GOA (3 n-1) further includes a fifth voltage stabilizing module 17, the fifth voltage stabilizing module 17 including a twenty-fifth transistor T23, a gate of the twenty-fifth transistor T23 receiving the first level VGL, a source and a drain of the twenty-fifth transistor T23 being connected between the gate of the seventh transistor T25 and the other one of the source and the drain of the third transistor T20.
It should be noted that, the first transistor T18 to the twenty-fifth transistor T23 are P-type transistors. The fourth transistor T10 and the fifth transistor T9 are P-type transistors.
Referring to fig. 5 again, the second gate driving unit GOA (2) is selected for illustration. Wherein, selecting the second gate driving unit GOA (2) means that the second gate driving unit GOA (2) outputs the display scanning signal WR1 (2) in the display scanning period S1, and selecting the second gate driving unit GOA (2) in the display scanning period S1, and making the second gate driving unit GOA (2) output the compensation detection scanning signal WR1 (2) in the scanning blank period S2.
In the first period T1 of the display scan period S1, the first compensation detection selection signal LP1, the second compensation detection selection signal LP2 and the third compensation detection selection signal LP2 are all low level signals to initialize the dot positions of the second transistor T19 of each gate driving unit.
In the second period t2 of the display scan period S1, the first compensating detection select signal LP1 and the third compensating detection select signal LP2 are both high level signals, and the second compensating detection select signal LP2 is a low level signal. When the first stage transmission signal ST (1) is a low level signal, the first transistor T18 of the second stage gate driving unit GOA (2) is turned on, the first transistor T18 outputs a low level detection selection control signal M (2), and the first capacitor C4 stores the detection selection control signal M (2).
In the third period T3 of the display scan period S1, the switching control signal CKB is switched from the low level to the high level, the eleventh transistor T22 and the twelfth transistor T21 are turned off, and the input control module 11 is disconnected from the output module 14.
In a fourth period T4 of the scan blank period S2, the second transistor T19 of the second stage gate driving unit GOA (2) is turned on, the output control signal RE is switched to a low level, the third transistor T20 of the second stage gate driving unit GOA (2) is turned on, the third transistor T20 outputs a low level compensation detection driving signal, and the seventh transistor T25 outputs a low level compensation detection scanning signal WR1 (2) according to the low level compensation detection driving signal. The second scanning signal line GL2 connected to the second stage gate driving unit GOA (2) outputs the low level compensation detection scanning signal WR1 (2) to the data writing transistor K1 of the corresponding pixel driving circuit 200, the data writing transistor K1 is turned on, the compensation control transistor K2 is also turned on, and the detection chip 30 detects the initial threshold voltage of the data writing transistor K1.
The foregoing description of the embodiments is only for the purpose of aiding in the understanding of the technical solutions of the present application and the core ideas thereof, and it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalents may be substituted for some of the technical features thereof, and these modifications or substitutions do not depart from the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (14)

1. A display panel, wherein a frame time of the display panel includes a display scan period and a scan blanking period, the display panel comprising:
A plurality of cascaded gate driving units, the gate driving units comprising:
An input control module for outputting a driving signal during the display scan period;
a compensation detection control module for outputting a compensation detection driving signal during the scanning blank period, and
An output module connected with the input control module and the compensation detection control module for responding to the driving signal to output a display scanning signal in the display scanning period and responding to the compensation detection driving signal in the scanning blank period to output a compensation detection scanning signal, and
And the pixel driving circuit is connected with the grid driving unit and is used for receiving the display scanning signal in the display scanning period and receiving the compensation detection scanning signal in the scanning blank period.
2. The display panel according to claim 1, wherein the gate driving unit further comprises a gradation module for outputting a present gradation signal in response to the driving signal in the display scan period;
the compensation detection control module includes:
a detection selection circuit for outputting the detection selection control signal in response to the pre-gradation signal and the compensation detection selection signal in the display scan period, and
And the detection control circuit is used for responding to the detection selection control signal and the output control signal in the scanning blank period to output the compensation detection driving signal.
3. The display panel of claim 2, wherein the detection selection circuit comprises:
and a first transistor having a gate receiving the compensation detection selection signal, one of a source and a drain receiving the pre-stage transmission signal, and the other of the source and the drain outputting the detection selection control signal during the display scan period.
4. A display panel according to claim 2 or 3, wherein the detection control circuit comprises:
A second transistor receiving the detection selection control signal at a gate of the second transistor in the display scan period, one of a source and a drain of the second transistor receiving a first level;
a first capacitor receiving the detection selection control signal at a first electrode of the first capacitor and receiving the first level at a second electrode of the first capacitor in the display scan period, and
And a third transistor, one of a source and a drain of the third transistor being connected to the other of the source and the drain of the second transistor, a gate of the third transistor receiving the output control signal during the scan blank period, the other of the source and the drain of the third transistor outputting the compensation detection driving signal.
5. The display panel of claim 2, wherein the drive signals include a first drive signal and a second drive signal, the present-stage signaling signal includes a high-level present-stage signaling signal and a low-level present-stage signaling signal that is less than the high-level present-stage signaling signal, the stage signaling module includes:
A fourth transistor having a gate receiving the first driving signal, one of a source and a drain receiving a second level, the other of the source and the drain outputting the high-level current-level signal;
And a fifth transistor having a gate receiving the second driving signal, one of a source and a drain receiving a first level, the other of the source and the drain outputting the low-level current-level hierarchical signal.
6. The display panel of claim 5, wherein the pre-stage signaling signal comprises a low-level pre-stage signaling signal, and the detection selection circuit is configured to output the detection selection control signal in response to the low-level pre-stage signaling signal and the compensation detection selection signal during the display scan period.
7. The display panel of claim 5, wherein the display scan signals include an active display scan signal and an inactive display scan signal, the output module comprising:
A sixth transistor having a gate receiving the first driving signal, one of a source and a drain receiving a second level, the other of the source and the drain outputting the inactive display scan signal during the display scan period, and
A seventh transistor, a gate of the seventh transistor receiving the second driving signal, one of a source and a drain of the seventh transistor receiving a first level, the other of the source and the drain of the seventh transistor outputting the effective display scan signal in the display scan period.
8. The display panel of claim 7, wherein the gate driving unit further comprises:
a feedback module for receiving the first driving signal and the clock signal during the display scan period and outputting a feedback signal, and
And the pull-down module is used for receiving the feedback signal in the display scanning period so as to pull down the second driving signal received by the grid electrode of the seventh transistor.
9. The display panel of claim 8, wherein the pull-down module comprises:
And an eighth transistor, one of a gate, a source and a drain of the eighth transistor receiving the feedback signal in the display scan period, the other of the source and the drain of the eighth transistor being connected to the gate of the seventh transistor.
10. The display panel of claim 9, wherein the feedback module comprises:
A ninth transistor, a gate of which receives the first driving signal, and one of a source and a drain of which receives a second level in the display scan period;
a tenth transistor receiving the clock signal in one of a source and a drain of the tenth transistor in the display scan period, and
A second capacitor having a first electrode connected to the other of the source and the drain of the ninth transistor and the other of the source and the drain of the tenth transistor, and a second electrode connected to the gate of the tenth transistor and the gate of the eighth transistor.
11. The display panel of claim 7, wherein the gate driving unit further comprises a switching module for connecting the input control module and the output module during the display scan period and for disconnecting the input control module and the output module during the scan blanking period.
12. The display panel of claim 11, wherein the switching module comprises:
an eleventh transistor having a gate receiving a switching control signal, a source and a drain connected between the gate of the sixth transistor and the input control module, and
A twelfth transistor, a gate of which receives a switching control signal, a source and a drain of which are connected between the gate of the seventh transistor and the input control module.
13. The display panel according to claim 1, wherein the pixel driving circuit includes a data writing transistor having a gate receiving the display scan signal during the display scan period and receiving the compensation detection scan signal during the scan blank period, one of a source and a drain receiving the data signal;
A driving transistor having a gate connected to the other of the source and the drain of the data writing transistor, the one of the source and the drain of the driving transistor receiving a first power supply signal;
A compensation control transistor having a gate receiving a compensation control signal, one of a source and a drain of the compensation control transistor and the other of the source and the drain of the driving transistor receiving a second power signal, the other of the source and the drain of the compensation control transistor being connected to the detection chip, and
A storage capacitor connected between the other of the source and the drain of the data writing transistor and the other of the source and the drain of the driving transistor.
14. The display panel of claim 13, wherein the data writing transistor and the compensation control transistor each comprise a P-type transistor.
CN202310810718.6A 2023-07-03 2023-07-03 Display Panel Pending CN119252189A (en)

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