CN119252181A

CN119252181A - Pixel circuit, display panel and display device

Info

Publication number: CN119252181A
Application number: CN202411613036.7A
Authority: CN
Inventors: 朱志坚; 黄寅虎; 杨盛际; 卢鹏程; 白枭; 张大成
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Yunnan Chuangshijie Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Yunnan Chuangshijie Optoelectronics Technology Co Ltd
Priority date: 2024-11-12
Filing date: 2024-11-12
Publication date: 2025-01-03

Abstract

The present application discloses a pixel circuit, a display panel and a display device, which relate to the field of display technology, and can improve the dark line defect caused by local electrode short circuit, and improve the display effect and display yield. The pixel circuit includes: a first subcircuit is electrically connected to a first node, and the first subcircuit is used to electrically connect a data signal line; a second subcircuit is electrically connected to a second node, and the second subcircuit is used to electrically connect a first power line; a driving subcircuit is electrically connected to a first node, a second node and a third node respectively, and the third node is used to electrically connect to a first pole of a light-emitting device, and the second pole of the light-emitting device is used to electrically connect to a common electrode; a reset subcircuit includes a protection unit and a reset unit, and the protection unit is electrically connected to the reset unit, and the protection unit is electrically connected to the third node, and the reset unit is used to electrically connect to a second power connection line; the protection unit includes a resistor, and the resistivity of the protection unit is less than the resistivity of the second power connection line.

Description

Pixel circuit, display panel and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a pixel circuit, a display panel, and a display device.

Background

Currently, in the field of display technology, a pixel circuit is used as a core circuit of a display driving back plate, and forms a basic display driving back plate with a gate driving circuit, a data driving circuit and the like. The pixel circuit writes the display data signals output by the data driving circuit into the storage capacitor of the pixel circuit line by line through the switching tube in the pixel circuit under the control of the line scanning signals output by the gate driving circuit, the driving tube in the pixel circuit accurately and continuously outputs voltage or current to the display photoelectric device, such as the pixel electrode of the light emitting device or the liquid crystal panel, under the control of the voltage stored by the capacitor, and the display device displays image information in an active light emitting or passive light emitting mode under the driving of the current or the voltage.

However, in the conventional pixel circuit structure, the local electrode short circuit easily causes poor dark lines of the whole row, the whole column or the cross shape, and seriously affects the display effect and the yield of the display panel.

Disclosure of Invention

The embodiment of the application provides a pixel circuit, a display panel and a display device, which can improve poor dark lines caused by local electrode short circuits and improve display effect and display yield.

In a first aspect of an embodiment of the present application, there is provided a pixel circuit including:

A first sub-circuit electrically connected to the first node, the first sub-circuit being for electrically connecting the data signal line;

the second sub-circuit is electrically connected with the second node and is used for being electrically connected with the first power line;

A driving sub-circuit electrically connected to the first node, the second node, and a third node, respectively, the third node being for electrically connecting to a first electrode of a light emitting device, the second electrode of the light emitting device being for electrically connecting to a common electrode;

The reset sub-circuit comprises a protection unit and a reset unit, wherein the protection unit is electrically connected with the reset unit, the protection unit is electrically connected with the third node, the reset unit is used for being electrically connected with a second power supply connecting wire, and the second power supply connecting wire is used for transmitting a second power supply signal;

the protection unit comprises a resistor, and the resistivity of the protection unit is smaller than that of the second power supply connecting wire.

In some embodiments, in the case that there is a short circuit between the first electrode and the second electrode of the light emitting device, a difference between the potential of the second power connection line and the potential of the common electrode is a first difference, the first difference is greater than or equal to a driving voltage difference of light emission of the light emitting device, the protection unit is configured to break under a current formed between the second power connection line and the third node, and the reset unit is disconnected from the third node.

In some embodiments, the first sub-circuit, the second sub-circuit, the driving sub-circuit, and the reset unit each include a transistor, the second sub-circuit includes a capacitor unit, a first end of the capacitor is electrically connected to the first node, a second end of the capacitor unit is electrically connected to the second node, a third end of the capacitor unit is electrically connected to a fourth node, and the fourth node is electrically connected to the first power line;

the driving sub-circuit includes a P-type transistor, and the reset unit includes an N-type transistor.

In some embodiments, the first sub-circuit includes a first transistor, the second sub-circuit includes a second transistor, the driving sub-circuit includes a driving transistor, the reset unit includes a third transistor, and the capacitance unit includes a first capacitance and a second capacitance;

The grid electrode of the first transistor is used for receiving a first control signal, the first electrode of the first transistor is used for being electrically connected with a data signal line, the second electrode of the first transistor is electrically connected with the first node, the grid electrode of the second transistor is used for receiving a second control signal, the first electrode of the second transistor is electrically connected with the fourth node, the second electrode of the second transistor is electrically connected with the second node, two ends of the first capacitor are respectively electrically connected with the first node and the second node, two ends of the second capacitor are respectively electrically connected with the second node and the fourth node, the grid electrode of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, the second electrode of the driving transistor is electrically connected with the third node, the grid electrode of the third transistor is used for receiving a third control signal, the first electrode of the third transistor is electrically connected with the protection unit, and the second electrode of the third transistor is electrically connected with the third power supply.

In some embodiments, the first control signal is for controlling the first transistor to be turned off to turn off the first sub-circuit in the presence of a short circuit of the first and second poles of the light emitting device, the second control signal is for controlling the second transistor to be turned off to turn off the second sub-circuit, the third control signal is for controlling the third transistor to be turned on to turn on the reset unit, and/or,

In the case where there is a short circuit between the first and second electrodes of the light emitting device, the potential of the second power supply signal is a ground potential, and the potential of the common electrode is a negative potential.

In some embodiments, the protection unit includes an electrical fuse;

in the presence of a short circuit of the first and second poles of the light emitting device, the electric fuse is for blowing under the action of a flowing current to disconnect the reset unit from the third node.

In some embodiments, the protection unit includes an electrical fuse;

the electrical fuse is arranged in the same layer as at least one signal line, the electrical fuse has a resistivity smaller than that of the signal line arranged in the same layer, and/or,

The electrical fuse is arranged in the same layer as the gate of the transistor, the electrical fuse has a resistivity less than the gate of the transistor, and/or,

The electrical fuse is arranged on the same layer as the semiconductor layer, and the resistivity of the electrical fuse is smaller than that of the semiconductor layer arranged on the same layer.

In some embodiments, the protection unit includes an electrical fuse;

The electric fuse comprises a first connecting end, a second connecting end and a fuse wire section, wherein the fuse wire section, the first connecting end and the second connecting end are of an integrated structure, and the fuse wire section is connected between the first connecting end and the second connecting end;

the first connecting end is electrically connected with the third node through a first via hole, and the second connecting end is electrically connected with the reset unit through a second via hole;

the dimension of the fuse wire section in the first direction is smaller than the dimension of the connecting end, the first direction is intersected with the second direction, and the second direction is the length direction of the fuse wire section.

In some embodiments, the pixel circuit further comprises:

a process reference structure disposed on the same layer as the electrical fuse;

The process reference structure, the first connecting end and the second connecting end are respectively arranged on different sides of the fuse wire section;

The orthographic projection of the process reference structure on the substrate layer does not overlap with the orthographic projection of the electrical fuse on the substrate layer.

In some embodiments, the second power supply connection line is used for electrically connecting with a second power supply line, and the second power supply line is electrically connected with a plurality of the second power supply connection lines;

The current density of the second power supply connecting wire is larger than that of the electric fuse;

the current density of the second power supply line is greater than the current density of the electric fuse.

In some embodiments, the electrical fuse is connected to the first pole of the light emitting device at a greater distance than the electrical fuse is connected to the second power connection line, and/or,

The electrical fuse blowing voltage ranges from 7.5V to 9V, and/or,

The fuse section has a line width in the range of 0.02 μm to 0.2 μm, and the fuse section has a thickness in the range of 200nm to 500nm, and/or,

The fuse wire sections are arranged in a curve or a broken line.

In some embodiments, the protection unit includes an electric fuse for blowing under the action of a flowing current to disconnect the reset unit from the third node in the case where there is a short circuit of the first and second poles of the light emitting device;

the electrical fuse has a sheet resistance in the range of 0.06 to 0.3 ohm/≡and/or,

The electrical fuse at least partially surrounds the third transistor and/or,

A shielding layer is arranged between the grid electrode of the third transistor and the electric fuse.

In a second aspect of an embodiment of the present application, there is provided a display panel including:

The pixel circuit according to the first aspect;

a light emitting device having a first electrode electrically connected to a third node of the pixel circuit;

A data signal line electrically connected to the first sub-circuit of the pixel circuit;

A first power line electrically connected to the second sub-circuit of the pixel circuit;

the second power supply connecting wire is electrically connected with the reset unit of the pixel circuit;

a second power supply line electrically connected to the plurality of pixel circuits through the second power supply connection line;

And a common electrode electrically connected to the second electrode of the light emitting device.

A third aspect of an embodiment of the present application provides a display device, including:

The display panel according to the second aspect.

By arranging the protection unit in the pixel circuit, the protection unit can comprise a resistor, the resistivity of the resistor of the protection unit can be smaller than that of the second power supply connecting wire, and under the condition that the two poles of the light emitting device are in short circuit, the resistor of the protection unit can be broken under the action of high current, and the high current has no influence on the second power supply connecting wire. The disconnection of the protection unit may disconnect the reset unit from the third node. The reset unit is disconnected with the third node, so that under the condition that the first pole and the second pole are short-circuited, the potential of the second power supply connecting wire is prevented from being pulled to the short-circuit potential of the first pole, and further the potential of the second power supply wire is prevented from being pulled to the potential of the first pole, and the defect of dark lines of whole rows, whole columns or cross shapes caused by short circuit of the local light emitting devices is avoided. The dark line defect in the display mode of the display panel can be repaired as a dot defect.

Drawings

Fig. 1 is a schematic block diagram of a pixel circuit according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present application;

FIG. 3 is a schematic block diagram of a display chip according to an embodiment of the present application;

FIG. 4 is a schematic architecture diagram of another display panel according to an embodiment of the present application;

Fig. 5 is a schematic structural diagram of a display module according to an embodiment of the present application;

fig. 6 is a schematic circuit connection diagram of a display panel according to an embodiment of the present application;

FIG. 7 is a schematic block diagram of another pixel circuit according to an embodiment of the application;

FIG. 8 is a schematic block diagram of yet another pixel circuit provided by an embodiment of the application;

FIG. 9 is a schematic diagram of a driving timing diagram of a pixel circuit according to an embodiment of the present application;

Fig. 10 is a schematic diagram of an operating state of a first stage of a pixel circuit according to an embodiment of the present application;

FIG. 11 is a schematic diagram illustrating an operation state of a second stage of a pixel circuit according to an embodiment of the present application;

fig. 12 is a schematic diagram of an operating state of a third stage of a pixel circuit according to an embodiment of the present application;

fig. 13 is a schematic diagram illustrating an operating state of a fourth stage of a pixel circuit according to an embodiment of the present application

Fig. 14 is a schematic diagram showing a fourth stage of operation of another pixel circuit according to an embodiment of the present application;

FIG. 15 is a timing diagram of a portion of control signals for repairing a driving mode according to an embodiment of the present application;

FIG. 16 is a schematic diagram illustrating an operating state of a pixel circuit in a repair driving mode according to an embodiment of the present application;

FIG. 17 is a schematic diagram illustrating another working state of the pixel circuit in the repair driving mode according to the embodiment of the present application;

FIG. 18 is a schematic diagram illustrating another working state of the pixel circuit in the repair driving mode according to the embodiment of the present application;

Fig. 19 is a schematic structural view of an electric fuse provided in an embodiment of the present application;

fig. 20 is a schematic structural view of another electric fuse provided in an embodiment of the present application;

fig. 21 is a schematic structural view of yet another electric fuse provided in an embodiment of the present application;

fig. 22 is a schematic structural view of still another electric fuse provided in an embodiment of the present application;

Fig. 23 is a schematic structural view of an electric fuse provided in an embodiment of the present application;

fig. 24 is a schematic structural view of a display panel according to an embodiment of the present application;

fig. 25 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

In order to better understand the technical solutions provided by the embodiments of the present specification, the following detailed description of the technical solutions of the embodiments of the present specification is made through the accompanying drawings and the specific embodiments, and it should be understood that the specific features of the embodiments of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and not limit the technical solutions of the present specification, and the technical features of the embodiments of the present specification may be combined with each other without conflict.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element. The term "two or more" includes two or more cases.

Currently, in the field of display technology, a pixel circuit is used as a core circuit of a display driving back plate, and forms a basic display driving back plate with a gate driving circuit, a data driving circuit and the like. The pixel circuit writes the display data signals output by the data driving circuit into the storage capacitor of the pixel circuit line by line through the switching tube in the pixel circuit under the control of the line scanning signals output by the gate driving circuit, the driving tube in the pixel circuit accurately and continuously outputs voltage or current to the display photoelectric device, such as the pixel electrode of the light emitting device or the liquid crystal panel, under the control of the voltage stored by the capacitor, and the display device displays image information in an active light emitting or passive light emitting mode under the driving of the current or the voltage. However, in the conventional pixel circuit structure, the local electrode short circuit easily causes poor dark lines of the whole row, the whole column or the cross shape, and seriously affects the display effect and the yield of the display panel.

In view of the above, embodiments of the present application provide a pixel circuit, a display panel and a display device, which can improve the poor dark line caused by the short circuit of the local electrode, and improve the display effect and the display yield.

In a first aspect of the embodiment of the present application, a pixel circuit is provided, and fig. 1 is a schematic block diagram of a pixel circuit provided in the embodiment of the present application. As illustrated in fig. 1, a pixel circuit includes a first sub-circuit 100 electrically connected to a first node N1, a first sub-circuit 100 electrically connected to a DATA signal line 600, the DATA signal line 600 may be used to transmit a DATA signal DATA, a second sub-circuit 200 electrically connected to a second node N2, the second sub-circuit 200 electrically connected to a first power line 700, the first power line 700 may be used to transmit a first power signal VDD, a driving sub-circuit 300 electrically connected to the first node N1, the second node N2, and a third node N3, respectively, a third node N3 electrically connected to a first electrode 510 of a light emitting device 500, a second electrode 520 of the light emitting device 500 electrically connected to a common electrode 800, the common electrode 800 may be used to transmit a common signal VCOM, and a reset unit 420, the protection unit 410 electrically connected to the third node N3, the reset unit 420 electrically connected to the second power signal line 900, and the second power supply 900 electrically connected to the second power line 900. The light emitting device 500 may emit light under the voltage driving of the first and second electrodes 510 and 520. The protection unit 410 includes a resistance, and the protection unit 410 has a resistivity smaller than that of the second power connection line 900.

In some examples, the second power connection line 900 is connected to a second power line, and the second power line may be connected to an entire row of pixel circuits, an entire column of pixel circuits, or a pixel circuit arranged in a cross shape, where the potential of the second power connection line 900 connected to the current pixel circuit may adversely affect the potential of the second power line.

Under the condition that two poles of the light-emitting device are short-circuited, the resistor of the protection unit can be broken under the action of high current, the protection unit is broken after breaking, and the high current has no influence on the second power supply connecting wire. The disconnection of the protection unit may disconnect the reset unit from the third node. The reset unit is disconnected with the third node, so that under the condition that the first pole and the second pole are short-circuited, the potential of the second power supply connecting wire is prevented from being pulled to the short-circuit potential of the first pole, and further the potential of the second power supply wire is prevented from being pulled to the potential of the first pole, and the defect of dark lines of whole rows, whole columns or cross shapes caused by short circuit of the local light emitting devices is avoided. The dark line defect in the display mode of the display panel can be repaired as a dot defect.

For example, referring to fig. 1, a repair driving mode may be set in which a difference between a potential of the second power connection line 900 and a potential of the common electrode 800 is a first difference, which may be a difference between the second power signal VSS and the understanding signal VCOM, the first difference being greater than or equal to a driving voltage difference of the light emitting device 500, i.e., a magnitude of the first difference may be used to drive the light emitting device 500 to emit light, and the protection unit 410 may be used to disconnect the reset unit 420 from the third node N3 under the effect of a current formed between the second power connection line 900 and the third node N3 if there is a short circuit condition of the first pole 510 and the second pole 520 of the light emitting device 500. The reset unit 420 is disconnected from the third node, so that the potential of the second power connection line 900 is prevented from being pulled to the short-circuit potential of the first pole 510 under the condition that the first pole 510 and the second pole 520 are short-circuited, and further the potential of the second power line is prevented from being pulled to the potential of the first pole 510, thereby avoiding the dark line defect of whole row, whole column or cross shape caused by short circuit of the local light emitting devices. The dark line defect can be repaired as a spot defect.

For example, the driving control circuit in the silicon-based OLED (organic light emitting diode) micro display, the silicon-based LED (light emitting diode) micro display, and the OLED display may include GATE DRIVER (gate driving) circuits, source driver circuits, and pixel circuits. Dual chip and single chip display architectures are included in silicon-based microdisplay architectures and manufacturing processes. The product types applicable to the pixel circuit provided by the embodiment of the application include, but are not limited to, silicon-based OLED micro-displays, silicon-based LED micro-displays and OLED displays. The field of application of the display panel applied by the pixel circuit provided by the embodiment of the application includes, but is not limited to, smart phones, computers, televisions, tablet computers or smart wearable devices, and the smart wearable devices can include smart watches or smart glasses, such as consumer electronics products including AR (augmented reality), VR (virtual reality), XR (augmented reality), MR (mixed reality), sighting telescope, range finder and the like.

Illustratively, a silicon-based OLED is a novel display technology that combines semiconductor processing with OLED display technology to produce an OLED device with a single crystal silicon drive circuit wafer as a substrate. The advantages of the semiconductor manufacturing process and the OLED display technology are achieved, and the technology can manufacture a micro display with smaller display area (generally 0.2-1.8 inch) on the basis of maintaining a certain resolution, so that the silicon-based OLED has very high pixel density (generally more than 3000 PPI). Besides high PPI, the silicon-based OLED has the advantages of high brightness, low power consumption, high response speed, high color gamut, high thermal stability and the like.

Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present application. For example, referring to fig. 2, the silicon-based OLED may be a single chip driving architecture. The single-chip driving architecture is to integrate and design the display area ACTIVE AREA of the display panel and the complete display control and driving circuit on the same chip, wherein the driving circuit comprises a row driving unit GATEDRIVER, a column driving unit SOURCE driver_mux, an image processing unit IMAGE PROCESS BLOCK, a storage unit RAM, a clock control unit OTC and the like. The binding AREA binding PAD AREA may bind the display chip.

Fig. 3 is a schematic architecture block diagram of a display chip according to an embodiment of the present application. For example, referring to fig. 3, the display chip in the single chip architecture may include digital and analog parts, which are mixed signal chips. The display chip comprises an electrostatic module ESD, a data driving module SD, a clock control module GTON, a memory unit RAM, a POWER module POWER, a processor interface MIPI, a clock generation module TS, and an I/O Pad of an input/output pin, and the image processing unit IMAGE PROCESS BLOCK, the clock control unit OTC and the like in the display control circuit belong to the digital module, and a semiconductor process (generally 55 nm) requiring a higher process node is used for manufacturing, meanwhile, because the logic of the digital module is complex, the number of metal layers (generally at least 6 metal layers) is more, resulting in overhigh production cost of the monocrystalline silicon driving substrate. In addition, the yield of the silicon-based OLED microdisplay can be divided into a display area portion and a display control driving portion, the yield of the display control driving portion is determined only by the semiconductor process, and the yield of the display area is determined by both the semiconductor process and the OLED device process. Under the single chip architecture, any part of defects can cause the whole module to become defective products, so that the product yield loss is large, and the production cost is further increased.

With the increasing display size requirements, cost issues of single chip architecture are of concern. To reduce the cost, and at the same time further reduce the power consumption, a dual chip architecture is proposed. Fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present application. Illustratively, as shown in fig. 4, the dual chip architecture is to integrate the display area and part of the driving circuitry in the panel. The remaining driving circuits and the display control circuit are independently DDICs. The panel part includes a display area ACTIVE AREA, a row driving unit GATEDRIVER, and a data driving module SD, and the DDIC part includes a timing controller CT, a processor interface MIPI, an image processing unit, which may include a data signal unit ddic_source, and a scan signal unit including ddic_gout_l and ddic_gout_r. The panel can also integrate a multiplexing circuit DeMUX <1:6> and a Cathode signal loop line Cathade Ring. After the design of the Panel and the DDIC is completed, the Panel and the DDIC are manufactured by adopting different process node processes, the DDIC part adopts a high process node process (generally below 28 nm), and the Panel part adopts a low process node process (generally 110 nm). After the production and manufacture of the panel circuit are completed, the panel good product is continuously put into the production and manufacture of the OLED device, and finally the manufactured panel good product and the DDIC good product are combined together through a binding process and a binding Area DDIC_I/O Pd Area to form a complete display or a display module.

Fig. 5 is a schematic structural diagram of a display module according to an embodiment of the present application. As illustrated in fig. 5, the display module includes a display panel, a driving chip DDIC, and a flexible circuit board FPC. The display panel is provided with a multiplexing circuit DeMUX <1:6>, cathode signal Ring lines captode Ring, a row driving unit GATEDRIVER, and a timing controller CT.

The panel portions have different components according to different partitioning schemes. The display area, GATE DRIVER circuits, and part of the source driver may be fabricated on the panel. Fig. 6 is a schematic circuit connection diagram of a display panel according to an embodiment of the present application. Exemplary, as shown in fig. 6, the display area is formed by an array of pixel circuits, each pixel circuit correspondingly drives a sub-pixel to emit light, that is, provides current required by the light emission of the OLED device, the row driving circuit provides a time signal required by the row switch of the pixel circuit to realize the progressive scanning function of display, and the column driving circuit provides a column signal required by the pixel circuit to realize the switching and control of the display picture.

In the single-chip architecture and the dual-chip architecture, the pixel circuit is used as a key part of the display driving backboard, and directly influences the PPI, the maximum brightness, the contrast, the crosstalk, the jitter and other performance indexes of the display.

The pixel circuit outputting the stabilized voltage may be referred to as a voltage type pixel circuit, and the pixel circuit outputting the stabilized current may be referred to as a current type pixel circuit, and the type of the pixel circuit may be determined according to the photoelectric characteristics of the display device. The pixel circuit can have a data writing stage and an output stage (or called a light emitting stage), the consistency of the on-off characteristic of the photoelectric device and the initial working state of the pixel circuit needs to be increased in an initialization stage, and in order to improve the uniformity of output current or voltage, the uniformity of threshold voltage and the carrier mobility of the driving tube need to be compensated, and an additional threshold compensation stage needs to be added. Therefore, the pixel driving circuit operating state includes four phases of initialization, threshold compensation, data writing, and driving light emission. Different applications and different circuit designs, four phases have the condition of simplification and combination, for example, the threshold compensation phase and the data writing phase are combined, and the threshold compensation and the data writing are performed in the same phase.

The measurement indexes of the pixel driving circuit mainly comprise three points, namely a range of outputting stable voltage and/or current, a wider application range of the pixel circuit with larger output stable current or voltage range, higher display brightness and contrast, better circuit performance, uniformity of the output voltage and/or current, better uniformity of the output current or voltage, better display brightness uniformity, stability of the output voltage and/or current, and stable output of the pixel circuit in one frame time because the display is to refresh the display image in a frame unit, and stable output of the pixel circuit in the display of complex or specific images because the displayed image is more complex, namely the pixel driving circuit output is not influenced by other data on a data line.

Fig. 7 is a schematic block diagram of another pixel circuit according to an embodiment of the present application. Referring to fig. 7, an exemplary embodiment of the present application is shown in fig. 7, where the third node N3 connected to the light emitting device 500 is directly connected to the reset unit 420, in the case where vcom= -9V is short-circuited between two end electrodes of the light emitting device 500, the potential of the first electrode 510 of the pixel circuit is pulled to the common signal VCOM, that is, generally-9V, the potential of one end of the reset unit 420 connected to the third node N3 of the pixel circuit is pulled to-9V, in the case where the reset unit 420 is turned on, the potential of one end of the reset unit 420 connected to the second power connection line 900 is pulled to-9V, the second power connection line 900 is connected to the second power connection line, the second power connection line may be connected to the whole row of pixel circuits, or connected to the pixel circuits arranged in a cross, the second power connection line is pulled to about-8V under the voltage drop effect, in the second power connection line is transmitted to the reset unit of other pixel circuits, in the case where the reset unit 420 of the other pixel circuits is connected to the reset unit is pulled to-9V, in the cross-8V of the other pixel circuits is turned on, that is acted on by the cross-8V of the other pixel circuits, that is, the cross-8V of the other pixel circuits is not connected to the other pixel circuits, and the cross-8V is pulled down on the common signal line is formed at the voltage drop-8V, and the voltage is formed at the dark line, and the dark line is formed at the voltage drop voltage level, or at the dark line is generally opposite to the voltage level, and the dark line is formed at the voltage level or at the dark line, and the dark line is opposite to the voltage level or the voltage level to the voltage V. Under the application of short circuit of the electrodes at two ends of one or more local light-emitting devices, a larger range of bad dark lines is caused, and the display effect, the yield and the reliability of the display panel are seriously affected.

Referring to fig. 1, a protection unit 410 is disposed in a pixel circuit, the protection unit 410 is disposed between a reset unit and a third node N3, a repair driving mode is set, in which the reset unit 420 and the protection unit 410 are both turned on, a short circuit does not occur between a first pole 510 and a second pole 520, the potential of the second pole 520 is identical to that of the common electrode 800, the potential of the first pole 510 is independent of that of the second pole 520 due to the non-short circuit, the potential of the first pole 510 is identical to that of one end of the protection unit 410 connected to the third node N3, the protection unit 410 can be regarded as a conductive wire, the potentials of both ends of the protection unit 410 are almost identical, the reset unit 420 can be regarded as a conductive wire when turned on, and the potential of both ends of the reset unit is identical to that of a second power signal on a second power connection wire. For example, in the repair driving mode, the common signal vcom= -9V, the potential of the second power connection line is the ground potential, that is, the second power signal vss=0v, the potential of the first electrode 510 is 0V, the voltage difference across the light emitting device 500 is 9V, and the potential of the first electrode 510 is higher than the potential of the second electrode 520, and the 9V satisfies the lighting voltage of the light emitting device, the light emitting device 500 may be normally lighted. Therefore, the repair driving mode does not affect the normal light emitting device and the connected pixel circuit.

Referring to fig. 1, in the repair driving mode, both the reset unit 420 and the protection unit 410 are turned on, the first pole 510 and the second pole 520 are shorted, the potential of the second pole 520 is identical to that of the common electrode 800, the potential of the first pole 510 is identical to that of one end of the protection unit 410 connected to the third node N3 due to the short circuit, the reset unit 420 is regarded as a conductive wire when turned on, and the potentials of both ends of the reset unit are identical to that of the second power signal on the second power connection line. In the repair driving mode, the common signal vcom= -9V is used to set the potential of the first pole 510 to-9V, the potential of the second power connection line 900 is set to the ground potential, i.e., the second power signal vss=0v is used to set the potential of one end of the reset unit 420 connected to the protection unit 410 to 0V, the voltage difference across the protection unit 410 is set to 9V, the current flowing through the protection unit 410 is large, which may cause the protection unit 410 to break, the connection between the reset unit 420 and the third node N3 is cut off, i.e., the connection between the second power connection line 900 and the first pole 510 is cut off, the potential on the second power connection line 900 is not affected, and the potential on the second power connection line is not affected. After the repairing driving mode is passed, in the process of lighting driving the pixel circuits of the display panel, the second power line and the pixel circuits connected with the short-circuited light emitting devices are mutually independent, namely, no electric connection relation exists, so that the potential of the second power line is not interfered by the pixel circuits where the short-circuited light emitting devices are located, dark point defects can occur at the positions where the short-circuited light emitting devices are located, but dark line defects can not occur, the defective range can be reduced to a large extent, and the display effect, the yield and the reliability of the display panel are improved.

It should be noted that, the signal voltage values mentioned in the above embodiments are only illustrative, the value of the common signal VCOM may be other values such as-12V, -11V, -10V, -8V or-7V, and the value of the second power signal VSS may be 0V, 1V or-1V, and the driving operation of the second power signal VSS being the ground potential is relatively simple.

Illustratively, the first pole 510 of the light emitting device 500 may be an anode of a light emitting diode and the second pole 520 may be a cathode of the light emitting diode.

The repair driving mode may be an independent mode independent of the lighting mode, may repair all pixel circuits of the display panel in the detection phase, may isolate the shorted light emitting device from the second power line, and may prevent the pixel circuits connected to the shorted light emitting device from interfering with the pixel circuits connected to the same second power line in the lighting mode.

In some embodiments, the first sub-circuit, the second sub-circuit, the driving sub-circuit and the reset unit each include a transistor, the second sub-circuit includes a capacitor unit, a first end of the capacitor unit is electrically connected to the first node, a second end of the capacitor unit is electrically connected to the second node, a third end of the capacitor unit is electrically connected to a fourth node, the fourth node is electrically connected to the first power line, and the capacitor unit is capable of storing and discharging charges.

In some examples, the drive subcircuit includes a P-type transistor and the reset unit includes an N-type transistor.

The reset unit adopts the P-type transistor for resetting, and the reset voltage range is limited, so that the voltage range of the first electrode is limited, but in a circuit structure using the P-type transistor for resetting, the wire defect cannot be caused by the same mechanism. The N-type transistor is adopted for resetting, so that a larger resetting voltage range can be provided, but because of the special structure of the N-type transistor, the line defect can occur due to the mechanism, so that the protection unit is introduced on the basis, and the N-type transistor is matched with the protection unit, so that the line defect can be avoided. The reset unit adopts an N-type transistor, and the driving sub-circuit can adopt a P-type transistor for matching.

By way of example, the transistor may be a thin film transistor, which may employ a semiconductor material as an active layer and a metal as an electrode of the transistor. The transistor may also be a silicon-based transistor, where a monocrystalline silicon wafer is used as a substrate, a source-drain electrode is obtained by local doping of the monocrystalline silicon substrate, a gate electrode is obtained by doping of polycrystalline silicon, and the substrate of the silicon-based transistor may be connected to a power supply signal, for example, the first power supply signal VDD, so that electrical connections between a plurality of transistors in the pixel circuit may be isolated.

Fig. 8 is a schematic block diagram of still another pixel circuit according to an embodiment of the present application. In some embodiments, referring to fig. 8, the first sub-circuit includes a first transistor M1, the second sub-circuit includes a second transistor M2, the driving sub-circuit includes a driving transistor DMOS, the reset unit 420 includes a third transistor M3, and the capacitor unit includes a first capacitor C1 and a second capacitor C2. The first transistor M1 has a gate for receiving a first control signal WS, the first control signal WS controls on and off states of the first transistor M1, a first electrode of the first transistor M1 is electrically connected with the DATA signal line DATA, a first electrode of the first transistor M1 is electrically connected with the DATA signal line 600, a second electrode of the first transistor M1 is electrically connected with the first node N1, a gate of the second transistor M2 is for receiving a second control signal DS, the second control signal DS controls on and off states of the second transistor M2, a first electrode of the second transistor M2 is electrically connected with the fourth node N4, the fourth node N4 is electrically connected with the first power line 700, a second electrode of the second transistor M2 is electrically connected with the second node N2, a first end of the capacitor unit is one end of the first capacitor C1, a second end of the capacitor unit is connected with the first capacitor C1 and the second capacitor C2, and a first end of the capacitor unit is the other end of the second capacitor C2. The first capacitor C1 is electrically connected with the first node N1 and the second node N2 at two ends, the second capacitor C2 is electrically connected with the second node N2 and the fourth node N4 at two ends, the fourth node N4 is electrically connected with the first power line 700, the grid electrode of the driving transistor DMOS is electrically connected with the first node N1, the first electrode of the driving transistor DMOS is electrically connected with the second node N2, the second electrode of the driving transistor DMOS is electrically connected with the third node N3, the grid electrode of the third transistor M3 is used for receiving a third control signal AZ, the third control signal AZ can control the on and off of the third transistor M3, the first electrode of the third transistor M3 is electrically connected with the protection unit 410, and the second electrode of the third transistor M3 is used for being electrically connected with the second power line 900.

It should be noted that the first electrode of the transistor may be one of a source and a drain, and the second electrode of the transistor may be the other of the source and the drain.

For example, referring to fig. 8, the protection unit may include an electric fuse 411, and the electric fuse 411 may be used as a wire. The electric fuse 411 can be blown by a large current, and can function as a fuse to cut off a passage of the large current. The large current usually comes from the large voltage difference at the two ends of the channel, so that the channel with the large voltage difference can be cut off to protect the potentials at the two ends of the channel from being mutually influenced by the conduction of the channel.

The pixel circuit provided by the embodiment of the application can be a silicon substrate, the substrate of the transistor in the pixel circuit can be a monocrystalline silicon substrate, and in order to realize electric isolation between the transistors, a power supply signal can be connected to the substrate of the transistor. For example, the substrates of the first transistor M1, the second transistor M2 and the driving transistor DMOS are all connected to the first power supply signal VDD, and the substrate of the third transistor M3 is connected to the second power supply signal VSS.

Typically, in silicon-based transistors, the source and substrate potentials are not the same. For NMOS tubes, the substrate is usually connected with the lowest potential of the circuit, VBS is less than or equal to 0, VBS is the pressure difference between the substrate and the source electrode, and for PMOS tubes, the substrate is usually connected with the highest potential of the circuit, VBS is more than or equal to 0. At this time, the threshold voltage of the transistor will vary with the potential between its source and the substrate. This effect is known as the "back gate effect".

Taking an NMOS transistor as an example, when the NMOS transistor VBS <0, the change rule of the threshold voltage is that, as Vgs rises, vgs is a voltage difference between the gate and the source of the transistor, the gate attracts electrons inside the substrate to move toward the surface of the substrate, and a depletion layer is generated on the surface of the substrate. When Vgs rises to a certain voltage until reaching a threshold voltage, inversion occurs on the surface of the substrate under the grid electrode, and the NMOS tube starts conducting between the source electrode and the drain electrode. The magnitude of the threshold voltage is related to the charge amount of the depletion layer, and the more the charge amount of the depletion layer is, the more difficult the NMOS transistor is turned on, and the higher the threshold voltage, that is, the voltage required to turn on the NMOS. When VBS <0, the potential difference between the gate and the substrate increases, the thickness of the depletion layer also increases, and the amount of charge in the depletion layer increases, so that the threshold voltage increases. As VBS becomes smaller, the threshold voltage rises, and the drain current becomes smaller with VGS and VDS unchanged. Thus the substrate and gate function similarly and the variation of drain current can be controlled. So we call it a "back gate" action. Some measures may be taken in circuit design to reduce or eliminate the effects of the liner bias, such as shorting the source and substrate, although the effects of the liner bias may be eliminated, which requires support for the circuit and device structures and manufacturing processes.

In addition, the circuit structure can be improved to reduce the lining bias effect. A power signal may also be coupled to the substrate.

In some examples, referring to fig. 8, in the repair driving mode, the first control signal WS is used to control the first transistor M1 to be turned off to turn off the first sub-circuit, the second control signal DS is used to control the second transistor M2 to be turned off to turn off the second sub-circuit, and the third control signal AZ is used to control the third transistor M3 to be turned on to turn on the reset unit.

In some examples, in the repair driving mode, in case that the first and second poles of the light emitting device are shorted, the electric fuse is used to blow by a flowing current to disconnect the reset unit from the third node.

In some examples, referring to fig. 8, in the repair driving mode, the potential of the second power supply signal VSS is a ground potential, and the potential of the common electrode 900 is a negative potential. The difference between the potential of the second power signal VSS and the potential of the common electrode 900 is a first difference, and the voltage value of the first difference may be used to drive the light emitting device 500 to light, so that the electric fuse 411 may be normally turned on in the repair driving mode and the light emitting device may be lighted in case that a short circuit does not occur at both poles of the light emitting device 500. In the case where a short circuit occurs between both electrodes of the light emitting device 500, the light emitting device 500 is not lighted in the repair driving mode, the electric fuse 411 is blown, and the reset sub-circuit is opened.

Fig. 9 is a schematic diagram of a driving timing sequence of a pixel circuit according to an embodiment of the present application, fig. 10 is a schematic diagram of a first stage of an operating state of a pixel circuit according to an embodiment of the present application, fig. 11 is a schematic diagram of a second stage of an operating state of a pixel circuit according to an embodiment of the present application, fig. 12 is a schematic diagram of a third stage of an operating state of a pixel circuit according to an embodiment of the present application, and fig. 13 is a schematic diagram of a fourth stage of an operating state of a pixel circuit according to an embodiment of the present application. For example, referring to fig. 8 to 13, the pixel circuit adopts a 4T2C current type circuit, 4T2C represents 4 transistors and 2 capacitors, and the operating state of the pixel circuit in the display stage may include four stages:

For example, referring to fig. 10, the first stage ① may be regarded as an initialization stage, where at time t ₀ to t ₁, M1 is turned on, M2 is turned on, M3 is turned on, the DATA signal DATA includes an initial DATA signal V _ofs and a display DATA signal V _data, the voltage of the initial DATA signal V _ofs is written into the first capacitor C1 through M1, the voltage of the second node N2 connected to the source of DMOS is V _s＝VDD,V_s and is also the source voltage of DMOS, the voltage of the first node N1 connected to the gate of DMOS is V _g＝V_ofs,V_g and is also the voltage of the gate of DMOS, the voltage of the third node N3 connected to the drain of DMOS is V _D＝V_g+V_th,V_D and is also the voltage of the drain of DMOS, and V _th is the threshold voltage of DMOS, so as to prepare VDD-V _ofs>|V_th l for the next discharging. Vgs=v _ini＝VDD-V_ofs at this time, C1 stores the voltage V _ini.

For example, referring to fig. 10, in the first stage, vss= -5V, vcom= -9V, m3 is turned on, the potential of the third node N3 is-5V, the potential of the first pole 510 of the light emitting device 500 is-5V, the potential of the second pole 520 is-9V, the voltage difference between the two poles of the light emitting device 500 is 4V, it is insufficient to light the light emitting device 500, the two poles of the light emitting device 500 are not turned on, the current flowing through the electric fuse 411 is about pA (picoampere) level, and the electric fuse 411 is not blown.

For example, referring to fig. 11, the second stage 2 is from time t ₁ to time t ₂, and can be considered as a self-discharge stage, M3 is kept on, M1 is turned off first, the potential of the first node N1 floats, M2 is turned off again, the potential voltage of the second node N2 starts to discharge through a loop formed by DMOS and M3, and the potential of the second node N2 drops. Because the potential of the first node N1 floats, the voltage difference between the two ends of the C1 is unchanged, and the potential of the first node N1 is reduced along with the potential of the second node N2. Due to the back gate effect of DMOS, the equivalent threshold voltage of DMOS, |v _{th_EF}|＝a×(VDD-V_s)+|V_th |, a is the back gate coefficient. Vgs remains unchanged, vgs is the voltage difference between the gate and the source of DMOS, V _{th_EF} gradually increases as the potential of the second node N2 decreases, DMOS turns off when V _{th_EF} increases to Vgs, and the second node N2 stops discharging. At this time, |v _{th_EF}|＝a×(VDD-V_s)+|V_th|＝V_ini,

For example, referring to fig. 12, the third stage ③ is from time t ₂ to time t ₃, and can be considered as a gray scale voltage writing and threshold compensation stage, M3 remains on, M2 remains off, M1 turns on, V _data writes to the first node N1, and the voltage of the first node N1 changes from V _ofs to V _data. Since the second node N2 floats, deltaV _s＝(1-b)ΔV_g, whereThe second node N2 voltage becomes:

It should be noted that VDD in bx VDD may be a power signal to which a transistor substrate is connected, and in the present application, a transistor silicon substrate is connected to a first power signal VDD, or may be separately connected to a fixed potential.

For example, referring to fig. 11 and 12, M3 remains on in the second and third phases, and the state of both ends of the electric fuse 411 coincides with the first phase, and the electric fuse is not blown.

Exemplary, referring to FIG. 13, stage 4 is a timing t ₄, where M1 is off, M2 is on, M3 is off, and light emitting device 500 is on, at which time current flows through light emitting device 500 It can be seen that whenAt this time, I ₅₀₀ is independent of the threshold voltage |v _th | of the driving transistor DMOS, i.e., the threshold voltage compensation is completed. W/L is the width to length ratio of the channel of the DMOS, mu _p is the dielectric constant, c _ox is the gate oxide capacitance of the DMOS, i.e., the capacitance of the gate and oxide layer.

For example, referring to fig. 13, in the fourth stage, M3 is opened, the electric fuses 411 and M3 cannot form a path, and no current passes through the electric fuse 411, so that the electric fuse 411 is not blown.

Fig. 14 is a schematic diagram illustrating a fourth stage operation state of another pixel circuit according to an embodiment of the present application. For example, referring to fig. 14, the second power line 901 routed in a horizontal line is exemplified as that in a row of pixel circuits including the first pixel circuit P1, the second pixel circuit P2, the first control signal ws=3.3v, the second control signal ds= -2V, the third control signal az= -5V, the first transistor M1 is turned off, the second transistor M2 is turned on, and the third transistor M3 is turned off in the fourth stage (lighting stage) of the display mode. For example, in a row of pixel circuits, where two poles of the light emitting device 500 connected to the second pixel circuit P2 are shorted, the potential of the second pole 520 of the light emitting device 500 is pulled to-9V, the gate voltage v3g=az= -5V of M3, the source voltage of M3 is pulled to-9V, that is, the source voltage v3s= -9V of M3, the gate-source voltage difference v3gs= -5V- (-9V) of M3=4v > v3th, that is, the gate-source voltage difference of M3 is greater than the threshold voltage V3th, M3 is turned on, the potential of the second power line 901 connected to the drain of M3 is pulled to-8V due to the voltage drop, that is, in the case of the two poles of the light emitting device 500 are shorted, the common signal VCOM is transferred to the second power line 901 in the arrow direction due to the voltage drop, that is pulled to-8V of the second power line 901. At this time, in the pixel circuits to which the remaining normal light emitting devices are connected, for example, the gate potential v3g=az= -5V of the third transistor M3 of the first pixel circuit P1, the drain potential v3d= -8V of the third transistor M3 of the first pixel circuit P1, the voltage difference v3gd= -5V- (-8V) =3v > V3th of the gate and drain of the third transistor M3, the voltage difference between the two electrodes of the light emitting devices is 1V when the gate potential v3g= -8V of the third transistor M3 is turned on, the voltage between the two electrodes of the light emitting device is-8V when the potential between the first electrode 510 of the light emitting device of the first pixel circuit P1 is-9V, and therefore, when the two electrodes of the light emitting device of the second pixel circuit P2 are shorted, the other light emitting devices arranged in the same row as the second pixel circuit P2 cannot be turned on, and a horizontal dark line defect is formed.

Illustratively, if the second power line 901 is a vertical trace, then a vertical dark line is formed, and if there is a horizontal and vertical trace, then a cross line is formed.

Fig. 15 is a schematic timing diagram of a part of control signals in a repair driving mode according to an embodiment of the present application, and fig. 16 is a schematic working state diagram of a pixel circuit in the repair driving mode according to an embodiment of the present application. For example, referring to fig. 16, in the repair driving Mode, the first control signal WS, the second control signal DS, and the first power signal VDD signal float (float), i.e., are in a high-impedance state, i.e., a high-impedance state or a 3V voltage is connected at the first control signal WS, the second control signal DS, and the first power signal VDD signal during a period of Mode On and Mode OFF of the repair driving Mode, but cannot be in a low-level state, for ensuring that current does not reversely flow through the driving transistor to be shunted. The third control signal AZ is set to a constant potential of 3V, the second power supply signal VSS is grounded, that is, az=3v, vss=0v, the common signal VCOM is input with a negative voltage of 12V (-12V), az=3v, vss=0v in the case that the light emitting device 500 is not shorted, the third transistor M3 is turned on, the potential of the first electrode 510 of the light emitting device 500 is 0V, the light emitting device 500 is turned on under a voltage of 12V, the loop current where the electric fuse 411 is located is in nA (nanoampere) stage, and the electric fuse is not blown. Therefore, the circuit operation state of the repair driving mode does not affect the normal light emitting device and the pixel circuit where it is.

Fig. 17 is a schematic diagram of another working state of the pixel circuit in the repair driving mode according to the embodiment of the application. For example, referring to fig. 17, in the repair driving mode, the first control signal WS, the second control signal DS, and the first power signal VDD signal floating (i.e., in a high resistance state), the third control signal AZ is set to a constant potential of 3V, the second power signal VSS is grounded, i.e., az=0v, and the common signal VCOM is input with a negative voltage of 12V (-12V). In the case where both poles of the light emitting device 500 are shorted, the potential of the first pole 510 of the light emitting device 500 is-12V, the potential of one end of the electric fuse 411 connected to the first node N3 is-12V, az=3v, vss=0v, the third transistor M3 is turned on, the potential of one end of the fuse connected M3 is 0V, and the voltage across the electric fuse 411 is-12V.

Fig. 18 is a schematic diagram of another working state of the pixel circuit in the repair driving mode according to the embodiment of the application. For example, referring to fig. 18, in the repair driving mode, in case that the two poles of the light emitting device 500 are shorted, the electric fuse 411 generates an instantaneous mA (milliamp) level large current at a voltage difference of-12V, the electric fuse 411 is blown, the third transistor M3 is disconnected from the light emitting device, and a potential of-12V is not transferred to the second power line 901 through M3, and then in the repair driving mode, a dark line defect becomes a dark spot defect. In the subsequent display mode, the short-circuited light emitting device is not lit in the lighting stage, and since the second power line 901 is disconnected from the short-circuited light emitting device, the short-circuited light emitting device does not affect the potential of the second power line 901, and other normal light emitting devices are normally lit, only dark spot failure occurs, and dark line failure does not occur.

In the display panel, the anode and cathode short circuit of a single sub-pixel can pull down the anode potential of the whole row or column of pixels through the second power line, so that the whole row or column of light emitting devices do not emit light, and a dark line is formed. According to the pixel point circuit provided by the embodiment of the application, a section of electric fuse is added in the quality inspection of the drain electrode of the third transistor and the anode of the light-emitting device, then the voltage difference between the second power supply signal and the public signal is increased in the repairing driving mode, so that the pixel with the shorted cathode and anode generates ampere level heavy current on the electric fuse, the electric fuse is fused to form a short circuit, the connection between the second power supply line and the shorted pixel is cut off, the second power supply line is not pulled down by the public electrode through the light-emitting device, the dark line can be repaired, the dark point of the pixel caused by the shorted cathode and anode is unchanged, and the tolerance of the display to the dark point is far higher than that of the dark line, so that the dark line is repaired into the dark point defect, the display effect of the display panel can be improved, and the yield of the display panel can be improved.

In some embodiments, the material of the electrical fuse may include a semiconductor material or a metal material.

Illustratively, in a silicon-based display panel, the gate electrode of the silicon-based transistor is polysilicon doped, and the electrical fuse may be disposed in the same layer as the gate electrode in the silicon-based display panel. The doping concentration and other doping process parameters of the electrical fuse can be set differently from the doping of the gate according to the resistivity requirement of the electrical fuse, or the polysilicon material of the electrical fuse is not doped. The line widths of the electric fuse and the grid electrode can also be set differently.

For example, the electrical fuse may have a resistivity smaller than that of the gate of the transistor disposed in the same layer, so that the electrical fuse is more likely to break under the same current, and the gate is not broken.

Illustratively, in the thin film display panel, the active layer of the thin film transistor is a semiconductor material, and the electric fuse may be disposed in the same layer as the active layer. The doping process is performed on a part of the active layer to connect the source electrode and the drain electrode, so that the doping of the electric fuse can be differently set with the doping of the active layer, or can be set in the same way, and the required resistivity can be obtained.

For example, the electrical fuse may have a resistivity smaller than that of the semiconductor layer provided in the same layer, so that the electrical fuse is more likely to be broken under the same current, and the semiconductor is not broken.

For example, the pixel circuit may be provided with a plurality of metal layers, a plurality of signal lines, which are generally metal materials, may be provided in the display panel, and the electrical fuse may be provided in the same layer as at least one of the metal layers.

For example, the electrical fuse may have a resistivity smaller than that of the signal line provided in the same layer, and thus the electrical fuse may be more likely to break under the same current, and the signal line may not break.

The metal may include a stacked structure or a single-layer structure of molybdenum, aluminum, molybdenum, titanium, aluminum, titanium, silver, or conductive metal oxide such as indium tin oxide, or the like, for example.

It should be noted that the arrangement of the same layers of the A and the B means that the A and the B are synchronously prepared through the same process, and the film forming and the patterning process preparation can be synchronously performed.

In some embodiments, the electric fuse comprises a first connecting end, a second connecting end and a fuse section, wherein the fuse section, the first connecting end and the second connecting end are of an integrated structure, the fuse section is connected between the first connecting end and the second connecting end, the first connecting end is electrically connected with the third node through a first through hole, the second connecting end is electrically connected with the reset unit through a second through hole, the size of the fuse section in a first direction is smaller than that of the connecting end, the first direction is intersected with the second direction, and the second direction is the length direction of the fuse section.

Fig. 19 is a schematic structural view of an electric fuse provided in an embodiment of the present application. As illustrated in fig. 19, the electrical fuse includes a first connection terminal 412, a second connection terminal 413, and a fuse section 414, and the fuse section 414 is connected between the first connection terminal 412 and the second connection terminal 413, and the first connection terminal 412, the second connection terminal 413, and the fuse section 414 may each have a rectangular shape. The first direction X intersects the second direction Y, which may be the length direction of the fuse section 414. The first connection end 412 and the second connection end 413 have the same size, and the second connection end 413 may have a first size L1 along the first direction X, and the fuse section 414 may have a second size L2 along the first direction X, where the first size L1 is greater than the second size L2. The fuse segment 414 is used to blow under high current, and the width of the fuse segment cannot be too wide. The connecting end is used for connecting other circuit structures, sufficient space is needed to ensure the stability of electric connection, and the width of the connecting end is larger than that of the fuse wire section.

In addition, the larger area of the connecting end can reduce the resistance of the electric fuse so as to ensure that the electric fuse is fused under the action of high current.

Illustratively, referring to fig. 19, the electric fuse further includes a process reference structure 415, the process reference structure 415 is disposed on the same layer as the electric fuse, the process reference structure 415 and the first connection terminal 412 and the second connection terminal 413 are disposed on different sides of the fuse section 414, that is, the process reference structure 415 may be disposed on left and right sides of the fuse section 414, the connection terminal is disposed on upper and lower sides of the fuse section, and an orthographic projection of the process reference structure 415 on the substrate layer and an orthographic projection of the electric fuse on the substrate layer do not overlap. The process reference structure 415 is spaced apart from the first connection terminal 412, the second connection terminal 413, and the fuse segment 414.

Illustratively, the larger connecting segment may also act as a heat sink, leaving the fuse segment cooler at both ends than in the middle region during blowing, the middle portion of the fuse being supposed to be the hottest portion, since it is furthest from the cooling terminal. It can be explained why we see that the blown portion of the fuse is always in the middle, not near either end.

Illustratively, in the process of disposing the electrical fuse, to ensure process accuracy and stability, the area of the pattern structure during the process may be ensured by disposing the process reference structure 415.

Fig. 20 is a schematic structural view of another electric fuse provided in an embodiment of the present application. Illustratively, referring to fig. 20, the first connection terminal 412 is electrically connected to the first node through a first via 416, and the second connection terminal 413 is electrically connected to the third transistor through a second via 417. Each connection terminal can be provided with 4 through holes, more, such as 6 or 3 through holes, and the more the through holes are, the higher the electric connection stability is, and a plurality of through holes can be arranged in the limited area of the connection terminal.

Fig. 21 is a schematic structural view of yet another electric fuse provided in an embodiment of the present application. Illustratively, referring to FIG. 21, the fuse segment 414 is curved in shape.

Fig. 22 is a schematic structural view of still another electric fuse provided in an embodiment of the present application. Illustratively, referring to fig. 22, the fuse segment 414 is in the shape of a fold line.

Fig. 23 is a schematic structural view of an electric fuse provided in an embodiment of the present application. Illustratively, referring to fig. 23, the shape of the fuse segment 414 is saw-tooth shaped to reduce the resistance of the fuse segment.

Because of the limitation of the setting position of the pixel circuit, the size of the space occupied by the pixel circuit can affect the resolution of the display panel, so that the pixel circuit is prevented from occupying a larger area as much as possible, the setting space of the newly-added electric fuse is limited in a limited area space, and a special-shaped fuse section can be arranged for ensuring the relevant electrical parameters of the electric fuse, such as the resistance value, the fusing current and the like.

In some embodiments, the second power supply connection line is used for electrically connecting with a second power supply line, the second power supply line is electrically connected with a plurality of second power supply connection lines, the current density of the second power supply connection line is larger than that of the electric fuse, and the current density of the second power supply line is larger than that of the electric fuse. The second power supply connecting wire and the second power supply wire can not be fused by large current under the condition of fusing the electric fuse, and the stability of the second power supply wire and the second power supply connecting wire is guaranteed.

In some embodiments, the electrical fuse is connected to the first electrode of the light emitting device at a greater distance than the electrical fuse is connected to the second power connection line. The electric fuse is closer to the second power supply connection line than the light emitting device, and it is possible to ensure disconnection of the second power supply line from the current pixel circuit in the event of the electric fuse blowing. In addition, shorting of the electrode of the light emitting device to the electrical fuse can be avoided.

In some embodiments, the electrical fuse blowing voltage ranges from 7.5V to 9V, i.e., the differential pressure across the electrical fuse that causes blowing may be between 7.5V and 9V, for example, may be 8V or 8.5V. In addition, the electrical fuse blowing condition also sterilizes the electrical resistance of the electrical fuse.

In some embodiments, the line width of the fuse segment ranges from 0.02 μm to 0.2 μm, i.e. the second dimension L2 has a value orientation of 0.1 μm to 0.2 μm, for example, may be 0.15 μm, etc., the thickness of the fuse segment ranges from 200nm to 500nm, and the cross-sectional area of the fuse segment may determine the resistance of the fuse segment.

Illustratively, the line width of the fuse segments in a 0.11 μm process precision process may range from 0.1 μm to 0.2 μm. The line width of the fuse segment in the 55nm process may range from 0.02 μm to 0.2 μm.

In some embodiments, the electrical fuse has a sheet resistance ranging from 0.06 to 0.3 ohms/≡ζ, which represents a single block in the sheet resistance test.

In some embodiments, the electric fuse may at least partially surround the third transistor, and the surrounding of the electric fuse to the third transistor may save a space for disposing the electric fuse and may also function to shield the third transistor from signal interference.

In some embodiments, a shielding layer is spaced between the gate of the third transistor and the electric fuse, where the shielding layer is mainly configured to shield interference of signals flowing through the electric fuse on the gate, and especially, the electric fuse is disposed around the third transistor, and a current on the electric fuse may affect induced charges of the gate and the active layer, thereby affecting a threshold voltage of the third transistor, and so on.

In a second aspect of the embodiment of the present application, a display panel is provided, and fig. 24 is a schematic structural diagram of the display panel provided in the embodiment of the present application. As shown in fig. 24, the display panel includes a pixel circuit P as provided in the first aspect, a plurality of pixel circuits arranged in an array, a first electrode of a light emitting device electrically connected to a third node N3 of the pixel circuit P, a data signal line 600 electrically connected to a first sub-circuit of the pixel circuit P, a first power line 700 electrically connected to a second sub-circuit of the pixel circuit P, a second power connection line electrically connected to a reset unit of the pixel circuit, a second power line 901 electrically connected to the plurality of pixel circuits through the second power connection line, and a common electrode electrically connected to a second electrode of the light emitting device.

The common electrode may be an electrode layer disposed entirely, for example. The second power line 901 can also be vertically arranged, and the second power line 901 can also be in a net shape, so that grid dark line defects are easy to occur under the condition of unrepaired. The first power lines 700 may also be disposed laterally, and the second power lines 901 may also be disposed in a grid.

In some embodiments, the ratio of the line width of the second power line 901 to the line width of the fuse segment is greater than or equal to 2, i.e., the line width of the second power line is much greater than the line width of the fuse segment, so that the blowing current of the fuse segment can be prevented from affecting the second power line.

In some examples, a ratio of a line width of the second power connection line to a line width of the fuse segment is greater than or equal to 1. The line width of the second power connection line is also larger than that of the fuse section.

The display panel is provided with the protection unit in the pixel circuit, the protection unit can comprise a resistor, the resistivity of the resistor of the protection unit can be smaller than that of the second power supply connecting wire, and under the condition that the two poles of the light emitting device are in short circuit, the resistor of the protection unit can be broken under the action of high current, and the high current has no influence on the second power supply connecting wire. The circuit breaker of the protection unit can enable the reset unit to be disconnected with the third node, and can avoid that the potential of the second power supply connecting wire is pulled to the short-circuit potential of the first pole under the condition that the first pole and the second pole are short-circuited, and further avoid that the potential of the second power supply wire is pulled to the potential of the first pole, thereby avoiding the defect of the dark line of the whole row, the whole column or the cross shape caused by the short circuit of the local light emitting device. The dark line defect in the display mode of the display panel can be repaired as a dot defect.

In a third aspect of the embodiment of the present application, fig. 25 is a schematic structural diagram of a display device according to an embodiment of the present application. As shown in fig. 25, a display device includes a display panel 1000 as provided in the second aspect.

The display panel that display device adopted, through setting up the protection cell in the pixel circuit, the protection cell can include the resistance, and the resistivity of the resistance of protection cell can be less than the resistivity of second power connecting wire, under the condition that there is the short circuit of luminescent device dipolar, the resistance of protection cell can break under the effect of heavy current, and heavy current does not have the influence to the second power connecting wire. The circuit breaker of the protection unit can enable the reset unit to be disconnected with the third node, and can avoid that the potential of the second power supply connecting wire is pulled to the short-circuit potential of the first pole under the condition that the first pole and the second pole are short-circuited, and further avoid that the potential of the second power supply wire is pulled to the potential of the first pole, thereby avoiding the defect of the dark line of the whole row, the whole column or the cross shape caused by the short circuit of the local light emitting device. The dark line defect in the display mode of the display panel can be repaired as a dot defect.

In a fourth aspect of an embodiment of the present application, there is provided a driving method of a pixel circuit, including:

In a first step, the first step is to provide a first step,

Providing a common signal to the common electrodes, respectively, wherein the common signal is a negative voltage;

and providing a ground voltage to the second power line, wherein a difference between the common signal and the ground signal is a first difference, the first difference being a voltage difference that can light the light emitting device;

and providing a third control signal like the third transistor, wherein the third transistor is turned on under the action of the third control signal so as to repair the bad dark line of the display panel, namely, perform the operation of repairing the driving mode.

Step two, a step two of the method,

After the repair driving mode is completed, driving the display mode of the display panel;

Or alternatively, the first and second heat exchangers may be,

After the repair driving mode is completed, performing test mode driving of the display panel;

In the test mode driving, if there is a dark line defect, the repair driving mode may be performed again.

In some examples, before the first step, test mode driving of the display panel may be performed, and if there is no dark line defect, the repair driving mode is not performed.

Embodiments of the present application may also provide a controller, which may include a memory, which may store a program stored by a computer, and a processor, which may perform steps of a pixel driving method according to the computer program.

The display device provided by the embodiment of the application can comprise a controller and a display panel, wherein the controller is used for driving the display panel.

The foregoing embodiments are merely for illustrating the technical solution of the present application, but not for limiting the same, and although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that modifications may be made to the technical solution described in the foregoing embodiments or equivalents may be substituted for parts of the technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solution of the embodiments of the present application in essence.

While preferred embodiments of the present description have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present specification without departing from the spirit or scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims and the equivalents thereof, the present specification is also intended to include such modifications and variations.

Claims

1. A pixel circuit, comprising:

A first sub-circuit, electrically connected to the first node, the first sub-circuit being used to electrically connect to a data signal line;

a second subcircuit, electrically connected to the second node, the second subcircuit being used to electrically connect to the first power line;

a driving subcircuit, electrically connected to the first node, the second node and a third node respectively, the third node is used to be electrically connected to the first electrode of the light emitting device, and the second electrode of the light emitting device is used to be electrically connected to the common electrode;

a reset subcircuit, the reset subcircuit comprising a protection unit and a reset unit, the protection unit being electrically connected to the reset unit, the protection unit being electrically connected to the third node, the reset unit being used to be electrically connected to a second power connection line, the second power connection line being used to transmit a second power signal;

The protection unit includes a resistor, and a resistivity of the protection unit is smaller than a resistivity of the second power connection line.

2. The pixel circuit according to claim 1, characterized in that:

In the event that the first and second poles of the light-emitting device are short-circuited, the difference between the potential connected to the second power connection line and the potential connected to the common electrode is a first difference, and the first difference is greater than or equal to the driving voltage difference of the light-emitting device. The resistance of the protection unit is used to break the circuit under the action of the current formed between the second power connection line and the third node, and the reset unit is disconnected from the third node.

3. The pixel circuit according to claim 1, characterized in that:

The first sub-circuit, the second sub-circuit, the driving sub-circuit and the reset unit all include transistors, the second sub-circuit includes a capacitor unit, a first end of the capacitor is electrically connected to the first node, a second end of the capacitor unit is electrically connected to the second node, a third end of the capacitor unit is electrically connected to a fourth node, and the fourth node is used to be electrically connected to the first power line;

The driving subcircuit includes a P-type transistor, and the reset unit includes an N-type transistor.

4. The pixel circuit according to claim 3, characterized in that:

The first sub-circuit includes a first transistor, the second sub-circuit includes a second transistor, the driving sub-circuit includes a driving transistor, the reset unit includes a third transistor, and the capacitor unit includes a first capacitor and a second capacitor;

The gate of the first transistor is used to receive a first control signal, the first electrode of the first transistor is used to electrically connect to a data signal line, the second electrode of the first transistor is electrically connected to the first node, the gate of the second transistor is used to receive a second control signal, the first electrode of the second transistor is electrically connected to the fourth node, the second electrode of the second transistor is electrically connected to the second node, the two ends of the first capacitor are electrically connected to the first node and the second node respectively, the two ends of the second capacitor are electrically connected to the second node and the fourth node respectively, the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, the second electrode of the driving transistor is electrically connected to the third node, the gate of the third transistor is used to receive a third control signal, the first electrode of the third transistor is electrically connected to the protection unit, and the second electrode of the third transistor is used to electrically connect to the second power supply connection line.

5. The pixel circuit according to claim 4, characterized in that:

In the case where the first and second electrodes of the light emitting device are short-circuited, the first control signal is used to control the first transistor to be turned off so as to disconnect the first sub-circuit, the second control signal is used to control the second transistor to be turned off so as to disconnect the second sub-circuit, and the third control signal is used to control the third transistor to be turned on so as to turn on the reset unit; and/or,

In the case that the first electrode and the second electrode of the light emitting device are short-circuited, the potential of the second power supply signal is the ground potential, and the potential of the common electrode is a negative potential.

6. The pixel circuit according to any one of claims 1 to 5, characterized in that:

The protection unit includes an electric fuse;

In the case that the first electrode and the second electrode of the light emitting device are short-circuited, the electric fuse is used to be blown under the action of the current flowing therethrough, so that the reset unit is disconnected from the third node.

7. The pixel circuit according to any one of claims 1 to 5, characterized in that:

The protection unit includes an electric fuse;

The electric fuse is arranged in the same layer as at least one signal line, and the resistivity of the electric fuse is smaller than the resistivity of the signal line arranged in the same layer; and/or,

The electric fuse is arranged in the same layer as the gate of the transistor, and the resistivity of the electric fuse is smaller than the resistivity of the gate of the transistor; and/or,

The electric fuse is arranged in the same layer as the semiconductor layer, and the resistivity of the electric fuse is smaller than the resistivity of the semiconductor layer arranged in the same layer.

8. The pixel circuit according to any one of claims 1 to 5, characterized in that:

The protection unit includes an electric fuse;

The electrical fuse comprises a first connection end, a second connection end and a fuse segment, the fuse segment, the first connection end and the second connection end are an integrated structure, and the fuse segment is connected between the first connection end and the second connection end;

The first connection end is electrically connected to the third node through a first via hole, and the second connection end is electrically connected to the reset unit through a second via hole;

The size of the fuse segment in a first direction is smaller than the size of the connection end, the first direction intersects with a second direction, and the second direction is the length direction of the fuse segment.

9. The pixel circuit according to claim 8, further comprising:

A process reference structure, wherein the process reference structure and the electrical fuse are arranged in the same layer;

The process reference structure and the first connection end and the second connection end are respectively arranged on different sides of the fuse segment;

The orthographic projection of the process reference structure on the substrate layer has no overlap with the orthographic projection of the electrical fuse on the substrate layer.

10. The pixel circuit according to claim 9, characterized in that:

The second power connection line is used to be electrically connected to a second power line, and the second power line is electrically connected to a plurality of the second power connection lines;

The current density of the second power connection line is greater than the current density of the electric fuse;

The current density of the second power line is greater than the current density of the electrical fuse.

11. The pixel circuit according to claim 9, characterized in that:

The connection distance between the electric fuse and the first electrode of the light emitting device is greater than the connection distance between the electric fuse and the second power connection line; and/or,

The fuse breaking voltage range is 7.5V to 9V; and/or,

The line width of the fuse segment is in the range of 0.02 μm to 0.2 μm, and the thickness of the fuse segment is in the range of 200 nm to 500 nm; and/or,

The fuse segment is arranged in a curve or a folded line.

12. The pixel circuit according to claim 4, characterized in that:

The protection unit comprises an electric fuse, and when the first electrode and the second electrode of the light emitting device are short-circuited, the electric fuse is used to be melted under the action of the current flowing therethrough, so that the reset unit is disconnected from the third node;

The square resistance of the electrical fuse is in the range of 0.06 to 0.3 ohm/□; and/or,

The electrical fuse at least partially surrounds the third transistor; and/or,

A shielding layer is provided between the gate of the third transistor and the electrical fuse.

13. A display panel, comprising:

The pixel circuit as claimed in any one of claims 1 to 12;

a light emitting device, wherein a first electrode of the light emitting device is electrically connected to a third node of the pixel circuit;

A second power connection line, electrically connected to a reset unit of the pixel circuit;

A second power line, electrically connected to the plurality of pixel circuits via the second power connection line;

The common electrode is electrically connected to the second electrode of the light emitting device.

14. A display device, comprising: the display panel according to claim 13.