CN119233751B - High-density linear capacitor, preparation method thereof and image sensor - Google Patents
High-density linear capacitor, preparation method thereof and image sensor Download PDFInfo
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- CN119233751B CN119233751B CN202411730551.3A CN202411730551A CN119233751B CN 119233751 B CN119233751 B CN 119233751B CN 202411730551 A CN202411730551 A CN 202411730551A CN 119233751 B CN119233751 B CN 119233751B
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- 239000003990 capacitor Substances 0.000 claims abstract description 229
- 238000002360 preparation method Methods 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 56
- 238000004519 manufacturing process Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 9
- 230000010354 integration Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
The invention provides a high-density linear capacitor, a preparation method thereof and an image sensor, comprising providing a basic capacitor structure; A functional pillar is formed on top of the base capacitor structure to divide the top of the base capacitor structure into a first region and a second region, and a multi-layered stacked extended capacitor structure is formed in the first region and the second region. Meanwhile, by forming the functional column, the extended capacitor structure is supported, so that the stability of the extended capacitor structure relative to the basic capacitor structure is ensured, and the problem of smaller capacitor capacity of the conventional capacitor for an image sensor is solved.
Description
Technical Field
The invention relates to the technical field of integrated circuit design and manufacture, in particular to a high-density linear capacitor, a preparation method thereof and an image sensor.
Background
The image sensor is mainly composed of a pixel array and a readout circuit, and the working performance of the image sensor is related to not only quantum efficiency, spectral response, noise, uniformity and the like of the pixel array, but also charge storage, uniformity, linearity, noise, injection efficiency and the like of the readout circuit. Currently, a major factor limiting the operation performance of image sensors is the integration capacitance in the readout circuitry. The integrating capacitor reflects the capacity of the readout circuit for storing charges, and the larger the capacitance capacity is, the more the charge processing capacity of the image sensor can be effectively improved, so that the performances of the image sensor such as dynamic range, signal-to-noise ratio, sensitivity and the like can be improved, and the quality of the finally output image is improved.
However, the integration capacitor used in the readout circuit of the image sensor is usually a single-layer MOS capacitor, and the capacitance density of this structure is usually about 5fF/μm 2, which cannot meet the requirement of 50-100 fF/μm 2 required by the application.
Disclosure of Invention
The invention aims to provide a high-density linear capacitor, a preparation method thereof and an image sensor, so as to at least solve the problem of smaller capacitance and capacity of the capacitor used for the image sensor.
In order to solve the technical problems, the invention provides a preparation method of a high-density linear capacitor, which comprises the following steps:
Providing a basic capacitor structure;
Forming a functional column on top of the base capacitor structure to divide the top of the base capacitor structure into a first region and a second region;
An extended capacitance structure of a multi-layer stack is formed in the first region and the second region.
Optionally, in the method for manufacturing a high-density linear capacitor, the basic capacitor structure is a MOS capacitor, a MOM capacitor, a MIM capacitor, or a PIP capacitor.
Optionally, in the method for manufacturing a high-density linear capacitor, the bottom of the functional pillar is in contact with the top metal layer of the basic capacitor structure.
Optionally, in the method for manufacturing a high-density linear capacitor, the material of the functional column is indium or silicon.
Optionally, in the method for manufacturing a high-density linear capacitor, the method for forming the multilayer stacked extended capacitor structure in the first region and the second region includes:
Preparing a conductive mask and a dielectric mask;
alternately forming a conductive polar plate and a dielectric layer in the first area and the second area from bottom to top by alternately utilizing the conductive mask plate and the dielectric mask plate;
All the conductive plates in the first region are conducted through the first via and the second via Kong Jiaoti, and all the conductive plates in the second region are conducted through the third via and the fourth via Kong Jiaoti.
Optionally, in the method for manufacturing a high-density linear capacitor, one of the first through hole and the second through hole is in contact with the top metal layer of the basic capacitor structure, and one of the third through hole and the fourth through hole is in contact with the top metal layer of the basic capacitor structure.
Optionally, in the method for manufacturing a high-density linear capacitor, the layout structure of the conductive electrode plate and the dielectric layer in the first area is consistent with the layout structure of the conductive electrode plate and the dielectric layer in the second area.
Optionally, in the method for manufacturing a high-density linear capacitor, the conductive mask includes a first conductive mask and a second conductive mask, and the method for alternately forming the conductive polar plate and the dielectric layer in the first area and the second area from bottom to top by alternately using the conductive mask and the dielectric mask sequentially includes:
And alternately forming a first conductive polar plate, a dielectric layer and a second conductive polar plate in the first area and the second area from bottom to top by alternately utilizing the first conductive mask, the dielectric mask and the second conductive mask, wherein the vertical projection of the first conductive polar plate and the vertical projection of the second conductive polar plate are not completely overlapped.
The invention further provides a high-density linear capacitor which is prepared by the preparation method of the high-density linear capacitor, wherein the high-density linear capacitor comprises a basic capacitor structure, a functional column, a first expansion capacitor structure and a second expansion capacitor structure, the functional column is formed on the top of the basic capacitor structure and divides the top of the basic capacitor structure into a first area and a second area, the first expansion capacitor structure is located in the first area and is in contact with the top of the basic capacitor structure, and the second expansion capacitor structure is located in the second area and is in contact with the top of the basic capacitor structure.
Optionally, in the high-density linear capacitor, the bottom of the functional pillar is in contact with the top metal layer of the base capacitor structure.
Optionally, in the high-density linear capacitor, the first expansion capacitor structure and the second expansion capacitor structure each include a plurality of conductive plates and dielectric layers stacked alternately from bottom to top, all the conductive plates of the first expansion capacitor structure are conducted through a first through hole and a second through hole Kong Jiaoti, one of the first through hole and the second through hole is in contact with the top metal layer of the base capacitor structure, all the conductive plates of the second expansion capacitor structure are conducted through a third through hole and a fourth through hole Kong Jiaoti, and one of the third through hole and the fourth through hole is in contact with the top metal layer of the base capacitor structure.
Optionally, in the high-density linear capacitor, the layout structure of the conductive polar plate and the dielectric layer of the first extended capacitor structure is consistent with the layout structure of the conductive polar plate and the dielectric layer of the second extended capacitor structure.
In order to solve the technical problem, the invention also provides an image sensor, which comprises a reading circuit, wherein the integration capacitance in the reading circuit is the high-density linear capacitance as described in any one of the above.
The invention provides a high-density linear capacitor, a preparation method thereof and an image sensor, which comprise the steps of providing a basic capacitor structure; A functional pillar is formed on top of the base capacitor structure to divide the top of the base capacitor structure into a first region and a second region, and a multi-layered stacked extended capacitor structure is formed in the first region and the second region. Meanwhile, by forming the functional column, the extended capacitor structure is supported, so that the stability of the extended capacitor structure relative to the basic capacitor structure is ensured, and the problem of smaller capacitor capacity of the conventional capacitor for an image sensor is solved.
Drawings
FIG. 1 is a graph showing the capacitance values of a multilayer stack capacitor, a MOS capacitor, a PIP capacitor and a MIM capacitor as a function of voltage;
Fig. 2 is a flowchart of a method for manufacturing a high-density linear capacitor according to the present embodiment;
fig. 3 (a) is a schematic structural diagram of the high-density linear capacitor provided in the present embodiment in step S1;
fig. 3 (B) is a schematic structural diagram of the high-density linear capacitor provided in the present embodiment in step S2;
Fig. 3 (C) is a schematic structural diagram of the high-density linear capacitor provided in the present embodiment in step S32;
fig. 3 (D) is a schematic structural diagram of the high-density linear capacitor provided in the present embodiment in step S33;
Wherein, each reference sign is explained as follows:
100-basic capacitance structure, 110-top metal layer, 120-top dielectric layer, 200-functional column, 201-first region, 202-second region, 210-first conductive plate, 220-dielectric layer, 230-second conductive plate, 240-first via, 250-second via, 260-third via, 270-fourth via.
Detailed Description
The high-density linear capacitor, the preparation method thereof and the image sensor provided by the invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
It is noted that "first", "second", etc. in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects so as to describe embodiments of the present invention, and not to describe a specific order or sequence, it should be understood that the structures so used may be interchanged under appropriate circumstances. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
To widen the capacitance, researchers have proposed a multilayer stack capacitor (stack capacitor), i.e., a multilayer vertical "stacking" process, which can obtain a larger capacitance in a smaller space, for example, a PIP (Poly-Insulator-Poly) capacitor and a MIM (Metal-Insulator-Metal) capacitor are stacked in sequence on an existing MOS capacitor structure. Although the capacitance of this capacitor is large, as shown in fig. 1, the capacitance value of the capacitor changes along with the voltage change at two ends of the capacitor, so that the linearity of the capacitor is insufficient, and when the capacitor is applied to an image sensor, signal integration is easily caused to generate nonlinearity, thereby influencing the output image quality.
Based on this, this embodiment provides a method for manufacturing a high-density linear capacitor, as shown in fig. 2, including:
s1, providing a basic capacitor structure;
S2, forming a functional column on the top of the basic capacitor structure to divide the top of the basic capacitor structure into a first area and a second area;
s3, forming a multi-layer stacked expansion capacitor structure in the first area and the second area.
According to the preparation method of the high-density linear capacitor, the multilayer stacked expansion capacitor structure is formed on the existing basic capacitor structure, so that the capacitance capacity of a capacitor in unit area is effectively increased, meanwhile, the function column is formed to support the expansion capacitor structure, stability of the expansion capacitor structure relative to the basic capacitor structure is guaranteed, and the problem that the capacitance capacity of the capacitor used for an image sensor is small in the prior art is solved.
Specifically, in the embodiment, in step S1, a base capacitor structure is provided, where the base capacitor structure may be a MOS capacitor, a MOM capacitor, a MIM capacitor, or a PIP capacitor. The preparation method of the basic capacitor structure is well known to those skilled in the art, and the present application will not be repeated.
In this embodiment, as shown in fig. 3 (a), the basic capacitor structure 100 is formed with a top metal layer 110 and a top dielectric layer 120 on top, wherein the top dielectric layer 120 covers the top metal layer 110. Of course, the top metal layer 110 and the top dielectric layer 120 are the requisite structural layers regardless of the structure of the capacitor.
In practical applications, the material of the top metal layer 110 may be metal, and the material of the top dielectric layer 120 may be silicide such as silicon nitride.
Further, in this embodiment, in step S2, a functional pillar is formed on top of the base capacitor structure to divide the top of the base capacitor structure into a first region and a second region.
Specifically, in order to facilitate effective electrical connection between the output MOS transistor in the pixel array and the integration capacitor of the readout circuit in the subsequent manufacturing process, in this embodiment, the functional column 200 may be used as a wire for both.
At this time, as shown in fig. 3 (B), a contact hole may be formed on the top dielectric layer 120 by a photolithography process using a photolithography plate, the bottom of the contact hole should be the top metal layer 110, and then a functional column 200 having a certain height may be formed on the contact hole. In this way, the functional pillars 200 are formed on top of the base capacitor structure 100, and the area on the left side of the functional pillars 200 is defined as the first area 201, the area on the right side is defined as the second area 202, and the bottom of the functional pillars 200 is in contact with the top metal layer 110 of the base capacitor structure 100.
In practical applications, the material of the functional post 200 may be indium or silicon.
Further, in the present embodiment, in step S3, a method for forming a multilayer stacked extended capacitor structure in a first region and a second region includes:
s31, preparing a conductive mask plate and a dielectric mask plate.
Specifically, in this embodiment, the conductive mask and the dielectric mask may be reused for multiple times, so as to save cost, in consideration of the need to form the multi-layered stacked extended capacitor structure in the first region and the second region.
Preferably, in order to facilitate the connection of the stacked conductive plates in the subsequent process so that the multiple capacitors in the extended capacitor structure can be connected in parallel, in this embodiment, the conductive mask includes a first conductive mask and a second conductive mask, where the conductive plates formed by the first conductive mask and the second conductive mask do not completely overlap in a vertical projection, so that all the conductive plates formed by the first conductive mask can be connected in the area of the misalignment by the through holes, and all the conductive plates formed by the second conductive mask can be connected.
S32, alternately forming a conductive polar plate and a dielectric layer in the first area and the second area from bottom to top by alternately utilizing the conductive mask plate and the dielectric mask plate.
Specifically, in this embodiment, the meaning of alternately forming the conductive electrode plate and the dielectric layer is that a conductive electrode plate is formed by using a conductive mask, then a dielectric layer is formed on the surface of the conductive electrode plate by using a dielectric mask, and then the conductive electrode plate is formed on the surface of the dielectric layer by using the conductive mask.
As described above, when the conductive mask includes a first conductive mask and a second conductive mask, the method for alternately forming the conductive plate and the dielectric layer in the first area and the second area from bottom to top by alternately using the conductive mask and the dielectric mask sequentially includes:
And alternately forming a first conductive polar plate, a dielectric layer and a second conductive polar plate in the first area and the second area from bottom to top by alternately utilizing the first conductive mask, the dielectric mask and the second conductive mask, wherein the vertical projection of the first conductive polar plate and the vertical projection of the second conductive polar plate are not completely overlapped.
As shown in fig. 3 (C), a first conductive plate 210 is formed on the surface of the top dielectric layer 120 by using a first conductive mask, then a dielectric layer 220 is formed on the surface of the first conductive plate 210 by using a dielectric mask, then a second conductive plate 230 is formed on the surface of the dielectric layer 220 by using a second conductive mask, then a dielectric layer 220 is formed on the surface of the second conductive plate 230 by using a dielectric mask, and then the above steps are repeated to form the first conductive plate 210.
The conductive plates (the first conductive plate 210 and the second conductive plate 230) may be made of metal, and the dielectric layer 220 may be made of silicide.
Preferably, in order to ensure stability of the capacitor structure and reduce complexity of the process, in this embodiment, the layout structure of the conductive plate and the dielectric layer in the first region 201 is consistent with the layout structure of the conductive plate and the dielectric layer in the second region 202.
And S33, conducting all the conductive plates in the first area through the first through hole and the second through hole Kong Jiaoti, and conducting all the conductive plates in the second area through the third through hole and the fourth through hole Kong Jiaoti.
Specifically, in the present embodiment, since the conductive plates are divided into the first conductive plate 210 and the second conductive plate 220 in the first area 201, and all the first conductive plates 210 are completely overlapped on the projection in the vertical direction, all the second conductive plates 230 are completely overlapped on the projection in the vertical direction, and all the first conductive plates 210 and the second conductive plates 230 are not completely overlapped on the projection in the vertical direction, as shown in fig. 3 (D), all the first conductive plates 210 can be conducted through the first through holes 240, and all the second conductive plates 230 can be conducted through the second through holes 250. That is, the fact that the conductive plates are alternately conducted by using the through holes means that the conductive plates spaced apart from one conductive plate are conducted by using the same through hole, so that a plurality of parallel MIM structure capacitors can be formed.
Similarly, all of the conductive plates in the second region 202 may be alternately conducted through the third through-holes 260 and the fourth through-holes 270.
In addition, in order to ensure that the extended capacitor structure is connected in parallel with the base capacitor structure to increase the capacitor capacity, in the present embodiment, one of the first via 240 and the second via 250 is in contact with the top metal layer 110 of the base capacitor structure, in the structure shown in fig. 3 (D), the second via 250 is in contact with the top metal layer 110, and one of the third via 260 and the fourth via 270 is in contact with the top metal layer 110 of the base capacitor structure, in the structure shown in fig. 3 (D), the fourth via 270 is in contact with the top metal layer 110.
It should be noted that, although in the capacitor structure shown in fig. 3 (D), the first through hole 240 and the third through hole 260 are formed downward from the first conductive plate 210 of the uppermost layer, in the actual process, in order to reduce the complexity of the process, the through holes may be formed downward from the top of the capacitor structure together with the second through hole 250 and the fourth through hole 270, so that the through hole process may be integrated in one step, and the through hole connection of the corresponding conductive plates is not affected.
In practical application, the stacking times of the conductive electrode plates can be reasonably set according to the requirement of practical capacitance values, and the application is not limited to the practical capacitance values.
And, on top of the extended capacitor structure, a structure of an output MOS transistor in the pixel array may be formed, and a specific preparation method thereof is well known to those skilled in the art, which is not described in detail herein.
According to the preparation method of the high-density linear capacitor, the plurality of MIM structure capacitors are stacked on the existing basic capacitor structure to form the extended capacitor structure, and the extended capacitor structure is organically connected with the basic capacitor structure through the through holes, so that the capacitors are connected in parallel to increase the capacitance capacity while the capacitance area is not increased. In addition, the function column is used for forcefully supporting the expansion capacitor structure, so that the stability of the capacitor structure is improved, and the function column can be used for realizing the electric connection of the capacitor and other components, so that the whole area of a circuit is reduced, and the circuit integration level is improved.
The embodiment also provides a high-density linear capacitor, which is prepared by the preparation method of the high-density linear capacitor, as shown in fig. 3 (D), and comprises a basic capacitor structure 100, a functional pillar 200, a first expansion capacitor structure and a second expansion capacitor structure, wherein the functional pillar 200 is formed on the top of the basic capacitor structure 100 and divides the top of the basic capacitor structure 100 into a first area and a second area, the first expansion capacitor structure is located in the first area and is in contact with the top of the basic capacitor structure 100, and the second expansion capacitor structure is located in the second area and is in contact with the top of the basic capacitor structure 100.
Specifically, in this embodiment, the first extended capacitor structure and the second extended capacitor structure each include a plurality of conductive plates (a first conductive plate 210 and a second conductive plate 230) and a dielectric layer 220 alternately stacked from bottom to top, all conductive plates of the first extended capacitor structure are alternately conducted through a first via 240 and a second via 250, one of the first via 240 and the second via 250 is in contact with the top metal layer 110 of the base capacitor structure 100, all conductive plates of the second extended capacitor structure (the first conductive plate 210 and the second conductive plate 230) are alternately conducted through a third via 260 and a fourth via 270, and one of the third via 260 and the fourth via 270 is in contact with the top metal layer 110 of the base capacitor structure 100.
Preferably, in order to ensure stability of the capacitor structure, in this embodiment, the layout structure of the conductive plate and the dielectric layer of the first extended capacitor structure is identical to the layout structure of the conductive plate and the dielectric layer of the second extended capacitor structure.
In practical applications, the conductive plates on top of the high-density linear capacitor, i.e., the first extended capacitor structure and the second extended capacitor structure, may further have other devices formed thereon for integration with other devices. And if the output MOS tube of the pixel array is integrated and prepared on the conductive polar plate at the top of the first expansion capacitor structure and the second expansion capacitor structure.
The high-density linear capacitor provided by the embodiment effectively increases the capacitance capacity of a capacitor per unit area by forming the multi-layer stacked expansion capacitor structure on the existing basic capacitor structure, and simultaneously, supports the expansion capacitor structure by forming the functional column, ensures the stability of the expansion capacitor structure relative to the basic capacitor structure, and solves the problem of smaller capacitance capacity of the capacitor used for the image sensor.
And, the present embodiment also provides an image sensor including a readout circuit, where an integration capacitance in the readout circuit is a high-density linear capacitance as described above.
In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, so that the same similar parts of each embodiment are referred to each other.
The embodiment provides a high-density linear capacitor, a preparation method thereof and an image sensor, wherein the high-density linear capacitor comprises a basic capacitor structure, a functional column is formed on the top of the basic capacitor structure to divide the top of the basic capacitor structure into a first area and a second area, and a multi-layer stacked expansion capacitor structure is formed in the first area and the second area. Meanwhile, by forming the functional column, the extended capacitor structure is supported, so that the stability of the extended capacitor structure relative to the basic capacitor structure is ensured, and the problem of smaller capacitor capacity of the conventional capacitor for an image sensor is solved.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
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| CN1484840A (en) * | 2000-12-29 | 2004-03-24 | ض� | Multiple tier array capacitor and methods of fabrication therefor |
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| US8094429B2 (en) * | 2009-06-22 | 2012-01-10 | Industrial Technology Research Institute | Multilayer capacitors and methods for making the same |
| CN102412310A (en) * | 2011-05-23 | 2012-04-11 | 上海华力微电子有限公司 | Multilayer stack structure for improving capacitance density and manufacturing method thereof |
| JP5753748B2 (en) * | 2011-08-19 | 2015-07-22 | 日本特殊陶業株式会社 | Multilayer capacitor and wiring board with built-in capacitor |
| JP6319758B2 (en) * | 2013-02-28 | 2018-05-09 | デクセリアルズ株式会社 | Capacitance device, resonance circuit, and electronic equipment |
| CN117241663A (en) * | 2023-09-04 | 2023-12-15 | 中国电子科技集团公司第十三研究所 | Silicon-based multilayer capacitor and preparation method thereof |
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