CN119233115B - Self-adaptive reset large dynamic range pixel structure, image sensor and electronic equipment - Google Patents
Self-adaptive reset large dynamic range pixel structure, image sensor and electronic equipmentInfo
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- CN119233115B CN119233115B CN202411282173.7A CN202411282173A CN119233115B CN 119233115 B CN119233115 B CN 119233115B CN 202411282173 A CN202411282173 A CN 202411282173A CN 119233115 B CN119233115 B CN 119233115B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/58—Control of the dynamic range involving two or more exposures
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/703—SSIS architectures incorporating pixels for producing signals other than image signals
- H04N25/706—Pixels for exposure or ambient light measuring
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- Transforming Light Signals Into Electric Signals (AREA)
Abstract
本发明公开一种自适应复位的大动态范围像素结构、图像传感器以及电子设备。大动态范围像素结构的像素单元通过列反馈实现像素在不同光强场景下复位的自适应控制，实现微光环境的动态范围扩展，包括光电二极管，传输管，电荷存储电容，复位管，第一开关，第一电容，第一源极跟随器，第二开关，行选管，第二源极跟随器，第三开关，锁存器，第一与门，第二与门。通过读出选择电路控制像素依次读出复位电压和信号电压，通过反馈逻辑电路接收列读出电路上一帧的比较结果控制像素是否进行复位。微光环境下，像素不进行复位接着开始下一帧的曝光，通过逐帧累积实现低光强信号量化，从而拓展像素的微光探测能力，提升微光环境下的动态范围。
The present invention discloses a large dynamic range pixel structure with adaptive reset, an image sensor, and an electronic device. The pixel unit of the large dynamic range pixel structure realizes adaptive control of pixel reset in different light intensity scenes through column feedback, thereby realizing dynamic range expansion in low-light environments. The structure includes a photodiode, a transmission tube, a charge storage capacitor, a reset tube, a first switch, a first capacitor, a first source follower, a second switch, a row selection tube, a second source follower, a third switch, a latch, a first AND gate, and a second AND gate. The pixel is controlled to read the reset voltage and signal voltage in sequence through a readout selection circuit, and the comparison result of the previous frame of the column readout circuit is received through a feedback logic circuit to control whether the pixel is reset. In a low-light environment, the pixel does not reset and then starts the exposure of the next frame. The low-light intensity signal is quantized through frame-by-frame accumulation, thereby expanding the low-light detection capability of the pixel and improving the dynamic range in the low-light environment.
Description
Technical Field
The present invention relates to the field of analog integrated circuits, and in particular, to a large dynamic range pixel structure, an image sensor and an electronic device suitable for adaptive reset in a low-light environment.
Background
The dynamic range (DYNAMIC RANGE, DR) is one of the key performance parameters of the CIS, and represents the range of the maximum light intensity signal and the minimum light intensity signal which can be detected by the CIS in the same frame of image at the same time, and the higher the dynamic range, the clearer the contrast details of the image. The micro-light detection capability of the CIS is closely related to the conversion gain of the pixels and the quantization precision of the ADC, the optical signal is very small in a micro-light environment, the optical signal is required to be converted into an electric signal by high conversion gain, and then the electric signal is quantized by the high-precision ADC, so that effective optical information can be obtained. The conversion gain of the pixel is determined by the capacitance of the charge-voltage conversion node, and it is difficult to continue to increase due to parasitic effects. The quantization accuracy of the ADC is determined by the number of bits of the counter, and improving the accuracy of the ADC results in an increase in power consumption and area. Thus, increasing the micro-light detection capability of a pixel presents a significant challenge.
Disclosure of Invention
The invention aims to solve the problems of weak micro-light detection capability and low dynamic range of a micro-light environment of a traditional pixel, and provides a self-adaptive reset large dynamic range pixel structure, an image sensor and electronic equipment. After each frame of exposure is finished, the pixel structure with a large dynamic range in self-adaptive reset judges whether the pixel is reset or not according to the comparison result of the column-level circuit, when the light intensity is low, the pixel structure is not reset, and exposure is continued on the basis of the previous frame, so that the quantification of a low-light signal is realized, and the dynamic range of a low-light environment is expanded.
The first aspect of the present invention provides a self-adaptively reset large dynamic range pixel structure, wherein a pixel unit of the pixel structure realizes self-adaptive control of resetting pixels in different light intensity scenes through column feedback, and realizes dynamic range expansion of a low-light environment, and the pixel structure comprises a photodiode, a transmission tube, a charge storage capacitor, a reset tube, a first switch, a first capacitor, a first source follower, a second switch, a row selection tube, a second source follower, a third switch, a latch, a first and gate and a second and gate;
The positive electrode of the photodiode is connected with the source electrode of the transmission tube, the negative electrode of the photodiode is grounded, the grid electrode of the transmission tube is connected with a transmission control signal, the drain electrode of the transmission tube is connected with one end of the charge storage capacitor, the source electrode of the first switch and the source electrode of the reset tube at the same time, the other end of the charge storage capacitor is grounded, the drain electrode of the first switch is connected with the output of the first AND gate, the other end of the first capacitor is grounded, the drain electrode of the first source electrode follower is connected with the source electrode of the first switch, the source electrode of the first source electrode follower is connected with the source electrode of the second switch, the drain electrode of the second switch is connected with the source electrode of the row selection tube, the drain electrode of the row selection tube is connected with the column bus, the grid electrode of the second source electrode follower is connected with the source electrode of the first switch, the drain electrode of the third switch is connected with the source electrode of the second switch, the source electrode of the second switch is connected with the second AND gate, the output of the second switch is connected with the first AND gate is connected with the first gate, the output of the second latch is connected with the second AND gate is connected with the first gate is connected with the second latch signal, the output of the second AND gate is connected with the second gate signal is the first latch signal.
After each frame of exposure is finished, the pixel unit judges whether the pixel is reset or not according to the comparison result of the column-level circuit, and when the pixel unit is not reset, the exposure is continued on the basis of the previous frame, so that the quantification of the low-light-level signal is realized, and the expansion of the dynamic range of the low-light-level environment is realized.
The pixel is reset by judging whether the pixel is reset or not according to the comparison result of the column-level circuit, judging whether the read reset voltage is smaller than the reference voltage after the difference between the read reset voltage and the signal voltage, if the difference between the reset voltage and the signal voltage is smaller than the reference voltage, the column feedback signal is in a low level, the pixel is not reset, and if the difference between the reset voltage and the signal voltage is larger than the reference voltage, the column feedback signal is in a high level.
The read reset voltage and the signal voltage are subjected to difference through correlated double sampling, and the difference result is compared with the reference voltage to generate a column feedback signal.
The column feedback signal is transmitted to the second AND gate under the control of the latch signal, and the output of the second AND gate controls whether the reset tube resets or not.
The pixel unit performs signal processing, and outputs a reset voltage and a signal voltage, including:
the first capacitor stores the reset voltage of the pixel, the sampling voltage is read out through the first source electrode follower, the charge storage capacitor stores the signal voltage of the pixel, the signal voltage is read out through the second source electrode follower, and when the row selection tube is conducted, the second switch signal and the third switch signal control the reset voltage and the signal voltage to be sequentially read out to the column bus.
The output of the pixel unit is connected with a column readout unit, and the column readout unit comprises a fourth switch, a fifth switch, a second capacitor, a third capacitor, a CDS circuit, a first comparator, a slope generator, a second comparator and a counter;
The column bus Vpix is connected with one end of a fourth switch and one end of a fifth switch, the other end of the fourth switch is simultaneously connected with one end of a second capacitor and a first input end of a CDS circuit, the other end of the fifth switch is simultaneously connected with one end of a third capacitor and a second input end of the CDS circuit, the fourth switch is controlled by a second switch signal, the fifth switch is controlled by a third switch signal S3, the other ends of the second capacitor and the third capacitor are grounded, an output end of the CDS circuit is simultaneously connected with a positive input end of a first comparator and a positive input end of the second comparator, a negative input end of the first comparator is connected with a reference voltage Vref, the output of the first comparator is a column feedback signal FS, the negative input end of the second comparator is connected with an output Vramp of a ramp generator, and the output of the second comparator is connected with a counter.
The signal processing process of the pixel unit comprises the following steps:
When the result of the difference between the reset voltage and the signal voltage output by the pixel of the previous frame is larger than the set threshold Vref through the CDS circuit, the output column feedback signal FS of the first comparator is high level, and during the high level period of the clock signal LATCH, the column feedback signal FS is latched in the LATCH and the latched result is kept until the next high level arrives; when the reset signal RST is pulled high, the second AND gate outputs high level, the reset tube in the pixel is conducted, the transmission tube is conducted, the reset of the photodiode and the charge storage capacitor is carried out, the transmission tube is closed after the reset is completed, the reset signal RST is pulled low, then the exposure stage is carried out, the signal transfer stage is carried out after the exposure is finished, the reset signal RST and the first switch signal S1 are pulled high firstly, the first AND gate and the second AND gate output high level, the reset tube and the first switch are controlled to be conducted, the charge storage capacitor and the first capacitor are reset, the reset signal RST and the first switch signal S1 are pulled low after the reset, the reset voltage is stored in the first capacitor, the transmission signal TX is pulled high afterwards, the transmission tube is conducted, the charge accumulated by the photodiode is transferred to the charge storage capacitor after the transfer is completed, the signal TX is pulled low, the signal voltage is stored in the charge storage capacitor and then the readout stage is carried out, the row selection signal SEL is pulled high during the readout stage, the pixel is kept connected with the column bus ix, the second switch signal S2 is pulled high firstly, the second switch and the fourth switch are conducted, the first capacitor is turned on, the third switch is pulled high, the third switch is turned on, and the third switch is turned on, and then the CDS circuit in the column reading unit makes a difference between the reset voltage stored in the second capacitor and the signal voltage stored in the third capacitor, compares the result after making the difference with a set threshold Vref, feeds back a comparison result FS to the pixel, and controls the reset of the next frame. Meanwhile, the result after the difference is compared with a ramp signal Vramp generated by a ramp generator through a second comparator, and the result is quantized by a counter;
When the result of the difference between the reset voltage and the signal voltage output by the pixel of the previous frame is smaller than the set threshold Vref through the CDS circuit, the column feedback signal FS is low level, the column feedback signal FS is latched in the LATCH during the high level period of the clock signal LATCH, the LATCH outputs low level, when the reset signal RST is pulled high, the output of the second AND gate still keeps low level, the charge storage capacitor still keeps the signal voltage of the previous frame and keeps the exposure, after the exposure is finished, the reset signal RST and the first switch signal S1 are pulled high, the output of the LATCH outputs low level, the output of the first AND gate and the second AND gate still keeps low level, the reset tube and the first switch are not conducted, the reset voltage stored in the first capacitor is not refreshed, then the transmission signal TX is pulled high, the charges accumulated in the exposure period continue to be transferred to the charge storage capacitor, the signal reading process is that the reset voltage is read first and then the signal voltage is read, the second capacitor stores the signal voltage respectively, the difference is carried out through the circuit, the result after the difference is finished, the result is compared with the reference voltage Vref, the result is compared with the result of the comparator and the comparator is quantized by the slope, and the result is quantized by the comparator, and the comparator is compared with the result of the slope Vref after the comparison is generated.
In a second aspect of the invention, an image sensor is provided comprising the adaptive reset high dynamic range pixel architecture.
In a third aspect of the invention, an electronic device is provided comprising the image sensor.
The pixel structure comprises a first capacitor, a first source follower, a charge storage capacitor, a second source follower, a second switch signal, a third switch signal, a column bus, a column feedback signal, a latch signal, a reset tube, a reference voltage and a self-adaptive control system, wherein the first capacitor stores reset voltage of the pixel, the sampling voltage is read out through the first source follower, the charge storage capacitor stores signal voltage of the pixel, the signal voltage is read out through the second source follower, when a row selection tube is conducted, the second switch signal and the third switch signal control the reset voltage and the signal voltage to be read out to the column bus in sequence, the read-out reset voltage and the signal voltage are subjected to difference through correlated double sampling (Correlated Double Sample, CDS), the result of difference is compared with the reference voltage to generate the column feedback signal, the column feedback signal is transmitted to the second AND gate under the control of the latch signal, the output of the second AND gate controls whether the reset tube is reset or not, if the reset voltage is smaller than the reference voltage after the difference is carried out, the column feedback signal is low level, the pixel is not reset, if the difference is larger than the reference voltage after the difference is carried out, the column feedback signal is high level, the pixel is reset, and self-adaptive control of reset under different light intensity scenes is realized through the column feedback, and dynamic range expansion of the pixel is realized.
Drawings
Fig. 1 is a schematic circuit diagram of a pixel unit according to an embodiment of the invention.
Fig. 2 is a circuit diagram of a column readout unit in an embodiment of the present invention.
FIG. 3 is a timing diagram of a pixel unit according to an embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The first aspect of the present invention provides a self-adaptive reset high dynamic range pixel junction, which includes a conventional 4T pixel circuit, a readout selection circuit 201 and a feedback logic circuit 301, wherein the readout selection circuit 201 controls the pixels to sequentially read out a reset voltage and a signal voltage, and the feedback logic circuit 301 receives a comparison result of one frame on a column readout circuit to control whether the pixels are reset. In the low-light environment, the pixels are not reset and then the exposure of the next frame is started, and the low-light intensity signal quantization is realized through the accumulation of frames, so that the low-light detection capability of the pixels is expanded, and the dynamic range in the low-light environment is improved.
Referring to fig. 1, a pixel structure with a large dynamic range for adaptive reset according to an embodiment of the present invention includes a photodiode 101, a transmission tube 102, a charge storage capacitor 103, a reset tube 104, a row selection tube 105, a readout selection circuit 201, and a feedback logic circuit 301. The readout selection circuit 201 includes a first switch 2011, a first capacitor 2012, a first source follower 2013, a second switch 2014, a second source follower 2015, and a third switch 2016. The feedback logic circuit 301 includes a latch 3011, a first and gate 3012, and a second and gate 3013.
Referring to fig. 1, the positive electrode of the Photodiode (PD) 101 is connected to the source of the transfer tube 102, the negative electrode of the photodiode 101 is grounded, the gate of the transfer tube 102 is connected to the transfer control signal TX, the drain of the transfer tube 102 is connected to one end of the charge storage capacitor (FD) 103, the source of the first switch 2011, the source of the reset tube 104, the other end of the charge storage capacitor 103 is grounded, the drain of the first switch 2011 is connected to one end of the first capacitor (C1) 2012, the gate of the first source follower 2013 is connected to the output of the first and gate 3012, the other end of the first capacitor 2012 is grounded, the drain of the first source follower 2013 is connected to the power supply voltage, the source of the first source follower 2013 is connected to the source of the second switch 2014, the drain of the second switch 2014 is connected to the source of the row select tube 105, the gate of the second switch 2014 is connected to the second switch signal S2, the gate of the row selection tube 105 is connected with a row selection signal SEL, the drain of the row selection tube 105 is connected with a column bus Vpix, the gate of the second source follower 2015 is connected with the source of the first switch 2011, the drain of the second source follower 2015 is connected with the source of the third switch 2016, the drain of the third switch 2016 is connected with the source of the row selection tube 105, the gate of the third switch 2016 is connected with the third switch signal S3, the input of the LATCH 3011 is a column feedback signal FS, the clock signal of the LATCH 3011 is a LATCH signal LATCH, the output of the LATCH 3011 is simultaneously connected with one end input of the first and gate 3012 and one end input of the second and gate 3013, the other end input of the first and gate 3012 is the first switch signal S1, the other end input of the second and gate 3013 is a reset control signal RST, the output of the second and the gate of the reset tube 104 are connected, the drain of the reset tube 104 is connected to the supply voltage.
Fig. 2 is a schematic circuit diagram of a column readout unit according to an embodiment of the present invention. Referring to fig. 2, the column readout unit includes a fourth switch 401, a fifth switch 402, a second capacitor 403, a third capacitor 404, a cds circuit 405, a first comparator 406, a ramp generator 407, a second comparator 408, and a counter 409.
Referring to fig. 2, the column bus Vpix is simultaneously connected to one ends of the fourth switch 401 and the fifth switch 402, the other end of the fourth switch 401 is simultaneously connected to one end of the second capacitor 403 and the first input end of the CDS circuit 405, the other end of the fifth switch 402 is simultaneously connected to one end of the third capacitor 404 and the second input end of the CDS circuit 405, the fourth switch 401 is controlled by the second switching signal S2, the fifth switch 402 is controlled by the third switching signal S3, the other ends of the second capacitor 403 and the third capacitor 404 are both grounded, the output end of the CDS circuit 405 is simultaneously connected to the positive input end of the first comparator 406 and the positive input end of the second comparator 408, the negative input end of the first comparator 406 is connected to the reference voltage Vref, the output of the first comparator 406 is the column feedback signal FS, the negative input end of the second comparator 408 is connected to the output Vramp of the ramp generator 407, and the output of the second comparator 408 is connected to the counter 409.
The CDS circuit 405, the first comparator 406, the second comparator 408, the ramp generator 407, and the counter 409 are all known in the art, and are not described in detail herein.
Fig. 3 is a timing diagram of a pixel unit according to an embodiment of the invention.
Referring to fig. 3, when the difference between the reset voltage and the signal voltage outputted from the pixel of the previous frame is greater than the set threshold Vref, the output column feedback signal FS of the first comparator 406 is high, and during the high level period of the clock signal LATCH, the column feedback signal FS is latched in the LATCH 3011 and keeps the latched result until the next high level comes, when the reset signal RST is pulled high, the second and gate 3013 outputs a high level, the in-pixel reset tube 104 is turned on, the transfer tube 102 is turned on, the reset of the photodiode 101 and the charge storage capacitor 103 is performed, the transfer tube 102 is turned off after the reset is completed, the reset signal RST is pulled down, and then the exposure stage is entered, and after the exposure stage is completed, the signal transfer stage is entered, the reset signal RST and the first switch signal S1 are pulled up first, the first and second and gate 3012 output high levels, the reset tube 104 and the first switch 2011 are controlled to be turned on, the charge storage capacitor 103 and the first capacitor 2012 are reset, and the reset signal RST and the first switch signal 2012 are pulled down, and the reset voltage is stored in the first capacitor 2012. The transfer signal TX is pulled up, the transfer tube 102 is turned on, the charge accumulated in the photodiode 101 during the exposure period is transferred to the charge storage capacitor 103, the transfer signal TX is pulled down after the transfer is completed, the signal voltage is stored in the charge storage capacitor 103, and then the readout period is entered, the row select signal SEL is pulled up, the row select tube 105 is turned on, and the pixel is kept connected with the column bus Vpix during the readout period. The second switch signal S2 is pulled up first, the second switch 2014 and the fourth switch 401 are both turned on, the reset voltage stored in the first capacitor 2012 is read out to the second capacitor 403, and then the third switch signal S3 is pulled up, the third switch 2016 and the fifth switch 402 are both turned on, and the signal voltage stored in the charge storage capacitor 103 is read out to the third capacitor 404. Then, the CDS circuit 405 in the column readout unit makes a difference between the reset voltage stored in the second capacitor 403 and the signal voltage stored in the third capacitor 404, compares the result of the difference with the set threshold Vref, and feeds back the comparison result FS to the pixel to control the reset of the next frame. Meanwhile, the result of the difference is compared with a ramp signal Vramp generated by a ramp generator 407 through a second comparator 408 and quantized by a counter 409.
When the result of the difference between the reset voltage and the signal voltage outputted by the pixel of the previous frame through the CDS circuit 405 is smaller than the set threshold Vref, the column feedback signal FS is low, during the period of the high level of the clock signal LATCH, the column feedback signal FS is latched in the LATCH 3011, the LATCH 3011 outputs low level, when the reset signal RST is pulled up, the output of the second and gate 3013 remains low, the charge storage capacitor 103 is not reset, the signal voltage of the previous frame is still saved, the exposure is continued, after the exposure is finished, the reset signal RST and the first switch signal S1 are pulled up, but because the output of the LATCH 3011 is low, the output of the first and second and gate 3012 and the output of the second and gate 3013 remain low, the reset tube 104 and the first switch 2011 are not conducted, the reset voltage stored in the first capacitor 2012 is not refreshed, then the transmission signal TX is pulled up, the charge accumulated in the photo diode 101 continues to be transferred to the charge storage capacitor 103, the readout phase after the transfer is completed, the reset voltage is still read, the reset voltage is compared with the result after the reset signal RST and the second and the third capacitor are compared with the reference frame through the CDS circuit 404, the comparison result is compared with the result of the reference frame comparison result of the pixel by the first and the comparison circuit 406. Meanwhile, the result of the difference is compared with a ramp signal Vramp generated by a ramp generator 407 through a second comparator 408 and quantized by a counter 409.
According to the self-adaptive reset large dynamic range pixel structure provided by the embodiment of the invention, after each frame of exposure is finished, whether the pixel is reset or not is judged according to the comparison result of the column readout circuit, when the light intensity is low, the reset is not performed, and the exposure is continued on the basis of the previous frame, so that the quantification of a low-light signal is realized, and the dynamic range of a low-light environment can be effectively expanded.
A second aspect of the embodiments of the present invention provides an image sensor comprising the adaptive reset high dynamic range pixel structure of the first aspect of the embodiments of the present invention.
A third aspect of the embodiment of the present invention provides an electronic device, including the image sensor of the second aspect of the embodiment of the present invention.
While the fundamental and principal features of the invention and advantages of the invention have been shown and described, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing exemplary embodiments, but may be embodied in other specific forms without departing from the spirit or essential characteristics thereof;
The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (8)
1. The pixel unit of the self-adaptive reset pixel structure with the large dynamic range is characterized by realizing self-adaptive control of resetting of pixels under different light intensity scenes through column feedback and realizing dynamic range expansion of a low-light environment, and the self-adaptive reset pixel structure comprises a photodiode, a transmission tube, a charge storage capacitor, a reset tube, a first switch, a first capacitor, a first source follower, a second switch, a row selection tube, a second source follower, a third switch, a latch, a first AND gate and a second AND gate; the positive electrode of the photodiode is connected with the source electrode of the transmission tube, the negative electrode of the photodiode is grounded, the grid electrode of the transmission tube is connected with a transmission control signal, the drain electrode of the transmission tube is connected with one end of the charge storage capacitor, the source electrode of the first switch and the source electrode of the reset tube, the other end of the charge storage capacitor is grounded, the drain electrode of the first switch is connected with one end of the first capacitor and the grid electrode of the first source follower, the grid electrode of the first switch is connected with the output of the first AND gate, the other end of the first capacitor is grounded, the drain electrode of the first source follower is connected with the power supply voltage, the source electrode of the first source follower is connected with the source electrode of the second switch, the drain electrode of the second switch is connected with the source electrode of the row selection tube, the gate electrode of the row selection tube is connected with the row selection signal, the drain electrode of the row selection tube is connected with the column bus, the gate electrode of the second source follower is connected with the source electrode of the first switch, the drain electrode of the second source follower is connected with the source electrode of the third switch, the latch signal is input to the latch signal of the third switch, the output of the latch is connected with one end input of a first AND gate and one end input of a second AND gate, the other end input of the first AND gate is a first switch signal, the other end input of the second AND gate is a reset control signal, the output of the second AND gate is connected with the grid electrode of the reset tube, the drain electrode of the reset tube is connected with the power supply voltage, after each frame of exposure is finished, the pixel unit judges whether the pixel is reset or not according to the comparison result of the column-level circuit, judges whether the read reset voltage is smaller than the reference voltage or not according to the difference between the read reset voltage and the signal voltage, if the difference between the reset voltage and the signal voltage is smaller than the reference voltage, the column feedback signal is low level, the pixel is not reset, the exposure is continued on the basis of the previous frame, and therefore the quantification of the low-light signal is achieved, the dynamic range of the low-light environment is expanded, and if the difference between the reset voltage and the signal voltage is larger than the reference voltage, the column feedback signal is high level, and the pixel is reset.
2. The adaptive reset high dynamic range pixel architecture of claim 1, wherein the read-out reset voltage and signal voltage are differenced by correlated double sampling, and the differenced result is compared with a reference voltage to generate a column feedback signal.
3. The adaptive reset high dynamic range pixel architecture of claim 2, wherein the column feedback signal is output to a second and gate under control of a latch signal, the output of the second and gate controlling whether the reset tube is reset.
4. A high dynamic range pixel architecture for adaptive reset as claimed in claim 3, wherein said pixel cell performs signal processing to output a reset voltage and a signal voltage, comprising:
the first capacitor stores the reset voltage of the pixel, the sampling voltage is read out through the first source electrode follower, the charge storage capacitor stores the signal voltage of the pixel, the signal voltage is read out through the second source electrode follower, and when the row selection tube is conducted, the second switch signal and the third switch signal control the reset voltage and the signal voltage to be sequentially read out to the column bus.
5. The adaptive reset high dynamic range pixel structure of claim 1, wherein the output of the pixel cell is connected to a column readout cell, the column readout cell comprising a fourth switch, a fifth switch, a second capacitor, a third capacitor, a CDS circuit, a first comparator, a ramp generator, a second comparator, a counter;
The column bus Vpix is connected with one end of a fourth switch and one end of a fifth switch, the other end of the fourth switch is simultaneously connected with one end of a second capacitor and a first input end of a CDS circuit, the other end of the fifth switch is simultaneously connected with one end of a third capacitor and a second input end of the CDS circuit, the fourth switch is controlled by a second switch signal, the fifth switch is controlled by a third switch signal S3, the other ends of the second capacitor and the third capacitor are grounded, an output end of the CDS circuit is simultaneously connected with a positive input end of a first comparator and a positive input end of the second comparator, a negative input end of the first comparator is connected with a reference voltage Vref, the output of the first comparator is a column feedback signal FS, the negative input end of the second comparator is connected with an output Vramp of a ramp generator, and the output of the second comparator is connected with a counter.
6. The adaptive reset high dynamic range pixel architecture of claim 5, wherein the signal processing of the pixel cell comprises:
When the result of the difference between the reset voltage and the signal voltage output by the pixel of the previous frame is larger than the set threshold Vref through the CDS circuit, the output column feedback signal FS of the first comparator is high level, and during the high level period of the clock signal LATCH, the column feedback signal FS is latched in the LATCH and the latched result is kept until the next high level arrives; when the reset signal RST is pulled high, the second AND gate outputs high level, the reset tube in the pixel is conducted, the transmission tube is conducted, the reset of the photodiode and the charge storage capacitor is carried out, the transmission tube is closed after the reset is completed, the reset signal RST is pulled low, then the exposure stage is carried out, the signal transfer stage is carried out after the exposure is finished, the reset signal RST and the first switch signal S1 are pulled high firstly, the first AND gate and the second AND gate output high level, the reset tube and the first switch are controlled to be conducted, the charge storage capacitor and the first capacitor are reset, the reset signal RST and the first switch signal S1 are pulled low after the reset, the reset voltage is stored in the first capacitor, the transmission signal TX is pulled high afterwards, the transmission tube is conducted, the charge accumulated by the photodiode is transferred to the charge storage capacitor after the transfer is completed, the signal TX is pulled low, the signal voltage is stored in the charge storage capacitor and then the readout stage is carried out, the row selection signal SEL is pulled high during the readout stage, the pixel is kept connected with the column bus ix, the second switch signal S2 is pulled high firstly, the second switch and the fourth switch are conducted, the first capacitor is turned on, the third switch is pulled high, the third switch is turned on, and the third switch is turned on, the CDS circuit in the column reading unit makes a difference between the reset voltage stored in the second capacitor and the signal voltage stored in the third capacitor, compares the result after the difference with a set threshold Vref, feeds back a comparison result FS to a pixel, and controls the reset of the next frame;
When the result of the difference between the reset voltage and the signal voltage output by the pixel of the previous frame is smaller than the set threshold Vref through the CDS circuit, the column feedback signal FS is low level, the column feedback signal FS is latched in the LATCH during the high level period of the clock signal LATCH, the LATCH outputs low level, when the reset signal RST is pulled high, the output of the second AND gate still keeps low level, the charge storage capacitor still keeps the signal voltage of the previous frame and keeps the exposure, after the exposure is finished, the reset signal RST and the first switch signal S1 are pulled high, the output of the LATCH outputs low level, the output of the first AND gate and the second AND gate still keeps low level, the reset tube and the first switch are not conducted, the reset voltage stored in the first capacitor is not refreshed, then the transmission signal TX is pulled high, the charges accumulated in the exposure period continue to be transferred to the charge storage capacitor, the signal readout enters the readout stage after the transfer is finished, the reset voltage is read first, the signal voltage is read again, the signal voltage is stored through the second capacitor and the third capacitor respectively, the difference is carried out through the circuit, the result after the difference is carried out, the result is compared with the reference voltage is compared with the first comparator, the result is compared with the reference voltage, and the result is quantized by the comparator, and the result is quantized by the slope comparator, the comparator is compared with the result is generated.
7. An image sensor comprising the adaptive reset high dynamic range pixel architecture of any one of claims 1-6.
8. An electronic device comprising the image sensor of claim 7.
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| CN116684755A (en) * | 2023-04-27 | 2023-09-01 | 天津天芯微系统集成研究院有限公司 | Linear logarithmic pixel circuit based on LOFIC capacitor and high dynamic range implementation method |
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| CN116684755A (en) * | 2023-04-27 | 2023-09-01 | 天津天芯微系统集成研究院有限公司 | Linear logarithmic pixel circuit based on LOFIC capacitor and high dynamic range implementation method |
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