CN119230612B - SiC power device of embedded SBD for improving short-circuit resistance - Google Patents
SiC power device of embedded SBD for improving short-circuit resistance Download PDFInfo
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Abstract
The invention discloses an embedded SBD SiC power device capable of improving short circuit resistance, which comprises a metal drain electrode, an N-type doped semiconductor substrate, an N-type doped semiconductor epitaxial layer, an N-type doped semiconductor JFET region, a grid deep groove, a metal grid, a source shallow groove, SBD metal, a P-type doped semiconductor shielding layer and a metal source electrode. The metal gate is embedded at the top of the gate deep trench. The SBD metal, the source shallow groove and the P-type doped semiconductor shielding layer can reduce the current density of the device in short circuit, reduce the temperature of the device in short circuit, avoid thermal breakdown of the device and improve the short circuit resistance of the device. In addition, the grid deep groove filled with the high-K dielectric medium can modulate the potential distribution of the drift region so as to ensure low on-resistance and high reverse breakdown voltage, thereby improving the on-resistance and short-circuit resistance of the device and effectively reconciling the contradictory relation of the on-resistance and the short-circuit resistance.
Description
Technical Field
The invention relates to the technical field of silicon carbide power devices, in particular to an embedded SBD SiC power device capable of improving short circuit resistance.
Background
Silicon carbide (SiC) power devices are widely used in electric vehicles, renewable energy sources, industrial automation, power electronics, aerospace, portable electronic devices, power transmission, medical devices and other scenes due to their lower on-resistance and switching loss, and superior performances such as better switching frequency and thermal management capability.
In recent years, the integration of schottky diodes (SBDs) into SiC power devices has become an important trend to improve device performance. SBDs can significantly reduce switching losses and conduction losses with their very low forward voltage drop and fast reverse recovery characteristics. The integrated design not only optimizes the power conversion efficiency, but also improves the thermal management capability of the system and simplifies the circuit design.
SiC power devices often operate in a high voltage, high current scenario, with short circuit stress being a key factor affecting their reliability. When a short circuit occurs, the following short circuit hazard occurs, specifically:
1. The device may be subjected to currents up to several times its rated value instantaneously, and this increased current may cause the internal temperature of the device to rise rapidly, possibly exceeding its thermal limit, causing thermal failure.
2. Short circuit conditions exceeding the rated voltage may cause breakdown phenomena, damaging the insulating layer.
3. Excessive carrier injection may lead to instability in the device turn-on characteristics, which in turn affects overall performance.
4. Thermal expansion mismatch can create mechanical stresses that lead to cracking or delamination at the material interface.
5. The aging process of the device is accelerated, and the service life of the device is shortened.
Based on the short-circuit hazard, the SiC power device generally introduces overcurrent and overvoltage protection measures such as fuses or piezoresistors in a circuit in practical application. However, although there are methods to cope with short circuits, improving the short circuit resistance of the device itself is still a core element to ensure system reliability, performance and safety.
The traditional method for improving the short-circuit resistance of the device is to increase the on-resistance, so that the short-circuit current density of the device is reduced, and the circuit is prevented from being damaged. Therefore, the improvement of the short-circuit resistance of the device and the reduction of the on-resistance have contradictory relation, and in order to optimize the short-circuit resistance of the device and the on-resistance of the device at the same time, the invention provides the SiC power device of the embedded SBD for improving the short-circuit resistance.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the SiC power device with the embedded SBD for improving the short-circuit resistance, which combines the power consumption and the short-circuit resistance of the device by adopting the step-type SBD metal in the shallow trench of the source electrode and filling the high-K material in the deep trench of the grid electrode.
In order to solve the technical problems, the invention adopts the following technical scheme:
A SiC power device with an embedded SBD for improving short circuit resistance comprises a metal drain electrode, an N-type doped semiconductor substrate, an N-type doped semiconductor epitaxial layer, an N-type doped semiconductor JFET region, a grid deep groove, a metal grid, a source shallow groove, SBD metal, a P-type doped semiconductor shielding layer and a metal source electrode.
The metal drain electrode, the N-type doped semiconductor substrate, the N-type doped semiconductor epitaxial layer, the N-type doped semiconductor JFET region and the metal source electrode are sequentially distributed from bottom to top.
The grid deep groove and the source shallow groove are longitudinally and penetratingly arranged at two sides of the N-type doped semiconductor JFET region, and the bottoms of the grid deep groove and the source shallow groove extend into the N-type doped semiconductor epitaxial layer right below the N-type doped semiconductor JFET region, wherein the depth of the grid deep groove is larger than that of the source shallow groove, high-K dielectric is filled in the grid deep groove, and a metal source is filled in the source shallow groove.
The metal gate is embedded at the top of the gate deep trench.
The SBD metal is in a stepped shape and embedded in the metal source electrode, and comprises an SBD transverse part and an SBD longitudinal part which are integrally arranged, wherein the SBD longitudinal part extends into the source shallow trench in a mode of being attached to the side wall of the source shallow trench, an SBD gap is formed between the SBD longitudinal part and the bottom surface of the source shallow trench, the SBD transverse part is positioned at the bottom of the metal source electrode, and the lower surface of the SBD transverse part is tightly attached to the upper surface of the N-type doped semiconductor JFET region.
The P-type doped semiconductor shielding layer is a stepped type and comprises a longitudinal shielding part and a transverse shielding part, wherein the longitudinal shielding part is arranged below the SBD longitudinal part and is overlapped with the N-type doped semiconductor JFET region on the side wall of the shallow trench of the source electrode, and the transverse shielding part is arranged on the top of the N-type doped semiconductor epitaxial layer overlapped with the bottom of the shallow trench of the source electrode.
An interlayer insulating medium is arranged between the metal grid electrode and the metal source electrode.
The semiconductor device further comprises a P-type doped semiconductor well, wherein the P-type doped semiconductor well is arranged in the N-type doped semiconductor JFET region between the grid deep groove and the source shallow groove.
The N-type doped semiconductor source electrode contact region and the P-type doped semiconductor ohmic contact region are arranged at the top of the N-type doped semiconductor JFET region right above the P-type doped semiconductor trap in parallel.
The longitudinal depth of the metal gate exceeds the longitudinal depth of the P-type doped semiconductor well.
The length of the lateral part of the SBD is not more than 15% of the lateral width of the N-type doped semiconductor epitaxial layer, and the length of the longitudinal part of the SBD is not more than 150% of the longitudinal depth of the P-type doped semiconductor well.
The width of the source shallow groove is not less than 5% of the transverse width of the N-type doped semiconductor epitaxial layer and not more than 20% of the transverse width of the N-type doped epitaxial layer, and the depth of the source shallow groove is not less than 30% of the longitudinal depth of the P-type doped semiconductor well and not more than 225% of the longitudinal depth of the P-type doped semiconductor well.
The SBD gap is not less than 25% of the longitudinal depth of the P-type doped semiconductor well and not more than 75% of the longitudinal depth of the P-type doped semiconductor well.
The width of the grid deep groove is not less than 10% of the transverse width of the N-type doped semiconductor epitaxial layer and not more than 20% of the transverse width of the N-type doped epitaxial layer, and the depth of the grid deep groove is not less than 30% of the longitudinal depth of the N-type doped semiconductor epitaxial layer and not more than 80% of the longitudinal depth of the N-type doped epitaxial layer.
The doping concentration of the P-type doped semiconductor shielding layer is between 0.6X10 17 ~2×1017cm-3.
The invention has the advantages that the arrangement of the step-type SBD metal, the source shallow groove and the P-type doped semiconductor shielding layer can reduce the current density of the device in the short circuit process, reduce the temperature of the device in the short circuit process, avoid the thermal breakdown of the device and improve the short circuit resistance of the SiC power device. In addition, the grid deep groove filled with the high-K dielectric medium can modulate the potential distribution of the drift region so as to ensure low on-resistance and high reverse breakdown voltage, thereby improving the on-resistance and short-circuit resistance of the SiC power device and effectively reconciling the contradictory relation of the on-resistance and the short-circuit resistance.
Drawings
Fig. 1 shows a schematic structural diagram of an SBD embedded SiC power device of the present invention for improving short circuit resistance.
Fig. 2 shows a schematic structural diagram of a conventional SiC power device with SBD (conventional device).
Fig. 3 shows a graph of short-circuit endurance time for a conventional device versus a device provided by an embodiment of the present invention.
Fig. 4 shows a comparison of the temperature change of the SBD area with time for a conventional device and the device provided by the embodiment of the present invention, which turns off the gate after being subjected to a short-circuit stress of 5 ms.
Fig. 5 shows a graph of the variation of the specific on-resistance of the device according to the embodiment of the invention along with the depth of the gate deep trench.
Fig. 6 shows a graph of the quality factor of the device according to the embodiment of the invention along with the depth of the gate deep trench.
Fig. 7 shows a schematic structure of the N-doped semiconductor epitaxial layer after epitaxial growth in step 1.
Fig. 8 shows a schematic structure of the gate deep trench and the source shallow trench after etching in step 2.
Fig. 9 shows a schematic structure of the N-doped semiconductor JFET region after fabrication in step 3.
Fig. 10 shows a schematic structure of the P-doped semiconductor well after the P-doped semiconductor well is fabricated in step 4.
Fig. 11 shows a schematic structure of the N-type doped semiconductor source contact region and the P-type doped semiconductor ohmic contact region after the fabrication of the N-type doped semiconductor source contact region and the P-type doped semiconductor ohmic contact region in step 5.
Fig. 12 shows a schematic structure of the P-type doped semiconductor shielding layer after the preparation of the P-type doped semiconductor shielding layer in step 6.
Fig. 13 shows a schematic structure after the completion of the filling of the two trenches in step 7.
Fig. 14 shows a schematic structure of the gate embedded groove and the SBD embedded groove after etching in step 8.
Fig. 15 shows a schematic structure of the metal gate and SBD metal after the preparation of the metal gate and SBD metal in step 9 is completed.
Fig. 16 shows a schematic structural diagram of the interlayer insulating medium after the preparation in step 10.
Fig. 17 shows a schematic structure of the metal source and the metal drain after the preparation of the metal source and the metal drain in step 11.
The method comprises the following steps:
1. The semiconductor device comprises a metal drain electrode, a 2-N type doped semiconductor substrate, a 3-N type doped semiconductor epitaxial layer, a 4-N type doped semiconductor JFET region, a 5.P type doped semiconductor well, a 6-N type doped semiconductor source electrode contact region, a 7-P type doped semiconductor ohmic contact region, a grid deep groove, a 9-metal grid electrode, a 10-source electrode shallow groove, 11-SBD metal, a 12-P type doped semiconductor shielding layer, a 13-metal source electrode and a 14-interlayer insulating medium.
Detailed Description
The invention will be described in further detail with reference to the accompanying drawings and specific preferred embodiments.
In the description of the present invention, it should be understood that the terms "left", "right", "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and "first", "second", etc. do not indicate the importance of the components, and thus are not to be construed as limiting the present invention. The specific dimensions adopted in the present embodiment are only for illustrating the technical solution, and do not limit the protection scope of the present invention.
As shown in fig. 1, an embedded SBD SiC power device for improving short circuit resistance includes a metal drain 1, an N-type doped semiconductor substrate 2, an N-type doped semiconductor epitaxial layer 3, an N-type doped semiconductor JFET region 4, a P-type doped semiconductor well 5, an N-type doped semiconductor source contact region 6, a P-type doped semiconductor ohmic contact region 7, a gate deep trench 8, a metal gate 9, a source shallow trench 10, an SBD metal 11, a P-type doped semiconductor shield layer 12, a metal source 13, and an interlayer insulating medium 14.
The metal drain electrode, the N-type doped semiconductor substrate, the N-type doped semiconductor epitaxial layer, the N-type doped semiconductor JFET region and the metal source electrode are sequentially distributed from bottom to top.
The grid deep groove and the source shallow groove are longitudinally and penetratingly arranged at two sides of the N-type doped semiconductor JFET region, and the P-type doped semiconductor well is arranged in the N-type doped semiconductor JFET region between the grid deep groove and the source shallow groove. Wherein the P-doped semiconductor well is completely surrounded by the N-doped JFET region.
The bottoms of the grid deep groove and the source shallow groove extend into the N-type doped semiconductor epitaxial layer right below, wherein the depth of the grid deep groove is larger than that of the source shallow groove, the depth of the grid deep groove is not smaller than 30% of the longitudinal depth of the N-type doped semiconductor epitaxial layer and not larger than 80% of the longitudinal depth of the N-type doped epitaxial layer, and the width of the grid deep groove is not smaller than 10% of the transverse width of the N-type doped semiconductor epitaxial layer and not larger than 20% of the transverse width of the N-type doped epitaxial layer. In this embodiment, the width of the gate deep trench is preferably 1.2 μm and the depth is preferably 7 μm.
The gate deep trench is filled with a high-K dielectric, preferably HfO 2.
The metal source is filled in the source shallow groove, the width of the source shallow groove is not less than 5% of the transverse width of the N-type doped semiconductor epitaxial layer and not more than 20% of the transverse width of the N-type doped epitaxial layer, and the depth of the source shallow groove is not less than 30% of the longitudinal depth of the P-type doped semiconductor well and not more than 225% of the longitudinal depth of the P-type doped semiconductor well. In this embodiment, the width of the source shallow trench is preferably 0.4 μm and the depth is preferably 0.8 μm.
The metal gate is embedded at the top of the gate deep trench, and the longitudinal depth of the metal gate exceeds the longitudinal depth of the P-type doped semiconductor well. The width of the metal gate is smaller than the width of the gate deep trench, and thus the metal gate is not in contact with the P-type doped semiconductor well.
The N-type doped semiconductor source electrode contact area and the P-type doped semiconductor ohmic contact area are arranged at the top of the N-type doped semiconductor JFET area right above the P-type doped semiconductor trap in parallel. In this embodiment, the right side of the N-type doped semiconductor source contact area is closely connected with the left side of the P-type doped semiconductor ohmic contact area, and both are completely surrounded by the P-type doped semiconductor well 5.
The SBD metal is stepped and embedded in the metal source, i.e. in direct contact with the metal source, in this embodiment, the SBD metal is preferably titanium metal.
The SBD metal comprises an SBD transverse part and an SBD longitudinal part which are integrally arranged.
The SBD longitudinal part is attached to the side wall of the source shallow trench and extends into the source shallow trench, and a SBD gap is formed between the SBD longitudinal part and the bottom surface of the source shallow trench. Further, the length of the SBD longitudinal part is not more than 150% of the longitudinal depth of the P-type doped semiconductor well, and the SBD gap is not less than 25% of the longitudinal depth of the P-type doped semiconductor well and not more than 75% of the longitudinal depth of the P-type doped semiconductor well. In this embodiment, the SBD longitudinal length is preferably 0.4 μm and the SBD gap is 0.4. Mu.m.
The lateral part of the SBD is positioned at the bottom of the metal source, namely the lower surface of the lateral part of the SBD is clung to the upper surface of the N-type doped semiconductor JFET region, and the left side is aligned with the right side boundary of the P-type doped semiconductor ohmic contact region. Further, the length of the lateral part of the SBD is not more than 15% of the lateral width of the N-type doped semiconductor epitaxial layer. In this embodiment, the SBD lateral length is preferably 1 μm.
The P-type doped semiconductor shielding layer is a stepped type and comprises a longitudinal shielding part and a transverse shielding part, wherein the longitudinal shielding part is arranged below the SBD longitudinal part and is overlapped with an N-type doped semiconductor JFET region on the side wall of a shallow trench of a source electrode, and the transverse shielding part is arranged on the top of an N-type doped semiconductor epitaxial layer overlapped with the bottom of the shallow trench of the source electrode. Further, the doping concentration of the P-type doped semiconductor shielding layer is preferably between 0.6x10 17 ~2×1017cm-3. In this embodiment, 1×10 17cm-3 is preferable.
The interlayer insulating medium is arranged between the metal grid electrode and the metal source electrode, preferably SiO 2, and is used for realizing electric isolation.
Principle of operation
As shown in fig. 2, if the conventional SiC power device with SBD (hereinafter referred to as conventional device) is intended to improve the short-circuit resistance, it is often necessary to improve the on-resistance of the device by reducing the doping concentration of the drift region of the device, so that the saturation current density during the short-circuit of the device is reduced, and the temperature during the short-circuit of the device is further reduced, so as to improve the short-circuit resistance of the device, and the power loss during the normal operation of the device is definitely increased by increasing the on-resistance of the device.
The SiC power device with embedded SBD for improving short circuit resistance (hereinafter referred to as the device provided by this embodiment) provided in this embodiment is fabricated by opening a source shallow trench, adding a step-type SBD metal in the source shallow trench, and introducing a P-type doped semiconductor shielding layer at the bottom of the source shallow trench and at the lower half of the sidewall. By playing the shielding effect of the P-type doped semiconductor well and the P-type doped semiconductor shielding layer on short circuit current, the saturation current density during short circuit is effectively reduced, and the design of the source shallow groove does not obviously increase the on-resistance of the device.
When a short circuit occurs, for the SiC power device embedded with the SBD, the leakage current is mainly the thermionic emission current J SBD generated by the SBD, and the specific calculation formula is as follows:
Where A is the PCS, T is the temperature of the SBD region, q is the electron charge amount, Is the barrier height, k is the thermal conductivity,Is the barrier height variation, C T is the tunneling coefficient, and E M is the maximum electric field strength of the SBD region.
From the above formula, it can be seen that the thermionic emission current generated by the SBD can be effectively reduced by lowering the temperature of the SBD region. According to the invention, the SBD metal with the ladder-type structure is adopted, and the P-type doped semiconductor shielding layer and the P-type doped semiconductor well are utilized to extrude an SBD current flow path in short circuit, so that the temperature in the short circuit of the device is effectively reduced, the thermionic emission current is inhibited, and the short circuit resistance of the device is effectively improved.
As shown in fig. 3, TCAD short-circuit stress simulation was performed on the device provided in this embodiment and the conventional device under the conditions of the gate-source voltage V gs =15V and the drain-source voltage V ds =400V, respectively. It can be seen that:
A. For conventional devices
The gate is turned off after being subjected to a short-circuit stress of 4 mus, and the device short-circuit current density gradually decreases to 0 as time goes on.
After being subjected to a short-circuit stress of 5 mus, the short-circuit current density drops rapidly to a low level due to gate turn-off, but then starts to rise gradually with time.
The gate is turned off after receiving a short-circuit stress of 8 mus, and the device short-circuit current rises rapidly until thermal damage occurs.
B. for the device provided in this embodiment
The gate is turned off after being subjected to a short-circuit stress of 7 mus, and the device short-circuit current gradually decreases to a lower level and remains stable.
The gate is turned off after being subjected to a short-circuit stress of 8 mus and the device is not normally turned off.
The gate is turned off after receiving a short-circuit stress of 11 mus, and the device short-circuit current increases significantly over time.
It is therefore considered that the short-circuit stress resistance time of the device provided in this embodiment is improved to 7 μs compared to the short-circuit stress resistance time of 4 μs of the conventional device.
Fig. 4 shows the results of temperature simulation for the device provided in this embodiment and the SBD area of the conventional device. The gate is turned off after bearing the short-circuit stress of 5 mu s, the temperature of the device is increased due to the gradual increase of the thermionic emission current density of the SBD area along with time, and further the thermionic emission current density is increased, and the device finally suffers from thermal failure under the effect of positive temperature feedback, while the temperature of the SBD area of the device provided by the embodiment is gradually reduced along with time.
Furthermore, the introduction of the gate deep trench filled with the high-K dielectric can effectively reduce the specific on-resistance R on,sp of the device, but the specific on-resistance of the device gradually increases along with the increase of the trench depth, as shown in fig. 5, and as shown in fig. 6, the device has the maximum quality factor.
A manufacturing method of an embedded SBD SiC power device for improving short-circuit resistance comprises the following steps.
And step 1, epitaxially growing an N-type doped semiconductor epitaxial layer, namely epitaxially growing an N-type doped semiconductor epitaxial layer 3 on the N-type doped semiconductor substrate 2 to form a basic structure shown in figure 7.
And 2, etching the grid deep groove and the source shallow groove, namely etching the grid region and the source region by using a reactive ion etching process to form two grooves of the grid deep groove and the source shallow groove respectively as shown in figure 8. However, it should be noted that since the two trenches have different depths, two etches are required using different reticles.
And step 3, preparing an N-type doped semiconductor JFET region, wherein nitride is used as a mask for ion implantation because an active region is 4H-SiC. Considering the stress of nitride on SiC, oxide with a thickness of 0.1 μm is deposited first on the N-type doped semiconductor epitaxial layer 3, and then nitride with a thickness of 1 μm is deposited. Then, the photoresist is used as a mask to etch away the nitride and oxide on the active region between the gate deep trench 8 and the source shallow trench 10, then all the photoresist is etched away, the N-type impurity ion implantation and high temperature annealing are performed on the region without nitride protection to form the N-type doped semiconductor JFET region 4, and then the remaining nitride and oxide are completely etched away, as shown in fig. 9.
And 4, preparing a P-type doped semiconductor well, namely repeating the operations of depositing the oxide and the nitride, taking the photoresist as a mask, etching away part of the nitride and the oxide on the N-type doped semiconductor JFET region 4, etching away all the photoresist, performing P-type impurity ion implantation and high-temperature annealing on the region without nitride protection to form a P-type doped semiconductor well 5, and completely etching away the rest of the nitride and the rest of the oxide, as shown in figure 10.
Step 5, preparing an N-type doped semiconductor source electrode contact region and a P-type doped semiconductor ohmic contact region
A. preparation of N-doped semiconductor source contact region
The above operations of depositing oxide and nitride are repeated, the nitride and oxide on the left part of the P-type doped semiconductor well 5 are etched by using the photoresist as a mask, then all the photoresist is etched, high-dose N-type impurity ion implantation and high-temperature annealing are performed on the area without nitride protection, so as to form an N-type doped semiconductor source electrode contact area 6, and then the remaining nitride and oxide are completely etched.
B. Preparation of P-type doped semiconductor ohmic contact region
The above-mentioned operations of depositing oxide and nitride are repeated, the right part of nitride and oxide on the P-type doped semiconductor well 5 is etched by using the photoresist as a mask, then all the photoresist is etched, high-dose P-type impurity ion implantation and high-temperature annealing are performed on the area without nitride protection, so as to form the P-type doped semiconductor ohmic contact region 7, and then the remaining nitride and oxide are completely etched, as shown in fig. 11.
And 6, preparing a P-type doped semiconductor shielding layer, namely repeating the operations of depositing oxide and nitride, taking photoresist as a mask, etching the nitride and oxide on the source shallow trench 10, etching all the photoresist, performing P-type impurity ion implantation and high-temperature annealing on the area of the source shallow trench 10 without nitride protection to form a P-type doped semiconductor shielding layer 12, and then completely etching the rest nitride and oxide, as shown in fig. 12.
Step 7, filling the trench, namely, as shown in fig. 13, adopting a magnetron sputtering deposition device to deposit HfO 2 to fill the deep trench 8 of the gate, and then using a specific mask to deposit a metal source to the top at the shallow trench 10 of the source. Considering the interfacial effect between HfO 2 and SiC, a layer of SiO 2 is prepared as a buffer layer prior to depositing HfO 2.
Step 8, etching the embedded groove of the grid and the embedded groove of the SBD
A. Etching a gate embedded groove, namely etching a shallow gate embedded groove on HfO 2 by using reactive ion etching
B. And (4) etching the SBD embedded groove, namely etching the metal source electrode deposited in the step (7) to a set height to form the SBD embedded groove, wherein the etched SBD embedded groove is shown in fig. 14.
Step 9, preparing a metal gate and SBD metal, namely respectively depositing the metal gate 9 and the SBD metal 11 in the gate embedded groove and the SBD embedded groove by using different masks, as shown in fig. 15. Wherein the SBD lateral part of the SBD metal is deposited on the upper surface of the N-type doped semiconductor JFET region.
Step 10, preparing an interlayer insulating medium, namely depositing SiO 2 on the metal grid 9 by using a chemical vapor deposition device by taking photoresist as a mask as an interlayer insulating medium 14, as shown in fig. 16.
Step 11, preparing a metal source electrode and a metal drain electrode, namely depositing metal in a source electrode area and a drain electrode area and performing annealing treatment to form a metal source electrode 13 and a metal drain electrode 1, wherein the final structure of the embedded SBD SiC power device with the short-circuit resistance improved provided by the embodiment is shown in fig. 17.
The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific details of the above embodiments, and various equivalent changes can be made to the technical solution of the present invention within the scope of the technical concept of the present invention, and all the equivalent changes belong to the protection scope of the present invention.
Claims (10)
1. The SiC power device with the embedded SBD for improving the short circuit resistance is characterized by comprising a metal drain electrode, an N-type doped semiconductor substrate, an N-type doped semiconductor epitaxial layer, an N-type doped semiconductor JFET region, a grid deep groove, a metal grid, a source shallow groove, SBD metal, a P-type doped semiconductor shielding layer and a metal source electrode;
the metal drain electrode, the N-type doped semiconductor substrate, the N-type doped semiconductor epitaxial layer, the N-type doped semiconductor JFET region and the metal source electrode are sequentially distributed from bottom to top;
The grid deep groove and the source shallow groove are longitudinally and penetratingly arranged at two sides of the N-type doped semiconductor JFET region, and the bottoms of the grid deep groove and the source shallow groove extend into the N-type doped semiconductor epitaxial layer right below the N-type doped semiconductor JFET region, wherein the depth of the grid deep groove is larger than that of the source shallow groove, the high-K dielectric medium is filled in the grid deep groove, and the metal source is filled in the source shallow groove;
the metal grid is embedded at the top of the grid deep groove;
The SBD metal is in a step shape and embedded in the metal source electrode, and comprises an SBD transverse part and an SBD longitudinal part which are integrally arranged, wherein the SBD longitudinal part extends into the source shallow groove in a mode of being attached to the side wall of the source shallow groove, and an SBD gap is formed between the SBD longitudinal part and the bottom surface of the source shallow groove;
The P-type doped semiconductor shielding layer is a stepped type and comprises a longitudinal shielding part and a transverse shielding part, wherein the longitudinal shielding part is arranged below the SBD longitudinal part and is overlapped with the N-type doped semiconductor JFET region on the side wall of the shallow trench of the source electrode, and the transverse shielding part is arranged on the top of the N-type doped semiconductor epitaxial layer overlapped with the bottom of the shallow trench of the source electrode.
2. The SiC power device of the embedded SBD for improving the short-circuit resistance according to claim 1, wherein an interlayer insulating medium is arranged between the metal gate and the metal source.
3. The SBD-embedded SiC power device of claim 1, further comprising a P-type doped semiconductor well disposed in the N-type doped semiconductor JFET region between the gate deep trench and the source shallow trench.
4. The SiC power device of the embedded SBD of claim 3, further comprising an N-type doped semiconductor source contact region and a P-type doped semiconductor ohmic contact region, wherein the N-type doped semiconductor source contact region and the P-type doped semiconductor ohmic contact region are arranged on top of the N-type doped semiconductor JFET region right above the P-type doped semiconductor well in parallel.
5. The SBD embedded SiC power device of claim 3, wherein the metal gate has a longitudinal depth exceeding that of the P-doped semiconductor well.
6. The SBD embedded SiC power device with short circuit resistance according to claim 3, wherein the length of the lateral part of the SBD is not more than 15% of the lateral width of the N-type doped semiconductor epitaxial layer, and the length of the longitudinal part of the SBD is not more than 150% of the longitudinal depth of the P-type doped semiconductor well.
7. The SiC power device with the embedded SBD for improving the short-circuit resistance according to claim 3, wherein the width of the source shallow trench is not less than 5% of the lateral width of the N-type doped semiconductor epitaxial layer and not more than 20% of the lateral width of the N-type doped epitaxial layer, and the depth of the source shallow trench is not less than 30% of the longitudinal depth of the P-type doped semiconductor well and not more than 225% of the longitudinal depth of the P-type doped semiconductor well.
8. The SBD embedded SiC power device with short circuit resistance according to claim 3, wherein the SBD gap is not less than 25% of the longitudinal depth of the P-type doped semiconductor well and not more than 75% of the longitudinal depth of the P-type doped semiconductor well.
9. The SiC power device with the embedded SBD for improving the short circuit resistance according to claim 1, wherein the width of the gate deep trench is not less than 10% of the transverse width of the N-type doped semiconductor epitaxial layer and not more than 20% of the transverse width of the N-type doped epitaxial layer, and the depth of the gate deep trench is not less than 30% of the longitudinal depth of the N-type doped semiconductor epitaxial layer and not more than 80% of the longitudinal depth of the N-type doped epitaxial layer.
10. The SBD embedded SiC power device of claim 1, wherein the P-type doped semiconductor shield layer has a doping concentration of 0.6X10 17 ~2×1017cm-3.
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| CN117766566A (en) * | 2024-01-15 | 2024-03-26 | 南京邮电大学 | Integrated high-K dielectric three-groove type silicon carbide longitudinal power device and preparation method thereof |
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| CN117766566A (en) * | 2024-01-15 | 2024-03-26 | 南京邮电大学 | Integrated high-K dielectric three-groove type silicon carbide longitudinal power device and preparation method thereof |
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