CN119225824A - BROM implementation method based on storage device, device, equipment and medium - Google Patents

Abstract

The application discloses a BROM (binary component array) realization method, a BROM realization device, BROM realization equipment and BROM realization medium based on storage equipment. The method comprises the steps of configuring a minimum and most stable system based on preset first control parameter information, starting BROM codes, determining a starting object, executing a first-stage bootstrap program in the BROM codes under the condition that the starting object is determined to be storage equipment, reading second control parameter information from a preset parameter space of the storage equipment according to the first control parameter information, performing data verification processing on the second control parameter information, executing a second-stage bootstrap program in the BROM codes under the condition that the data verification processing is passed, performing second data reading processing according to the second control parameter information, and reading boot codes from the storage equipment to start the SOC. The method can reduce the starting cost of the SOC, improve the starting performance, and improve the parameter reading stability and the starting flexibility.

Description

BROM implementation method and device based on storage equipment, equipment and medium

Technical Field

The application relates to the field of embedded development, in particular to a BROM (binary component array) realization method, a device, equipment and a medium based on storage equipment.

Background

BROM (Boot Read-Only Memory) contains the first level code required for starting the SOC (System on Chip), which is the key component for starting the SOC. BROM is solidified in SOC, is located in ROM (Read-Only Memory) of chip, and is a piece of software code which is not modifiable and is executed in initial stage of system start-up. eFuses, like EEPROMs, are one-time programmable memories that are written with information prior to shipment of the chip. In one chip, the capacity of eFuses is typically small. BROM typically implements a limited configuration through eFuses. At present, the operation of the BROM is controlled by modifying an one-time programmable memory (eFuse), but the eFuse space is limited, calculated by bits, has high cost, can be modified only once and has poor flexibility. The conventional BROM reads boot codes directly from a nonvolatile memory inside the UFS device. In order to meet the requirement of high performance, the traditional BROM uses a faster frequency to read as soon as possible, and the equivalent production process has problems, and can not be modified or can only be modified once, so that the flexibility is poor. Therefore, the currently adopted method for starting the SOC has the disadvantages of poor starting performance, instability, high cost, poor flexibility and large debug difficulty.

Disclosure of Invention

The present application aims to solve at least one of the technical problems in the related art to some extent.

Therefore, the embodiment of the application provides a BROM implementation method, device, equipment and medium based on storage equipment, which can reduce the starting cost of SOC, improve the starting performance, the parameter reading stability and the starting flexibility.

In a first aspect, an embodiment of the present application provides a method for implementing a brim based on a storage device, including:

configuring a minimum and most stable system based on preset first control parameter information, wherein the minimum and most stable system is used for providing a basic system operation environment for starting a system;

The BROM code is started to determine a starting object, wherein the BROM code is divided into a first-stage bootstrap program and a second-stage bootstrap program;

When the starting object is determined to be a storage device, executing the first-stage bootstrap program in the BROM code under the minimum and most stable system, and reading second control parameter information from a preset parameter space of the storage device according to the first control parameter information;

and carrying out data verification processing on the second control parameter information, and executing the second-stage bootstrap program in the BROM code under the condition that the data verification processing is passed, and carrying out second data reading processing according to the second control parameter information, and reading the boot code from the storage device to start the SOC.

According to some embodiments of the application, after performing the data verification process on the second control parameter information, the method further includes:

And under the condition that the data verification process is not passed, performing first data reading process according to the first control parameter information, and reading boot codes from the storage equipment to start the SOC.

According to some embodiments of the application, the storage device is a UFS device or an EMMC device.

According to some embodiments of the application, when the storage device is a UFS device, the second data reading process includes:

Determining a new reading rate, a new UFS parameter, a UFS BROM strategy and a system parameter according to the second control parameter information;

And reading the boot code from the UFS device according to the new reading rate, the new UFS parameter, the UFS BROM strategy and the system parameter.

According to some embodiments of the application, the second control parameter information includes debug print control information, the method further comprising:

obtaining debug printing control information from the second control parameter information;

And in the process of reading the boot code from the storage device or in the case of errors in the mass production stage, performing debug printing processing according to the debug printing control information to obtain debug information.

According to some embodiments of the application, the method further comprises:

Under the condition that the second control parameter information needs to be modified, receiving an update and upgrade package issued by an OTA server through a wireless network;

and updating the second control parameter information according to the update upgrade package to obtain updated third control parameter information.

According to some embodiments of the application, the method further comprises:

triggering a rollback mechanism under the condition that the second control parameter information does not need to be updated and errors occur in a mass production stage;

And under the rollback mechanism, the second control parameter information is rolled back to the first control parameter information, so that a boot code is read according to the first control parameter information in the process of executing the second-stage boot program.

In a second aspect, the present application provides a BROM implementation apparatus, comprising at least one processor and a memory for communication connection with the at least one processor, the memory storing instructions executable by the at least one processor, the instructions being executable by the at least one processor to enable the at least one processor to perform a storage device based BROM implementation method according to any one of the embodiments of the first aspect.

In a third aspect, the present application provides an electronic device, including a brim implementation apparatus as provided in the embodiment of the second aspect.

In a fourth aspect, the present application provides a storage medium, which is a computer-readable storage medium storing computer-executable instructions for causing a computer to perform a storage device-based BROM implementation method according to any one of the embodiments of the first aspect.

The embodiment of the application comprises the steps of firstly configuring a minimum and most stable system based on preset first control parameter information, enabling the minimum and most stable system to provide a basic system operation environment for a starting system, secondly starting BROM codes, determining a starting object, dividing the BROM codes into a first-stage bootstrap program and a second-stage bootstrap program, then executing the first-stage bootstrap program in the BROM codes under the condition that the starting object is determined to be a storage device, reading second control parameter information from a preset parameter space of the storage device according to the first control parameter information, then performing data verification processing on the second control parameter information, executing the second-stage bootstrap program in the BROM codes under the condition that the data verification processing is passed, and performing second data reading processing according to the second control parameter information, and reading the boot codes from the storage device to start the SOC. The embodiment of the application utilizes the storage equipment (such as UFS equipment) to replace eFuses, the nonvolatile medium of the storage equipment (such as UFS equipment) has large capacity, can store more data, can be modified for many times, has good flexibility and expansibility, is favorable for providing flexibility in starting and reducing the starting cost of the SOC, and ensures that the second control parameter information stored in the parameter space of the storage equipment can be stably read by introducing the minimum and most stable system and the second-stage guidance and carrying out the first-stage guidance under the minimum and most stable system so as to improve the reading stability of the starting parameter, and carries out high-performance second data reading processing based on the second control parameter information so as to improve the starting performance. That is, the embodiment of the application can reduce the starting cost of the SOC, improve the starting performance, the parameter reading stability and the starting flexibility.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

FIG. 1 is a schematic flow chart of a BROM implementation method based on a memory device according to an embodiment of the present application;

FIG. 2 is a schematic flowchart of a BROM implementation method based on a memory device according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating a specific flow of OTA upgrades provided by one embodiment of the present application;

Fig. 4 is a schematic hardware structure of a brim implementation device according to an embodiment of the present application.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent.

It should be noted that although a logical order is illustrated in the flowchart in the description of the present application, in some cases, the steps illustrated or described may be performed in an order different from that in the flowchart. In the description of the present application, a plurality means one or more, and a plurality means two or more. The description of "first" and "second" is used for the purpose of distinguishing between technical features only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.

First, several terms involved in the present application are explained:

BROM is commonly referred to as Boot Read-Only Memory, i.e., boot ROM. Which is a key component in the startup process, contains the initial level code required for system startup. BROM is located in ROM (Read-Only Memory) of the chip and is code executed in the initial stage of system start-up.

SOC, collectively referred to as System on a Chip, i.e., system on a Chip, is an integrated circuit design methodology that integrates the major components of a conventional computer or other electronic System onto a single Chip. These components typically include a Central Processing Unit (CPU), a Graphics Processor (GPU), memory, input/output (I/O) interfaces, and possibly other functional blocks such as analog circuitry, digital Signal Processors (DSPs), wireless communication modules, etc.

EFuses, collectively referred to as electronic fuses, are one-time programmable memory devices, also non-volatile memory devices, used to store information and protect chips.

Boot code, also known as Boot code or Boot code, is a piece of program that a computer or embedded system first executes when it is booted or restarted. Its main functions are initializing hardware device, creating mapping of memory space, loading kernel of operating system and preparing running environment of system. Boot code is the basis for the system to be able to start and run the operating system normally. Boot code is typically stored on non-volatile storage media such as ROM, EPROM, EEPROM or flash memory, etc., to ensure that the code is not lost after power is turned off.

UFS (Universal Flash Storage, universal flash memory storage) is a high-performance, high-integration storage device interface standard, formulated by JEDEC (joint electronic equipment engineering committee). UFS is designed to meet the increasing demands of mobile devices for high-speed read-write performance and high data throughput. It aims to replace the old eMMC (embedded multimedia card) standard and provide higher data transfer rates and better energy efficiency ratios.

Static random access memory (StaticRandom-AccessMemory, SRAM) is a common system memory. The data of the SRAM does not need a refresh process, and the data is not lost during power-up. SRAM costs are high.

Dump registers, which generally refer to the function of outputting the processor's register state into a log file or other storage medium when an error, exception, or debug occurs, are important for system debugging and error analysis.

OTA (Over-The-Air) remote upgrade is a wireless update technology that allows device manufacturers and software developers to push software updates to devices Over a wireless network without requiring manual intervention by The user. Which can be used to update firmware, data, and applications without requiring a physical connection to the device. In the implementation of OTA upgrades, the device needs to establish a connection with an OTA server, typically through Wi-Fi, cellular network, or other wireless communication technology. The OTA server can issue the upgrade package to the target device, so that the target device can realize the upgrade.

BROM (Boot Read-Only Memory) contains the first level code required for starting the SOC (System on Chip), which is the key component for starting the SOC. BROM is solidified in SOC, is located in ROM (Read-Only Memory) of chip, and is a piece of software code which is not modifiable and is executed in initial stage of system start-up. eFuses, like EEPROMs, are one-time programmable memories that are written with information prior to shipment of the chip. In one chip, the capacity of eFuses is typically small. BROM typically implements a limited configuration through eFuses. At present, the operation of the BROM is controlled by modifying an one-time programmable memory (eFuse), but the eFuse space is limited, calculated by bits, has high cost, can be modified only once and has poor flexibility. The conventional BROM directly reads boot codes from the nonvolatile memory of UFS devices. In order to meet the requirement of high performance, the traditional BROM uses a faster frequency to read as soon as possible, and the equivalent production process has problems, and can not be modified or can only be modified once, so that the flexibility is poor. Therefore, the currently adopted method for starting the SOC has the disadvantages of poor starting performance, instability, high cost, poor flexibility and large debug difficulty.

Furthermore, the UFS protocol is a 4-layer protocol stack, which is itself very complex to design in order to achieve high-speed rate transmission (up to 11.6Gps per lane), even with MIPI protocol M-PHY as the physical layer inside the physical layer. The complex protocol complicates the parameters that need to be configured and the number is large. In addition, the UFS controller needs to run firmware and provide firmware upgrade service when a problem is found, but the UFS controller does not use a nonvolatile storage medium and has a small amount of SRAM in order to save cost and simplify manufacturing process. Thus, the firmware can only be updated into the SRAM every time it is powered up. The firmware inside the UFS controller can only guarantee that the low rate is stable.

This makes it a major challenge to implement BROM based on UFS devices. On the one hand, setting a large number of parameters in the BROM will bring a great risk to mass production. It will be appreciated that BROM cannot be modified once it is mass produced. Moreover, if eFuses are used to control a large number of parameters, significant startup costs will result. In the prior art, only a small amount of parameters can be controlled by eFuses, and eFuses have only one modification opportunity, so that the flexibility is poor. On the other hand, if firmware upgrade is performed in the BROM, not only complex operations are brought, but also the risk of mass production is greatly increased, so that the UFS device can only use the lowest speed. The parameters are numerous, the firmware needs to be upgraded, the design of the UFS BROM tends to be conservative, the parameters are conservative, the speed is low, and the like, so that the starting performance of the UFS BROM is further limited, and the starting performance of the UFS BROM is even inferior to emmc. BROM has few debuggable means, no basic printing, and few debugged registers, so that how debugged in mass production is an important problem for complex UFS BROM.

Currently, UFS devices are widely used in electronic products such as tablet computers as a main storage device, so that the BROM as an SOC end needs to read boot codes from the UFS devices to finally complete the startup of the entire os system. In order to achieve higher performance, the UFS master control is very complex in design, has numerous parameters, even the master control itself is equivalent to an SOC, and needs to operate firmware, and even needs to update the firmware of the UFS master control according to the subsequent mass production. The UFS BROM at the SOC end has high requirements for realizing the UFS BROM at the SOC end, the starting performance and the stability are balanced, the stability is ensured while the performance is ensured, and a more detailed debug function is provided for analyzing the reasons of the output problems.

Based on the above, the application provides a BROM implementation method based on storage equipment, a BROM implementation device, electronic equipment and a computer readable storage medium; the method comprises the steps of configuring a minimum and most stable system based on preset first control parameter information, starting BROM codes, determining a starting object, executing a first-stage bootstrap program in the BROM codes under the condition that the starting object is determined to be storage equipment, reading second control parameter information from a preset parameter space of the storage equipment according to the first control parameter information, performing data verification processing on the second control parameter information, executing a second-stage bootstrap program in the BROM codes under the condition that the data verification processing is passed, performing second data reading processing according to the second control parameter information, and reading boot codes from the storage equipment to start the SOC. The method can reduce the starting cost of the SOC, improve the starting performance, and improve the parameter reading stability and the starting flexibility.

Embodiments of the present application will be further described below with reference to the accompanying drawings.

In a first aspect, as shown in fig. 1, fig. 1 is a schematic flow chart of a memory device-based brim implementation method according to an embodiment of the present application, where the memory device-based brim implementation method may include, but is not limited to, steps S110 to S140.

Step S110, configuring a minimum and most stable system based on preset first control parameter information, wherein the minimum and most stable system is used for providing a basic system operation environment for starting the system.

Step S120, BROM codes are started to determine starting objects, wherein the BROM codes are divided into a first-level bootstrap program and a second-level bootstrap program.

And step S130, when the starting object is determined to be the storage device, executing a first-stage bootstrap program in the BROM code under the minimum and most stable system, and reading second control parameter information from a preset parameter space of the storage device according to the first control parameter information.

And step S140, performing data verification processing on the second control parameter information, and executing a second-stage bootstrap program in the BROM code when the data verification processing is passed, performing second data reading processing according to the second control parameter information, and reading the boot code from the storage device to start the SOC.

It will be appreciated that in step S110, during start-up of the SOC, the minimum and most stable system generally refers to an operating system environment containing only the most basic functions and drivers, which is sufficient to support the minimum level operation of the device and further system start-up procedures. The minimum and minimum stable system is used for carrying out hardware initialization, setting and configuring various hardware components on the SOC, and configuring a system, such as setting a clock, a network interface and the like.

It can be understood that, in step S110, the first control parameter information refers to the most basic, most reliable and fully verified configuration settings and performance indexes in the system design. The first control parameter information comprises the parameters of minimum reading rate and most stability and conservation. These parameters and rates ensure that the SOC is capable of stable operation under a variety of conditions, even in the most severe operating environments or under the least adverse external conditions.

It will be appreciated that during startup, boot data in a storage device (e.g., UFS device) may be read, depending on the system design and startup sequence. Therefore, first, in step S120, the BROM code is started, and the start mode is checked to determine the start target.

According to some embodiments of the present application, step S140 is further described, wherein after performing the data verification process on the second control parameter information, the method further includes performing a first data reading process according to the first control parameter information to read a boot code from the storage device to start the SOC if the data verification process is not passed.

According to some embodiments of the application the storage device is a UFS device or an EMMC device. It is understood that the storage device is an embedded storage device. The BROM implementation method provided by the embodiment of the application can also be applied to other storage devices similar to the UFS device, so that the type of the storage device is not particularly limited by the application.

The method comprises the steps of S110 to S140, firstly, configuring a minimum and most stable system based on preset first control parameter information, secondly, starting BROM codes to determine a starting object, wherein the BROM codes are divided into a first-stage bootstrap program and a second-stage bootstrap program, then, when the starting object is determined to be a storage device, executing the first-stage bootstrap program in the BROM codes, reading second control parameter information from a preset parameter space of the storage device according to the first control parameter information, then, performing data verification processing on the second control parameter information, executing the second-stage bootstrap program in the BROM codes, and performing second data reading processing according to the second control parameter information under the condition that the data verification processing is passed, and reading the boot codes from the storage device to start the SOC. The embodiment of the application utilizes the storage equipment (such as UFS equipment) to replace eFuses, the nonvolatile medium of the storage equipment (such as UFS equipment) has large capacity, can store more data, can be modified for many times, has good flexibility and expansibility, is favorable for providing flexibility in starting and reducing the starting cost of the SOC, and ensures that the second control parameter information stored in the parameter space of the storage equipment can be stably read by introducing the minimum and most stable system and the second-stage guidance and carrying out the first-stage guidance under the minimum and most stable system so as to improve the reading stability of the starting parameter, and carries out high-performance second data reading processing based on the second control parameter information so as to improve the starting performance. Therefore, the embodiment of the application can reduce the starting cost of the SOC, improve the starting performance, the parameter reading stability and the starting flexibility.

As an example, further explaining steps S110 to S140 of the brim implementation method provided by the embodiment of the present application when the storage device is a UFS device.

In one embodiment, a parameter space is preset in the UFS device prior to performing step S130, and second control parameter information is stored in the parameter space. It will be appreciated that a parameter space is reserved in advance in the non-volatile storage medium of the UFS device, and the parameter space is used to store the control parameters (i.e., the second control parameter information) of the UFS BROM. I.e. replace eFuses with UFS devices, a larger, cheaper, lower cost, and reusable parameter interval is obtained. Because of the large capacity of the non-volatile storage medium of the UFS device, the number of parameters that can be saved is large, and the non-volatile storage medium of the UFS device can be modified multiple times, its flexibility and scalability are better than that of the efuses. When the UFS device is applied to electronic products such as tablet computers, the UFS device is a main storage device that must be used, and a parameter space is opened up to replace an eFuse space, so that the eFuse space can be saved, and the SOC hardware cost can be reduced. In addition, the parameter space of the UFS equipment is very small compared with the UFS equipment, the required control parameters can be quickly read out from the parameter space, the influence on the starting performance of BROM is small, and the starting performance is improved.

It should be noted that, in the embodiment of the present application, the BROM code is divided into a first-stage boot program and a second-stage boot program, that is, the two-stage boot is implemented in the BROM, the first-stage boot reads the second control parameter information from the parameter space of the UFS device, and the second-stage boot reads the real boot code according to the second control parameter information to start the SOC.

It can be understood that the minimum and most stable system is selected, the first control parameter information (including the most stable and most conservative parameters and the lowest reading rate) is used as a bottom protection scheme, the first-stage guidance is performed based on the first control parameter information, so as to ensure that the second control parameter information is stably read from the parameter space of the UFS device, and then the subsequent BROM is controlled to operate with high performance according to the second control parameter information, so as to solve the problem of how to stably and efficiently read the control parameters of the BROM. In the embodiment of the application, the minimum and most stable system operation environment (namely, the bottom protection scheme) is configured, so that the second control parameter information can be stably read out, and in addition, once a problem exists (for example, firmware upgrading is required, the existing firmware can only ensure that the low speed is stable), the BROM can safely read boot data in the first-stage boot and the second-stage boot by using the minimum and stable environment in an OTA (over the air) mode and the like, so that the robustness of the BROM is improved. The setting of the bottom protection scheme, namely the setting of the first control parameter information, also provides reliable emergency guarantee for the second-stage guiding and lifting performance. The second stage of guiding can not only promote UFS frequency, but also promote cpu frequency, bus frequency and other system parameters which help to improve performance.

According to some embodiments of the present application, further describing step S140, after performing the data verification process on the second control parameter information, the method further includes performing a first data reading process according to the first control parameter information to read a boot code from the UFS device to start the SOC if the data verification process is not passed.

When the storage device is a UFS device, through steps S110 to S140, firstly, a minimum and most stable system is configured based on preset first control parameter information, the minimum and most stable system is used for providing a basic system operation environment for a starting system, secondly, a BROM code is started to determine a starting object, wherein the BROM code is divided into a first-stage bootstrap program and a second-stage bootstrap program, then, when the starting object is determined to be the UFS device, the first-stage bootstrap program in the BROM code is executed under the minimum and most stable system, second control parameter information is read from a preset parameter space of the UFS device according to the first control parameter information, then, data verification processing is performed on the second control parameter information, and when the data verification processing is passed, the second-stage bootstrap program in the BROM code is executed, second data reading processing is performed according to the second control parameter information, and the boot code is read from the UFS device to start the SOC. The embodiment of the application utilizes the UFS equipment to replace eFuses, has large capacity of nonvolatile media of the UFS equipment, can store more data, can be modified for multiple times, has good flexibility and expansibility, is favorable for providing flexibility in starting and reducing the starting cost of the SOC, and ensures that the second control parameter information stored in the parameter space of the UFS equipment can be stably read by introducing a minimum and most stable system and carrying out the first-stage guidance under the minimum and most stable system so as to improve the starting parameter reading stability, and carries out high-performance second data reading processing based on the second control parameter information so as to improve the starting performance. Therefore, the embodiment of the application can reduce the starting cost of the SOC, improve the starting performance, the parameter reading stability and the starting flexibility.

According to some embodiments of the application, when the storage device is a UFS device, the second data reading process includes, but is not limited to, the steps of:

And reading boot codes from the UFS equipment according to the new reading rate, the new UFS parameters, the UFS BROM strategy and the system parameters. Therefore, based on the second control parameter information, BROM can be operated with high performance, and starting performance is improved.

Specifically, the UFS BROM policy may be to re-initialize host and UFS device re-read data using new UFS parameters.

Specifically, the system parameters include, for example, cpu frequency, bus frequency, and the like.

According to some embodiments of the present application, the second control parameter information includes debug print control information, and the method for implementing the brim based on the storage device according to the embodiment of the present application further includes, but is not limited to, the following steps:

and performing debug printing processing according to the debug printing control information in the process of reading the boot code from the UFS equipment or in the case of errors in the mass production stage to obtain debug information. In this way, a controllable debug print process is realized.

Specifically, an option of opening printing can be added in the parameter space, BROM printing is opened when a mass production problem exists, so that debug efficiency is improved, and the problems that BROM does not print and debug is difficult are solved. In addition, a dump register function can be added, and when the quantity is output in error, the register can be printed out, so that a first site of the problem is obtained.

As an example, when the storage device is a UFS device, a specific flow of the UFS device-based BROM implementation method provided by the embodiment of the present application is described with reference to fig. 2.

Step S201, UFS BROM is started.

And step S202, carrying out UFS initialization processing by using the most conservative parameters and the lowest reading rate, and initializing the UFS controller and the UFS equipment.

Step S203, the second control parameter information stored in the parameter space of the UFS device is read using the most conservative parameter and the lowest reading rate. The most conservative parameter, the lowest read rate, is the first control parameter information of the embodiment of the present application.

Step S204, checking the second control parameter information.

Step S205, judging whether the verification is passed or not, if the verification is passed, executing step S206 to step S209, and if the verification is not passed, executing step S210.

Step S206, determining new reading rate, new UFS parameter and system parameter according to the second control parameter information.

Step S207, determining to perform debug printing processing or open debug information according to the second control parameter information.

Step S208, determining the UFS BROM strategy according to the second control parameter information, such as re-initializing host and UFS device re-reading data with new UFS parameters.

Step S209, the boot data is read from the UFS equipment according to the new reading rate, the new UFS parameters, the UFS BROM strategy and the system parameters.

Step S210, continuing to read the boot data by using the most conservative parameter and the lowest reading rate.

In the BROM implementation method based on the storage device, which is provided by the embodiment of the application, an OTA remote upgrading function is also configured.

According to some embodiments of the present application, the memory device-based BROM implementation method further includes, but is not limited to, the following steps:

and under the condition that the second control parameter information needs to be modified, receiving an updating update package issued by the OTA server through the wireless network, and updating the second control parameter information according to the updating update package to obtain updated third control parameter information.

According to some embodiments of the present application, the memory device-based BROM implementation method further includes, but is not limited to, the following steps:

And under the rollback mechanism, rollback the second control parameter information into the first control parameter information so as to read boot codes according to the first control parameter information in the process of executing the second-stage bootstrap program.

It will be appreciated that the parameter space of the UFS device can be modified multiple times to enable remote control of the BROM behavior. In the case that the control parameter is found to have a problem and needs to be updated, or a problem occurs in a mass production stage, the BROM parameter can be remotely modified in an OTA upgrading mode, and even the second control parameter information is directly restored to the most conservative parameter and the lowest reading rate (namely, the first control parameter information) based on a rollback mechanism.

As an example, a specific flow of OTA upgrade is described in conjunction with fig. 3.

Step S301, OTA upgrade starts.

Step S302, judging whether the parameters need to be updated, if yes, executing step S303, and if not, executing steps S304 to S305.

Step S303, updating parameters.

Step S304, when mass production problems are found, the roll-back to the conservative parameter and the lowest reading rate are needed.

Step S305, rollback to the conservative parameter and the lowest read rate, and using the conservative parameter and the lowest read rate.

It can be understood that, based on the BROM implementation method based on the storage device provided by the embodiment of the application, the programming mass production is performed, the product differentiation is realized, and the customization is realized. Specifically, after mass production begins, the type of parameters used is determined according to customer category or differentiated requirements. For the customer pursuing stability, the first control parameter information is used. For customers who do not pursue stability, the second control parameter information is used. Therefore, product differentiation can be realized simultaneously, the high-end product rate is high, and the low-end product rate is low.

In summary, the embodiment of the application realizes UFS BROM controllable performance, controllable parameters and strategies, and controllable multiple rewrites, print debug and remote control through OTA upgrading by introducing the minimum and most stable system into BROM, introducing the secondary guidance, and replacing eFuses with UFS equipment, thereby reducing the starting cost, and enabling the mass production process to be differentiated and customizable. Flexibility, compatibility, and performance of a memory device-based BROM implementation are improved and debug is facilitated.

In a second aspect, as shown in fig. 4, the present application further provides a BROM implementation apparatus 400, including:

The processor 401 may be implemented by a general purpose central processing unit, a microprocessor, an application specific integrated circuit, or one or more integrated circuits, etc. for executing related programs to implement the technical solution provided by the embodiments of the present application;

Memory 402 may be implemented in the form of read-only memory, static storage, dynamic storage, random access memory, or the like. The memory 402 may store an operating system and other application programs, and when the technical solution provided in the embodiments of the present disclosure is implemented by software or firmware, relevant program codes are stored in the memory 402, and the processor 401 invokes a BROM implementation method based on a storage device to execute the embodiments of the present disclosure;

an input/output interface 403 for implementing information input and output;

The communication interface 404 is configured to implement communication interaction between the device and other devices, and may implement communication in a wired manner (such as USB, network cable, etc.), or may implement communication in a wireless manner (such as mobile network, WIFI, bluetooth, etc.);

A bus 405 for transferring information between the various components of the device (e.g., processor 401, memory 402, input/output interface 403, and communication interface 404);

Wherein the processor 401, the memory 402, the input/output interface 403 and the communication interface 404 are in communication connection with each other inside the device via a bus 405.

In a third aspect, an embodiment of the present application further provides an electronic device, including a BROM implementation apparatus as described above.

In a fourth aspect, an embodiment of the present application provides a storage medium, where the storage medium is a computer readable storage medium, where computer executable instructions are stored, where the computer executable instructions are configured to cause a computer to perform a brim implementation method based on a storage device according to the above embodiment.

The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The apparatus embodiments described above are merely illustrative, in which the elements illustrated as separate components may or may not be physically separate, implemented to reside in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and may include any information delivery media.

While the preferred embodiment of the present application has been described in detail, the present application is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit and scope of the present application, and these equivalent modifications or substitutions are included in the scope of the present application as defined in the appended claims.

While the preferred embodiments of the present application have been described in detail, the present application is not limited to the above embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present application, and these equivalent modifications and substitutions are intended to be included in the scope of the present application.

Claims (10)

1. A BROM implementation method based on a storage device, characterized by comprising: Based on the preset first control parameter information, configuring a minimum and most stable system; the minimum and most stable system is used to provide a basic system operating environment for starting the system; The BROM code is started to determine the startup object; wherein the BROM code is divided into a first-level boot program and a second-level boot program; When it is determined that the boot object is a storage device, the first level boot program in the BROM code is executed under the minimum and most stable system, and second control parameter information is read from a preset parameter space of the storage device according to the first control parameter information; Perform data verification processing on the second control parameter information. If the data verification processing passes, execute the second-level boot program in the BROM code, perform second data reading processing according to the second control parameter information, and read the boot code from the storage device to start the SOC. 2. The BROM implementation method based on a storage device according to claim 1, characterized in that after performing data verification processing on the second control parameter information, the method further comprises: In the case that the data verification process fails, a first data reading process is performed according to the first control parameter information to read a boot code from the storage device to start the SOC. 3. The BROM implementation method based on a storage device according to claim 1, characterized in that the storage device is: a UFS device or an EMMC device. 4. The BROM implementation method based on a storage device according to claim 1, characterized in that when the storage device is a UFS device, the second data reading process comprises: Determine a new read rate, a new UFS parameter, a UFS BROM strategy, and a system parameter according to the second control parameter information; The boot code is read from the UFS device according to the new read rate, the new UFS parameter, the UFS BROM policy, and the system parameter. 5. The BROM implementation method based on a storage device according to claim 1, wherein the second control parameter information includes debug printing control information, and the method further comprises: Acquire debug printing control information from the second control parameter information; In the process of reading the boot code from the storage device, or in the case of an error in the mass production stage, debug printing processing is performed according to the debug printing control information to obtain debug information. 6. The BROM implementation method based on a storage device according to claim 1, characterized in that the method further comprises: When the second control parameter information needs to be modified, receiving an update package sent by the OTA server through a wireless network; According to the update package, the second control parameter information is updated to obtain updated third control parameter information. 7. The BROM implementation method based on a storage device according to claim 1, characterized in that the method further comprises: When the second control parameter information does not need to be updated and an error occurs during the mass production phase, a rollback mechanism is triggered; Under the rollback mechanism, the second control parameter information is rolled back to the first control parameter information, so that during the execution of the second-level boot program, the boot code is read according to the first control parameter information. 8. A BROM implementation device, characterized in that it includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the BROM implementation method based on the storage device as described in any one of claims 1 to 7. 9. An electronic device, comprising the BROM implementation device according to claim 8. 10. A storage medium, characterized in that the storage medium is a computer-readable storage medium, the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the BROM implementation method based on a storage device as described in any one of claims 1 to 8.