CN119213556A

CN119213556A - Solid-state imaging device with high charge transfer capability

Info

Publication number: CN119213556A
Application number: CN202280096091.6A
Authority: CN
Inventors: 高桥诚司; 夏爱华
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-07-04
Filing date: 2022-07-04
Publication date: 2024-12-27
Also published as: WO2024007121A1

Abstract

A solid-state imaging device comprising a pixel array, wherein each pixel of the pixel array (1201) comprises: a photodiode for converting electromagnetic radiation into electric charge; and a transfer gate device for transferring the electric charge from the photodiode to a floating diffusion node, wherein the transfer gate device comprises an embedded portion (102) embedded in the pixel array (1201), and a first wall of the embedded portion (102) on a side facing the floating diffusion node and a second wall of the embedded portion (102) on a side not facing the floating diffusion node have different shapes.

Description

Solid-state imaging device with high charge transfer capability

Technical Field

The present disclosure relates to a solid-state imaging device, and particularly to a solid-state imaging device including a pixel structure having a high charge transfer capability.

Background

An important issue associated with solid-state imaging devices is the increase of the full well capacity, which is the upper limit of the capacity to store the charge generated by converting the detected electromagnetic radiation into photo-charges. Since charges exceeding the full well capacity cannot be detected as signals, a small full well capacity can lead to a low dynamic range (DYNAMIC RANGE, DR) and a low signal-to-noise ratio (SNR) under a large amount of electromagnetic radiation. In contrast, due to the detected electromagnetic radiation, the large full well capacity helps to reproduce the high definition image, thereby achieving true restoration of the image. Thus, higher full well capacity is always desirable.

Another important issue associated with solid-state imaging devices is the reduction of pixel size. However, this also results in a reduction in the full well capacity of the solid-state imaging device. Accordingly, it is designed to enlarge the photodiode in a direction perpendicular to the surface of the solid-state imaging device (i.e., in the depth direction) to increase the full well capacity while reducing the pixel size. In order to achieve high charge transfer capability to transfer all charges stored in such a deep photodiode, a vertical transfer gate (VERTICAL TRANSFER GATE, VTG) has been proposed, which has a structure extending in the depth direction, instead of a planar structure provided on the surface of a solid-state imaging device.

Since the charge transport capacity of a vertical transport element (VTG) is proportional to the bottom area of the VTG, it is desirable to increase the bottom area of the VTG. In order to increase the floor area of the VTG, cup-shaped VTG (US 009041071B 2) has been proposed. However, cup VTGs are very large and may cause defects and may also cause problems in subsequent manufacturing processes due to cup-shaped steps, such as source/drain sidewall spacer formation and back end of line (BEOL).

For this reason, a technique has been devised to improve the charge transfer capability of the VTG by providing a shallow photodiode adjacent to the VTG and transferring charge from the VTG side wall while reducing the pixel size by reducing the bottom area of the VTG (US 2020/0344333 A1). However, the pixel size reduction is limited by the need to provide shallow photodiodes beside the VTG. Further, since the bottom area of the VTG is small, the electric charges from the deep portion of the photodiode cannot be sufficiently read out.

In addition, increasing the bottom area of the VTG causes another problem, namely "high light spillover". The blooming is a phenomenon in which a plurality of pixel defects occur on a reproduced image, and since a photodiode of a pixel irradiated with strong light cannot store electric charges, excessive electric charges are diffused to surrounding pixels. In order to prevent blooming, a blooming prevention path is provided through which excess charge is discharged from the photodiode to the floating diffusion node (US11,195,873B2). However, since the VTG has two columnar electrodes to configure a highlight overflow preventing path, the pixel size cannot be reduced.

Therefore, in the case where the space of the solid-state imaging device is limited, it is highly desirable to increase the full well capacity as much as possible.

Disclosure of Invention

An object of the present invention is to solve the above-described problems in the field of solid-state imaging devices.

According to a first aspect of the present invention, there is provided a solid-state imaging device including a pixel array, wherein each pixel of the pixel array includes:

a photodiode for converting electromagnetic radiation into electrical charge;

A transfer gate device for transferring the charge from the photodiode to a floating diffusion node,

Wherein the transfer gate device includes an embedded portion embedded in the pixel array, a first wall of a side of the embedded portion facing the floating diffusion node and a second wall of a side of the embedded portion not facing the floating diffusion node having different shapes.

According to a first possible implementation form of the first aspect of the invention, the embedded part comprises a surface of the pixel array and a bottom surface between the photodiodes, each pixel comprises a P-type doped region between the bottom surface and the photodiodes, and further comprises an N-type doped region between the P-type doped region and the photodiodes.

According to a second possible implementation form of the first aspect of the invention, the P-type doped region is further extended to one side of the transfer gate device.

According to a third possible implementation form of the first aspect of the invention, the embedded portion comprises a surface of the pixel array and a bottom surface between the photodiodes, each pixel comprising a P-type doped region between the bottom surface and the photodiodes.

According to a fourth possible implementation form of the first aspect of the invention, the P-type doped region is further extended to one side of the transfer gate device.

According to a fifth possible implementation manner of the first aspect of the present invention, the P-type doped region and the N-type doped region are self-aligned.

According to a sixth possible implementation manner of the first aspect of the present invention, the P-type well between the embedded portion and the pixel device is deeper than the P-type well between the embedded portion and the floating diffusion node.

According to a seventh possible implementation form of the first aspect of the invention, a cross-section of the embedded portion parallel to the surface of the pixel array is a combination of polygons or curves.

According to an eighth possible implementation form of the first aspect of the invention, the transfer gate device further comprises a protrusion formed on a surface of the pixel array, in the cross section of the embedded portion parallel to the surface of the pixel array, a part or all of the polygonal side or the plurality of curves is located outside the area of the protrusion.

According to a ninth possible implementation form of the first aspect of the invention, the pixel array comprises a pixel unit comprising 4 pixels coupled to the same floating diffusion node, the embedded parts comprised in the pixel unit being arranged in a ring shape.

According to a tenth possible implementation form of the first aspect of the invention, the embedded parts comprised in the pixel unit are arranged to be rotationally symmetrical by 90 degrees or rotationally symmetrical by 180 degrees with respect to the same floating diffusion node.

According to an eleventh possible implementation form of the first aspect of the invention, in a cross-section of the embedded portion parallel to the surface of the pixel array, the first wall has a first arc comprising a first center and a first radius, the second wall has a second arc comprising a second center and a second radius, and wherein the first center and the second center are both between the floating diffusion node and the transfer gate device, the first radius being smaller than the second radius.

According to a twelfth possible implementation manner of the first aspect of the present invention, the transfer gate device further includes a protrusion formed on a surface of the pixel array, the first wall and the second wall are disposed opposite to each other, the embedded portion further includes a third wall and a fourth wall, the third wall and the fourth wall respectively connect the first wall and the second wall, and in a section of the embedded portion parallel to the surface of the pixel array, a part or all of one or more of the first wall, the second wall, the third wall and the fourth wall is located outside an area of the protrusion.

According to a thirteenth possible implementation manner of the first aspect of the present invention, a cross section of the embedded portion perpendicular to the surface of the pixel array is any one of the following shapes:

a square;

a trapezoid narrowed toward the bottom surface;

a trapezoid widening toward the bottom surface;

A parallelogram;

is approximately rectangular, and is provided with round corners at one side of the bottom surface;

Is generally rectangular with rounded corners on one side of the surface of the pixel array.

According to a fourteenth possible implementation form of the first aspect of the invention, a part of the overflow path is formed between the bottom surface of the embedded part and the photodiode or below the bottom surface of the embedded part inside the photodiode.

According to a fifteenth possible implementation form of the first aspect of the invention, the overflow path is a path for transferring photoelectric charges exceeding a full well capacity of the photodiode to the floating diffusion node.

According to a second aspect of the present invention, there is provided an electronic device comprising a solid-state imaging device according to the first aspect or any one of the first to twelfth possible implementations of the first aspect.

[ Effect of the invention ]

With the solid-state imaging device of the present invention, the full well capacity can be improved while reducing the pixel size.

Further, according to the solid-state imaging device of the present invention, there is no problem of a residual image in the readout phase, and high pixel charge transfer capability from the light conversion region to the floating diffusion node can be achieved.

Further, according to the solid-state imaging device of the present invention, blooming in the pixel charge integration stage can be suppressed.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the background art, the drawings for describing the embodiments of the present application or the background art will be described below. It is apparent that the figures in the following description show only some embodiments of the application and that other figures can be obtained from these figures by a person of ordinary skill in the art without inventive effort.

Fig. 1 shows a top view of a pixel cell including 4 photodiodes formed on a semiconductor substrate according to a first embodiment of the present invention.

Fig. 2A illustrates a top view and a cross-sectional view of a single pixel formed on a semiconductor substrate according to the related art.

Fig. 2B shows a top view and a cross-sectional view of a single pixel formed on a semiconductor substrate according to a first embodiment of the present invention.

Fig. 3 shows a cross-sectional view along the line A-A' in fig. 1.

Fig. 4 shows a top view of various shapes of a VTG according to a second embodiment of the present invention.

Fig. 5 shows a top view of various shapes of a VTG according to a third embodiment of the present invention.

Fig. 6 shows a top view of various arrangements of a VTG according to a fourth embodiment of the invention.

Fig. 7 shows a cross-sectional view of various shapes of a VTG according to a fifth embodiment of the present invention.

Fig. 8 shows a cross-sectional view of various shapes of a VTG according to a sixth embodiment of the present invention.

Fig. 9 shows cross-sectional views of various shapes of a PD according to a seventh embodiment of the present invention.

Fig. 10 shows various circuits of a shared pixel device according to an eighth embodiment of the present invention.

Fig. 11 shows various circuits of a pixel device according to a ninth embodiment of the present invention.

Fig. 12 shows an exemplary pixel array to which an embodiment of the present invention is applied.

Fig. 13 shows a cross-sectional view of a portion of an exemplary pixel array to which an embodiment of the invention is applied.

Fig. 14 shows a schematic structural diagram of an exemplary solid-state imaging device to which an embodiment of the present invention is applied.

Fig. 15 shows a schematic block diagram of an exemplary electronic device to which embodiments of the invention are applied.

Fig. 16 shows an exemplary technical field to which an embodiment of the present invention is applied.

Fig. 17 shows an example of applying an embodiment of the present invention to a vehicle.

Detailed Description

The terminology used in the present application is for the purpose of describing particular possible implementations only and is not intended to be limiting of the application. The use of the terms "a," "an," "the," and "said" in the singular, including the claims, is intended to include the plural forms as well, unless expressly stated otherwise. It will also be understood that the term "and/or" as used herein refers to any or all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, data, information, entities, steps, operations, devices, units, elements, and/or components, but do not preclude the presence or addition of one or more other features, data, information, entities, steps, operations, devices, units, elements, components, and/or groups thereof.

It should be understood that although the terms "first," "second," etc. may be used in embodiments of the present application to describe various devices or units, these devices or units should not be limited by the terms. These terms are only used to distinguish one from another device or unit. For example, a first device and a first unit may be referred to as a second device and a second unit, respectively, without departing from the scope of embodiments of the application. Similarly, the second device and the second unit may be referred to as a first device and a first unit, respectively.

It should be noted that the order of the steps in the present application can be freely arranged. I.e. the application is not limited to the order of the steps.

The following describes the technical scheme in the embodiment of the present application with reference to the accompanying drawings.

In the following description and the accompanying drawings, electrons or holes are the main carriers in the region denoted by N or P, respectively. The region denoted by N or P is referred to as an N-type doped region or a P-type doped region, or simply as an N-type or P-type, or N-region or P-region. For an N or P region marked with "+", i.e., a region denoted by n+ or p+, it means that the doping concentration of the region is higher than that of a region not denoted by "+". For an N or P region marked with a "-" i.e. a region denoted by N-or P-it means that the doping concentration of the region is lower than for a region not denoted by a "-". While the following discussion describes the case where the signal charge includes electrons and all transistors are N-type transistors, in other embodiments the signal charge may include holes and some of the transistors may be P-type transistors.

Fig. 1 shows a top view of a pixel unit 100 including 4 photodiodes PD1 to PD4 formed on a semiconductor substrate according to a first embodiment of the present invention. In fig. 1, 4 photodiodes PD1 to PD4 share a pixel device. The photodiodes PD1 to PD4 are separated by deep channel isolation (DTI) and/or doped isolation. The pixel devices are separated by shallow trench isolation (shallow trench isolation, STI) and/or doped isolation. The pixel device includes a vertical transfer gate (VERTICAL TRANSFER GATE, VTG) device, a floating diffusion node (floating diffusion, FD), a Reset (RST) device, a dual conversion gain (dual conversion gain, DCG) device, an Amplifier (AMP) device, and a Selector (SEL). VTG, RST, DCG, AMP and SEL may be implemented by complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) transistors.

Each of the photodiodes PD1 to PD4 is connected to AVSS1, which AVSS1 is grounded or negative voltage in the range of-5.0V to 0V. Each of the photodiodes PD1 to PD4 detects electromagnetic radiation and converts the detected electromagnetic radiation into electrons. As long as the VTG is not in a conductive state, electrons remain between each of the photodiodes PD1 to PD4 and the corresponding VTG. When the VTG receives a transfer signal from a control circuit (not shown) and is in a conductive state (ON), the VTG transfers electrons to the FD. The FD receives electrons and stores charges generated by the electrons.

The FD is connected to a gate of an Amplifier (AMP) device, and a change in charge stored in the FD is amplified by the AMP. SEL receives a row selection signal from the control circuit, then turns into a conductive state (ON), and outputs a voltage corresponding to the charge stored in the FD at Vout. A Reset (RST) device selectively resets the charge stored on the PD and/or FD. In some embodiments, the signal is acquired by performing correlated double sampling (correlated double sampling, CDS). The CDS uses the difference between the reset level and the signal level to reduce fixed pattern noise and reset noise. In some embodiments, the charge-to-voltage conversion is performed by AMPs with a gain equal to or less than 1 using source follower operation. In some embodiments, the charge-to-voltage conversion is performed by AMPs with a gain greater than 1, where a differential amplification mode may be employed.

In some embodiments, vout may be greater than 2, and at least two rows may be read out simultaneously.

A dual conversion gain (dual conversion gain, DCG) device switches between the two conversion gains. When the DCG is in the conductive state (ON), the FD of the pixel cell 100 is connected to the FD of another pixel cell to provide a low conversion gain (low conversion gain, LCG) mode suitable for a high dynamic range (HIGH DYNAMIC RANGE, HDR). When the DCG is in a non-conductive state (OFF), the FD of the pixel unit 100 is not connected to the FD of another pixel unit to provide a high conversion gain (high conversion gain, HCG) mode suitable for high signal-to-noise ratio.

The power supply voltages AVDD1 and AVDD2 supply power to the pixel devices. AVDD1 and AVDD2 may have the same or different potentials.

In the example of fig. 1, the pixel unit 100 includes 4 photodiodes PD1 to PD4 and 4 corresponding VTGs, but the number of photodiodes and VTGs included in one pixel unit 100 may be more or less than 4. A pixel array can also be formed by arranging a plurality of pixel units 100 in rows and columns. The solid-state imaging device according to the present invention includes such a pixel array.

The VTG of each of the photodiodes PD1 to PD4 has a protruding portion 101 represented by a solid hexagon and an embedded portion 102 represented by a broken line. The protruding portion 101 is a portion protruding from the surface of the pixel array (i.e., the surface of the semiconductor substrate forming the pixel unit 100), and the embedded portion 102 is a portion embedded within the pixel array (i.e., the inside of the semiconductor substrate forming the pixel unit 100).

The cross section of the embedded portion 102 is a shape surrounded by two arcs and two straight lines in a plan view. This shape allows the bottom area of the embedded portion 102 of the VTG to be larger than conventional circles, rectangles, squares, etc. The two arcs are portions of different circles, each circle having a different radius. The center of each circle may be the same or different and is located between the FD and the insert 102. Or the centers of the arcs forming the cross-section of the embedded portion 102 corresponding to different PDs may be different or the same. This configuration of the embedded portion 102 increases the bottom area of the VTG, thereby improving the charge transfer capability of the VTG, and thus achieving a high full well capacity.

The 4 embedded parts 102 included in the pixel unit 100 may be disposed in one annular space. For example, 4 inserts 102 may be disposed on a circumference, the center of which may be located at or near FD, or between FD and insert 102.

The shape of the embedded portion 102 is not limited to the shape shown in fig. 1. For convenience, the electrode (black square) of the VTG as shown in fig. 1 is referred to as the center of the embedded portion 102, and the side near the adjacent PD is referred to as one end of the embedded portion 102. At this time, the closer the point on the arc is to the center of the embedded portion 102, the larger the distance between the surface of the embedded portion 102 and the FD is, and the closer the point on the arc is to the end of the embedded portion 102, the smaller the distance between the surface of the embedded portion 102 and the FD is. In this way, the distance between the embedded portion 102 and the FD is made as far as possible.

Such a shape and arrangement of the embedded portion 102 increases the distance between the embedded portion 102 of the VTG and the FD, and thus decreases the electric field strength between the VTG and the FD. Accordingly, leakage current from the VTG to the FD, which causes severe fixed pattern noise, can be reduced.

Fig. 2A shows a top view (upper) and a cross-sectional view (lower) of a single pixel formed on a semiconductor substrate according to the related art. As shown in the cross-sectional view (bottom), both sides of an N-type PD (N-PD) have deep channel isolation (DTI) separating the N-PD from adjacent N-PDs. On the left side of the DTI there is a shallow trench isolation (shallow trench isolation, STI) separating the photodiode region from adjacent pixel devices. In some embodiments, separation between devices may be achieved by STI or doped isolation.

In some embodiments, some of the Reset (RST) device, the Dual Conversion (DCG) device, the Amplifier (AMP) device, or the Selector (SEL) (see also fig. 1) may be formed on a separate wafer that is coupled to the wafer on which the PD, VTG, and FD are formed.

The embodiment shown in fig. 2A shows a partial deep channel isolation (DTI), but in other embodiments a complete DTI may be formed with a depth equal to or greater than the thickness of the light conversion material.

FD is shown as the n+ region. The VTG of fig. 2A is circular in cross-section (as shown in top view (up)) and horizontally T-shaped (as shown in cross-section (down)) to the deep portion of the N-PD, with an N-region on the N-PD on the left side of the VTG. The charge stored in the N-PD is guided to the N-region (path 201') and carried to the FD through the VTG side (path 201). Path 201' is a side view of path 201. The path 201 or the path 201' serves as a blooming prevention path to drain excess charge from the N-PD to the FD to prevent blooming. As shown in fig. 2A, path 201 is directed to the FD while bypassing the VTG, thus increasing the path length and achieving only low anti-blooming capability.

Fig. 2B shows a top view (upper) and a cross-sectional view (lower) of a single pixel formed on a semiconductor substrate according to the first embodiment of the present invention. The VTG of fig. 2B has a cross-section similar to the VTG of fig. 1, as shown in top view (up), and has shallower embedded portions (corresponding to 102 of fig. 1) than the VTG of fig. 2A, as shown in cross-section (down). The VTG of fig. 2B has a larger cross-sectional area in a top view and a shallower cross-section in a side view than the VTG of fig. 2A. The N-region is disposed within the N-PD and between the VTG and the N-PD, rather than immediately adjacent to the VTG. The charge stored in the N-PD is directed to the N-region (path 202') and carried under the VTG (dashed portion of path 202) to the FD, denoted as n+. Path 202' is a side view of path 202. The path 202 or 202' serves as a blooming prevention path to drain excess charge from the N-PD to the FD to prevent blooming. As shown in fig. 2B, path 202 is transported to the FD at the VTG, providing a shorter distance and higher anti-blooming capability than path 201 in fig. 2A.

The N-region and P-region provided between the VTG and the N-PD shown in fig. 2B may be formed using a self-aligned doping process. This process is very robust and can achieve very high yields.

Fig. 3 shows a cross-sectional view along the line A-A' in fig. 1. Fig. 3 shows a region of the pixel device other than fig. 2B. Referring to fig. 3, the maximum width W of the embedded portion of the VTG is less than twice the height H of the pixel devices other than the VTG on the pixel array surface. I.e. W <2H. This relationship can avoid the problem in the related art that a slit is formed in the VTG during the manufacturing process of the VTG because the VTG is too wide. The VTG shown in fig. 3 is robust because it has no slits.

Fig. 4 shows a top view of various shapes of a VTG according to a second embodiment of the present invention. Fig. 4 (a) shows an octagonal insert 102 similar to the hexagonal protrusion 101"[" shape of fig. 1. Fig. 4 (B) shows the pentagonal protruding portion 101 and the L-shaped embedded portion 102. Fig. 4 (C) shows a hexagonal protrusion 101 and an insert 102 having three interconnected circles, similar to fig. 1. Fig. 4 (D) shows a hexagonal protrusion 101 similar to fig. 1 and an elliptical insert 102 with three interconnections. Each of the shapes shown in (a) to (D) may be determined to increase the bottom area of the embedded portion 102 while spatially separating the embedded portion 102 and the FD as much as possible. By increasing the bottom area of the VTG, high pixel charge transfer capability can be achieved. The shape and sectional area of the cross section of the protruding portion 101, the shape and sectional area of the cross section of the embedded portion 102, the relative positions of the protruding portion 101 and the PD, the relative positions of the embedded portion 102 and the PD, and the like may be changed as needed. For example, the cross-sections of the protruding portion 101 and the embedded portion 102 may be a shape including a polygon or a curve different from that shown in fig. 4, or a combination of a straight line and a curve.

Fig. 5 shows a top view of various shapes of a VTG according to a third embodiment of the present invention. In fig. 5 (a), the end of the embedded portion 102 on the adjacent PD side is located outside the end of the protruding portion 101. In fig. 5 (B), the end of the embedded portion 102 opposite to FD is outside the end of the protruding portion 101. In fig. 5 (C), the end of the embedded portion 102 on the FD side is located outside the end of the protruding portion 101. These shapes enable the pixel size to be reduced by reducing the protruding portion 101 without reducing the VTG embedding portion 102. Further, reducing the protruding portion 101 can improve the degree of freedom of layout.

Fig. 6 shows a top view of various arrangements of a VTG according to a fourth embodiment of the invention. In fig. 6 (a), the distance between the embedded parts 102 of the VTGs of the PD1 and PD2 or between the embedded parts 102 of the VTGs of the PD3 and PD4 is smaller than the distance between the embedded parts 102 of the VTGs of the PD1 and PD3 or between the embedded parts 102 of the VTGs of the PD2 and PD 4. The protrusion 101 and/or the insertion 102 in fig. 6 (a) are provided to be rotationally symmetrical at 180 degrees with respect to FD. In other words, the protruding portion 101 and/or the embedded portion 102 in (a) of fig. 6 are provided to be linearly symmetrical with a vertical line or a horizontal line passing through the FD.

In fig. 6 (B), the distances between the embedded parts 102 of the VTGs of the adjacent PDs remain equal, and each embedded part 102 is positioned offset with respect to the corresponding protruding part 101. The protrusion 101 and/or the insertion 102 in fig. 6 (B) are provided to be rotationally symmetrical at 90 degrees with respect to FD.

As shown in fig. 6 (a) and (B), the asymmetric arrangement of the VTG improves the degree of freedom of the circuit layout of the pixel array. Other asymmetric settings of the VTG may be applied as desired.

In the examples of fig. 4 to 6, the pixel unit includes 4 VTGs corresponding to 4 photodiodes PD1 to PD4, but the number of photodiodes and VTGs included in one pixel unit may be greater or less than 4.

Fig. 7 shows a cross-sectional view of various shapes of a VTG according to a fifth embodiment of the present invention. In the example shown in fig. 7 (a), the P-well on the left side of the photodiode N-PD is deeper than the P-well on the right side of the N-PD, i.e., the P-well on the FD side (denoted by n+). With this arrangement, the electric charges stored in the N-PD are efficiently transferred from the bottom of the VTG to the inside of the VTG through the N-region and to the FD, thereby improving the residual image.

In the example shown in fig. 7 (B), the embedded portion of the VTG is shallow, and the P-region and N-region between the VTG and N-PD and the P-well on the left side of the N-PD do not enter the N-PD interior. Therefore, the P-region under the VTG is not in direct contact with the N-PD, thereby preventing dark current.

In the example shown in fig. 7 (C), the N-region between the VTG and the N-PD is omitted (see fig. 7 (B)), thereby reducing manufacturing costs. Since the N-region between the embedded part of the VTG and the FD is in contact with the N-PD, a high light overflow preventing path from the N-PD to the FD through the N-region is formed.

In the example shown in fig. 7 (D), the N-region between the VTG and the N-PD is omitted (see fig. 7 (B)), and the N-region between the VTG and the FD is also omitted (see fig. 7 (C)). Since two N-regions are omitted, the manufacturing cost is further reduced.

In the example shown in fig. 7 (E), the protruding portion of the VTG is further omitted (see fig. 7 (D)). Since the tabs of the VTG cannot improve the charge transfer capability of the VTG, removing the tabs can ensure space and impart circuit layout flexibility while maintaining VTG performance.

In the example shown in fig. 7 (F), the P-well around DTI is omitted (see fig. 7 (C)). If the dark current is sufficiently suppressed in some way, for example, by a background film (which is a film having negative fixed charges), the manufacturing cost can be further reduced by omitting the P-well. For example, the background film may include SiO₂、SiN、SiON、HfO₂、Al₂O₃、AlN、ZrO₂、Ta₂O₅、TiO₂、La₂O₃、Pr2O₃、CeO₂、Nd₂O₃、Pm₂O₃、Sm₂O₃、Eu₂O₃、Gd₂O₃、Tb₂O₃、Dy₂O₃、Ho₂O₃、Er₂O₃、Tm₂O₃、Yb₂O₃、Lu₂O₃、Y₂O₃ or a combination thereof.

Fig. 8 shows a cross-sectional view of various shapes of a VTG according to a sixth embodiment of the present invention. In fig. 8 (a), the cross section of the embedded portion of the VTG is trapezoidal or tapered, with the cross section narrowing toward the bottom. In fig. 8 (B), the cross section of the embedded portion of the VTG is trapezoidal or reverse tapered, wherein the cross section widens toward the bottom. In fig. 8 (C), the cross section of the embedded portion of the VTG is a parallelogram. In fig. 8 (D), the cross section of the embedded portion of the VTG is rectangular, and has rounded corners on the N-PD side. In fig. 8 (E), the cross section of the insertion portion of the VTG is rectangular, and has rounded corners on the FD side. These or other shapes may be selected to enhance the charge transport capability of the VTG, depending on the requirements of the manufacturing process or circuit layout.

Fig. 9 shows cross-sectional views of various shapes of a PD according to a seventh embodiment of the present invention. In the example shown in (a) to (D) of fig. 9, each N-PD has structures 901 to 904 on its side facing a Color Filter (CF). The structures 901 to 904 may comprise one or more square pyramids or one or more cones, and a triangle in cross-section may correspond to one square pyramid or cone. The structures 901 to 904 reduce the reflectivity of electromagnetic radiation incident from the microlenses (microlens, ML) and improve the absorption. Structures 901 to 904 may be any other structures that achieve a similar purpose.

Fig. 10 shows various circuits of a shared pixel device according to an eighth embodiment of the present invention. The pixel device includes a transfer gate (TRANSFER GATE, TX) device, a floating diffusion node (floating diffusion, FD), a reset device (RESET DEVICE, RST), a dual conversion gain (dual conversion gain, DCG) device, an Amplifier (AMP) device, and a Selector (SEL). TX corresponds to the vertical transfer gate (VERTICAL TRANSFER GATE, VTG) device described above. A Photodiode (PD) corresponds to any one of the above-described PDs 1 to 4. AVSS1 and AVSS2 are ground or negative voltages, e.g., in the range of-5.0V to 0V. For a description of the pixel device, please refer to the description of fig. 1.

As shown in fig. 10, a pixel device may be provided for one PD (1001), shared by two PDs (1002), shared by 4 PDs (1004), shared by eight PDs (1008), or shared by any other number of PDs.

The invention is suitable for the image sensor which reads data frame by frame. A frame consists of all pixels in the array, and frame-by-frame data reading is accomplished by sequentially reading the pixel charge stored in all pixels in the array using row select transistors. Or the invention may be applied to image sensors that operate in a manner known as event-driven. In event driven image sensors, data can be output asynchronously over time in response to changes in the intensity of electromagnetic radiation incident on a pixel. In particular, when the pixel charge generated by electromagnetic radiation incident on the pixel and stored in the pixel exceeds a predetermined threshold, data is output to indicate that the intensity of the electromagnetic radiation has exceeded the threshold, or pixel coordinates and time information are combined to indicate the intensity of the electromagnetic radiation.

In some embodiments, the pixels are controlled in a global shutter manner. That is, the solid-state imaging device has a synchronous shutter function for all pixels in the voltage domain or the charge domain.

Fig. 11 shows various circuits of a pixel device according to a ninth embodiment of the present invention. Fig. 11 (a) to (D) show capacitors C1 to C4 added to the circuit of fig. 10. The capacitors C1 to C4 have a large capacitance, and may include, for example, a PN junction capacitor, a MOS capacitor, a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, a capacitor such as a capacitive DTI or polysilicon-insulator-polysilicon (PIP) capacitor, or a memory such as a dynamic random access memory (dynamic random access memory, DRAM), a Magnetoresistive Random Access Memory (MRAM), or a combination thereof.

Taking (a) as an example, one end of C1 is connected between RST and DCG, and the other end of C1 is grounded. Taking (B) as an example, one end of C2 is connected between RST and DCG, and the other end of C2 is connected to AMP and AVDD2. Taking (C) as an example, one end of C3 is connected between RST and DCG, and the other end of C3 is connected to a constant voltage Vconst. Taking (D) as an example, one end of C4 is connected between RST and DCG, and the other end of C4 is connected to the pulse voltage Vpulse.

The FD is electrically connected to any one of C1 to C4, and C1 to C4 can store excess charges, thereby increasing the full well capacity of the FD. By turning on the DCG, excess charges from Photodiodes (PDs) generated in a high-illuminance environment may remain in C1 to C4 instead of being discharged. When the solid-state imaging device operates in a high-illuminance environment, the DCG may be always on. The increased full well capacity of C1 to C4 reduces the potential variation of FD even in the presence of excess charge. Therefore, in a high-illuminance environment, the conversion gain may decrease.

Fig. 12 shows an exemplary pixel array to which an embodiment of the present invention is applied. The solid-state imaging device 1200 includes a pixel array 1201, a control circuit 1202, a readout circuit 1203, and a signal processing circuit 1204. The pixel array 1201 is a two-dimensional (2D) array of pixels, where the pixels are arranged in rows (R1 to Ry in fig. 12) and columns (C1 to Cx in fig. 12), each pixel being capable of detecting electromagnetic radiation. Each pixel may include any one of the above-described PD1 to PD 4. The control circuit 1202 generates shutter signals, row selection signals, and other control signals to control the pixel array 1201 such that each pixel in the pixel array 1201 outputs a digital signal corresponding to the detected electromagnetic radiation to the readout circuit 1203 via a bit line. The readout circuit 1203 transmits the digital signal to the signal processing circuit 1204 for further processing. The pixel array 1201 may be front-lit or back-lit.

Fig. 13 shows a cross-sectional view of a portion of an exemplary pixel array to which an embodiment of the invention is applied. Fig. 13 shows a backside deep channel isolation (DTI). In other embodiments, the foregoing DTI may be used. Color Filters (CF) are placed under microlenses (microlens, ML), PDs 1 to PD4 are mounted under CF, and TX corresponding to the above VTG is placed near PD. Other pixel devices may be implemented at the same layer as TX or at any other layer. The control circuit 1202, the readout circuit 1203, and the signal processing circuit 1204 may also be implemented at the same layer as TX. Any other layout is possible, depending on the implementation. Fig. 13 shows only one example, and a part of the structure shown in fig. 13 may be replaced with the structure shown in any one of fig. 2A, 3, and 7 to 9 described above.

Fig. 14 shows a schematic structural diagram of an exemplary solid-state imaging device to which an embodiment of the present invention is applied. The pixel array of fig. 14 may correspond to the pixel array 1201 of fig. 12, and may include the pixel unit 100 according to the present invention.

A in fig. 14 shows a standard solid-state imaging device including a pixel array, a control circuit, and a signal processing circuit mounted on a single semiconductor chip. The semiconductor substrate may be composed of a semiconductor material such as silicon or gallium. In some embodiments, the semiconductor substrate may be composed of one or more other materials that are sensitive to electromagnetic radiation, such as silicon germanium, silicon carbide, potassium arsenide, gallium phosphide, indium arsenide, indium, antimony, semiconductors on insulators, or combinations thereof.

B in fig. 14 shows a solid-state imaging device having a first semiconductor chip section and a second semiconductor chip section. The first semiconductor chip portion includes a pixel array and a control circuit, and the second semiconductor chip portion includes a signal processing circuit. The first semiconductor chip portion and the second semiconductor chip portion are electrically connected to each other to form a single semiconductor chip of the solid-state imaging device.

C in fig. 14 shows a solid-state imaging device having a first semiconductor chip section and a second semiconductor chip section. The first semiconductor chip portion includes a pixel array, and the second semiconductor chip portion includes a control circuit and a signal processing circuit. The first semiconductor chip portion and the second semiconductor chip portion are electrically connected to each other to form a single semiconductor chip of the solid-state imaging device.

D in fig. 14 shows a solid-state imaging device having a first semiconductor chip section, a second semiconductor chip section, and a third semiconductor chip section. The first semiconductor chip portion includes a pixel array, the second semiconductor chip portion includes a memory circuit, and the third semiconductor chip portion includes a control circuit and a signal processing circuit. The first semiconductor chip portion, the second semiconductor chip portion, and the third semiconductor chip portion are electrically connected to each other to form a single semiconductor chip or two semiconductor chips of the solid-state imaging device.

E in fig. 14 shows a solid-state imaging device having a first semiconductor chip section, a second semiconductor chip section, and a third semiconductor chip section. The first semiconductor chip portion includes a pixel array, the second semiconductor chip portion includes a pixel circuit, and the third semiconductor chip portion includes a control circuit and a signal processing circuit. The first semiconductor chip portion, the second semiconductor chip portion, and the third semiconductor chip portion are electrically connected to each other to form a single semiconductor chip or two semiconductor chips of the solid-state imaging device.

Fig. 15 shows a schematic block diagram of an exemplary electronic device to which embodiments of the invention are applied. The electronic device 1500 includes a lens 1501, an imaging element 1502, a Digital Signal Processing (DSP) circuit 1503, a frame memory 1504, a display unit 1505, a recording unit 1506, an operation unit 1507, a power supply unit 1508, and a bus 1509 that connects these devices together.

For example, the imaging element 1502 may be the solid-state imaging device 1200 of the present invention shown in fig. 12. The DSP circuit 1503 is a camera signal processing circuit that processes a signal supplied from the imaging element 1502. The DSP circuit 1503 outputs image data obtained by processing a signal from the imaging element 1502. The frame memory 1504 temporarily stores the image data processed by the DSP circuit 1503 in units of frames. The display unit 1505 includes a flat panel display device such as a liquid crystal panel or an organic electroluminescent (Electro Luminescence, EL) panel to display a moving image or a still image imaged by the imaging element 1502. The recording unit 1506 records image data of a moving image or a still image captured by the imaging element 1502 on a recording medium such as a semiconductor memory or a hard disk.

The operation unit 1507 outputs arithmetic instructions associated with various functions of the electronic device 1500 according to the operation of the user. The power supply unit 1508 supplies power to the DSP circuit 1503, the frame memory 1504, the display unit 1505, the recording unit 1506, and the operation unit 1507.

Fig. 16 shows an exemplary technical field to which an embodiment of the present invention is applied. For example, the solid-state imaging device according to the present invention may be included in an electronic device, an image sensor, or any other device. The solid-state imaging device according to the present invention can be applied to various fields such as sports equipment such as wearable cameras, medical devices such as endoscopes, beauty parlors, trucks or transportation devices supporting automatic/autonomous driving, entertainment devices such as cell phones, game terminals, digital cameras, video cameras, agricultural fields such as farm monitoring cameras, household appliances such as televisions and refrigerators, disaster notification systems such as monitoring cameras, network cameras, machine vision cameras, broadcasting cameras and monitoring cameras for rivers/dams/oceans/roads/construction sites, and any other fields.

Fig. 17 shows an example of applying an embodiment of the present invention to a vehicle. The vehicle 1700 includes an image sensor 1701, an image sensor 1702, an image sensor 1703, an image sensor 1704, and an image sensor 1705, which include a solid-state image sensor according to the present invention. An image sensor 1701 is located in front of the vehicle 1700 for monitoring a front area 1711 of the vehicle 1700. The image sensor 1702 is located on a left side rearview mirror of the vehicle 1700 for monitoring a left side region 1712 of the vehicle 1700. The image sensor 1703 is located at a right side rearview mirror of the vehicle 1700 for monitoring a right side area 1713 of the vehicle 1700. The image sensor 1704 is located at a rear camera of the vehicle 1700 for monitoring a rear area 1714 of the vehicle 1700. The image sensor 1705 is located at the roof of the vehicle 1700 for monitoring a region farther than the regions 1711 to 1714 or monitoring the surrounding environment of the vehicle 1700 from a position higher than the image sensors 1701 to 1704. The illustration of fig. 17 is merely an example, in other embodiments, the image sensors may be located elsewhere on the vehicle 1700 to monitor other areas, and the number of image sensors may be greater or less than the number of image sensors illustrated in fig. 17.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Accordingly, the present application is intended to cover such modifications and variations as fall within the scope of the application defined by the appended claims and their equivalents.

Claims

1. A solid-state imaging device characterized by comprising a pixel array, wherein each pixel of the pixel array comprises:

A photodiode for converting electromagnetic radiation into an electrical charge;

2. The solid-state imaging device according to claim 1, wherein,

The embedded part comprises a surface of the pixel array and a bottom surface between the photodiodes;

Each pixel includes a P-type doped region between the bottom surface and the photodiode, and an N-type doped region between the P-type doped region and the photodiode.

3. The solid-state imaging device according to claim 2, wherein,

The P-type doped region extends further to one side of the pass gate device.

4. The solid-state imaging device according to claim 1, wherein,

Each pixel includes a P-type doped region between the bottom surface and the photodiode.

5. The solid-state imaging device according to claim 4, wherein,

The P-type doped region extends further to one side of the pass gate device.

6. The solid-state imaging apparatus according to claim 2, wherein the P-type doped region and the N-type doped region are self-aligned with the transfer gate device.

7. The solid-state imaging apparatus according to claim 6, wherein a P-type well between the embedded portion and the pixel device is deeper than a P-type well between the embedded portion and the floating diffusion.

8. The solid-state imaging device according to claim 7, wherein a cross section of the embedded portion parallel to the surface of the pixel array is a combination of polygons or curves.

9. The solid-state imaging device according to claim 8, wherein,

The transfer gate device further includes a protrusion formed on a surface of the pixel array;

In the section of the embedded portion parallel to the surface of the pixel array, part or all of the polygonal side or curves are located outside the area of the protruding portion.

10. The solid-state imaging device according to claim 8, wherein the pixel array includes a pixel unit including 4 pixels coupled to the same floating diffusion node, the embedded portion included in the pixel unit being provided in a ring shape.

11. The solid-state imaging device according to claim 10, wherein the embedded portion included in the pixel unit is provided to be rotationally symmetrical by 90 degrees or rotationally symmetrical by 180 degrees with respect to the same floating diffusion node.

12. The solid-state imaging device according to claim 11, wherein in the cross section of the embedded portion parallel to the surface of the pixel array, the first wall has a first arc including a first center and a first radius, the second wall has a second arc including a second center and a second radius, and wherein the first center and the second center are both between the floating diffusion node and the transfer gate device, the first radius being smaller than the second radius.

13. The solid-state imaging device according to claim 12, wherein,

The first wall and the second wall are arranged oppositely, the embedded part further comprises a third wall and a fourth wall, and the third wall and the fourth wall are respectively connected with the first wall and the second wall;

in the cross section of the embedded portion parallel to the surface of the pixel array, part or all of one or more of the first wall, the second wall, the third wall, and the fourth wall is located outside an area of the protruding portion.

14. The solid-state imaging device according to claim 13, wherein,

The cross section of the embedded portion perpendicular to the surface of the pixel array is any one of the following shapes:

a square;

a trapezoid narrowed toward the bottom surface;

a trapezoid widening toward the bottom surface;

A parallelogram;

a substantially rectangular shape with rounded corners on one side of the bottom surface;

15. The solid-state imaging device according to claim 14, wherein a portion of an overflow path is formed between the bottom surface of the embedded portion and the photodiode or below the bottom surface of the embedded portion inside the photodiode.

16. The solid-state imaging apparatus according to claim 15, wherein the overflow path is a path that transfers photoelectric charges exceeding a full well capacity of the photodiode to the floating diffusion node.

17. An electronic device characterized by comprising the solid-state imaging device according to any one of claims 1 to 16.