CN119212489A

CN119212489A - Display panel and display device

Info

Publication number: CN119212489A
Application number: CN202411304306.6A
Authority: CN
Inventors: 张元其; 刘庭良; 李伟; 张玉欣
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2024-09-18
Filing date: 2024-09-18
Publication date: 2024-12-27

Abstract

A display panel includes: a base substrate, a display structure layer, an encapsulation structure layer, a touch structure layer and a plurality of frame signal lines. The display structure layer includes a plurality of display organic insulation layers and a plurality of display inorganic insulation layers, and the plurality of display organic insulation layers are located on a side of the plurality of display inorganic insulation layers away from the base substrate. The touch structure layer is located on a side of the encapsulation structure layer away from the base substrate, and includes a touch inorganic insulation layer; the touch inorganic insulation layer includes: a first inorganic boundary portion located in a first frame region, the first inorganic boundary portion is in direct contact with at least one display organic insulation layer, and is not in direct contact with a plurality of display inorganic insulation layers. A plurality of frame signal lines are located in the first frame region, located on a side of the plurality of display inorganic insulation layers away from the base substrate and located on a side of the touch inorganic insulation layer close to the base substrate, and a voltage difference exists between at least two adjacent frame signal lines.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

Organic LIGHT EMITTING Diode (OLED) and Quantum-dot LIGHT EMITTING Diode (QLED) are active light emitting display devices, and have advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high reaction speed, thinness, flexibility, low cost, and the like.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the application provides a display panel and a display device.

In one aspect, the embodiment provides a display panel, which comprises a substrate, a display structure layer, a packaging structure layer, a touch structure layer and a plurality of frame signal lines. The display structure layer is arranged on the substrate and comprises a plurality of display organic insulating layers and a plurality of display inorganic insulating layers, and the plurality of display organic insulating layers are arranged on one side of the plurality of display inorganic insulating layers away from the substrate. The packaging structure layer is positioned on one side of the display structure layer away from the substrate. The touch control structure layer is positioned on one side of the packaging structure layer far away from the substrate base plate and comprises a touch control inorganic insulating layer, wherein the touch control inorganic insulating layer comprises a first inorganic boundary part positioned in a first frame area, and the first inorganic boundary part is in direct contact with at least one display organic insulating layer in the plurality of display organic insulating layers and is not in direct contact with the plurality of display inorganic insulating layers. The plurality of frame signal lines are located in the first frame area, the plurality of frame signal lines are located on one side, far away from the substrate, of the plurality of display inorganic insulating layers and on one side, close to the substrate, of the touch inorganic insulating layers, and voltage differences exist between at least two adjacent frame signal lines in the plurality of frame signal lines. The display panel satisfies at least one of a front projection of a first inorganic boundary portion of the touch inorganic insulating layer on the substrate and a minimum distance between overlapping areas of the front projections of the at least two frame signal lines located at different conductive layers on the substrate is greater than 0, and a minimum distance between the front projections of the first inorganic boundary portion of the touch inorganic insulating layer on the substrate and the front projections of the at least two frame signal lines located at the same conductive layer closest to the touch inorganic insulating layer on the substrate is greater than 0.

In some exemplary embodiments, a minimum distance between the first inorganic boundary portion of the touch inorganic insulating layer and an overlapping region of the at least two bezel signal lines in front projection of the substrate is greater than 20 micrometers.

In some exemplary embodiments, the plurality of frame signal lines includes at least one first frame signal line and a plurality of second frame signal lines, the plurality of second frame signal lines being located on a same conductive layer, the first frame signal line and the plurality of second frame signal lines being located on different conductive layers, the first frame signal line configured to transmit a constant power signal, an orthographic projection of the first frame signal line on the substrate at least partially overlapping an orthographic projection of at least one of the plurality of second frame signal lines on the substrate.

In some exemplary embodiments, the display structure layer further comprises a plurality of display metal layers, and the second frame signal lines and the display metal layer closest to the touch structure layer in the plurality of display metal layers are of the same layer structure.

In some exemplary embodiments, the plurality of display metal layers include a first source drain metal layer, a second source drain metal layer and a third source drain metal layer on a side of the plurality of display inorganic insulating layers away from the substrate, the plurality of second frame signal lines and the third source drain metal layer are of a same layer structure, and the first frame signal lines are on a side of the plurality of second frame signal lines close to the substrate.

In some exemplary embodiments, the first frame region includes a first routing region, a bending region, and a second routing region sequentially disposed along a direction away from the active region, an orthographic projection of the touch inorganic insulating layer on the substrate base plate does not overlap with the bending region, and a first inorganic boundary portion of the touch inorganic insulating layer is located in the second routing region and is adjacent to the bending region.

In some exemplary embodiments, the display structure layer includes a plurality of sub-pixels located in the active area and a plurality of data lines connected to the plurality of sub-pixels. The substrate also includes a second bezel area located on the remaining side of the active area, the second bezel area being provided with a gate driving circuit configured to provide gate control signals to the plurality of sub-pixels. The first frame area further comprises at least one first signal access area which is positioned on one side, away from the bending area, of the second wiring area, and a plurality of first contact pads are arranged on the first signal access area. The second wiring area is provided with at least one first power supply switching line, a plurality of data switching lines, a plurality of first driving transmission lines, a plurality of first driving connecting lines and a plurality of second driving connecting lines, and the first power supply switching lines are configured to transmit constant first power supply signals. The plurality of data lines are connected with a part of first contact pads of the first signal access area through the plurality of data transfer lines, the plurality of first driving transmission lines and the plurality of second driving connection lines are located on two sides of the first signal access area along a first direction, the plurality of first driving transmission lines are connected with the plurality of second driving connection lines through the plurality of first driving connection lines and configured to transmit control signals provided for the grid driving circuit, and the plurality of first driving connection lines are located on one side, close to the bending area, of the first signal access area. The first frame signal line comprises the first power supply switching line, and the plurality of second frame signal lines comprise the plurality of first driving connecting lines.

In some exemplary embodiments, the plurality of first driving connection lines are located at a side of the plurality of first driving transmission lines and the plurality of second driving connection lines remote from the substrate. The first power supply switching wires are located on one side, far away from the substrate, of the plurality of data switching wires, and are located on one side, close to the substrate, of the plurality of first driving connecting wires.

In some exemplary embodiments, the first frame region further includes a second signal access region on a side of the first signal access region remote from the inflection region, the second signal access region being provided with a plurality of second contact pads. The second wiring area is also provided with a plurality of second drive transmission lines, and the second drive transmission lines and the first drive transmission lines are positioned on the same side of the first signal access area. The plurality of second contact pads comprise at least one first group of second contact pads, at least one second group of second contact pads and at least one third group of second contact pads, wherein the first group of second contact pads are connected with a part of the first contact pads in the first signal access area, the second group of second contact pads are connected with the plurality of second driving transmission lines, the third group of second contact pads are connected with the plurality of second driving connection lines, and the second group of second contact pads and the third group of second contact pads are positioned on two sides of the first group of second contact pads.

In some exemplary embodiments, the second routing area is provided with at least one second power supply patch cord configured to transmit a constant second power supply signal, and a plurality of touch patch cords. The first frame signal line comprises the second power supply switching line, and the plurality of second frame signal lines comprise the plurality of touch switching lines.

In some exemplary embodiments, the display panel further includes an auxiliary organic insulating layer at the first frame region, the auxiliary organic insulating layer being at a side of the plurality of display organic insulating layers remote from the substrate, and at a side of the touch inorganic insulating layer close to the substrate. And the orthographic projection of the auxiliary organic insulating layer on the substrate covers the orthographic projection of the at least two frame signal lines on the substrate.

In some exemplary embodiments, the orthographic projection of the first inorganic boundary portion of the touch inorganic insulating layer on the substrate overlaps with the orthographic projection portion of the auxiliary organic insulating layer on the substrate.

In some exemplary embodiments, the touch structure layer comprises a touch barrier layer, a first touch conductive layer, a touch interlayer insulating layer, a second touch conductive layer and a touch protective layer which are sequentially arranged on the packaging structure layer, wherein the touch inorganic insulating layer comprises the touch barrier layer or comprises the touch barrier layer and the touch interlayer insulating layer.

In another aspect, the present embodiment provides a display device including the display panel as described above.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the principles of the application, and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the principles of the application.

FIG. 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

FIG. 2 is a schematic partial plan view of a touch area of a display panel according to at least one embodiment of the disclosure;

FIG. 3A is a schematic partial cross-sectional view of an active area of a display panel according to at least one embodiment of the present disclosure;

FIG. 3B is another schematic partial cross-sectional view of an active area of a display panel according to at least one embodiment of the present disclosure;

FIG. 3C is another schematic partial cross-sectional view of an active area of a display panel according to at least one embodiment of the present disclosure;

FIG. 4 is a schematic partial plan view of a first frame region of a display panel according to at least one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a partial trace of the region S1 in FIG. 4;

FIG. 6 is a schematic plan view of a portion of the region S1 in FIG. 4;

FIG. 7 is a schematic plan view of a portion of the region S2 in FIG. 4;

FIG. 8A is a schematic view of a partial section along the direction PP' in FIG. 6;

FIG. 8B is a schematic partial cross-sectional view along QQ' in FIG. 6;

FIG. 8C is another partial cross-sectional view taken along the direction PP' in FIG. 6;

FIG. 9 is a partial plan view of the schematic diagram of FIG. 5;

FIG. 10A is a schematic view of a partial cross section along the RR' direction in FIG. 9;

fig. 10B is a schematic partial cross-sectional view along UU' in fig. 9;

fig. 11 is a schematic diagram of a display device according to at least one embodiment of the disclosure.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be implemented in a number of different forms. One of ordinary skill in the art will readily recognize the fact that the manner and content may be changed into other forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.

In the drawings, the size of one or more constituent elements, thicknesses of layers or regions may be exaggerated for clarity. Accordingly, one aspect of the present disclosure is not necessarily limited to this dimension, and the shape and size of one or more components in the drawings do not reflect true proportions. Further, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or numerical values shown in the drawings, and the like.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number. The term "plurality" in this disclosure means two or more in number.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the described constituent elements. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, they may be fixedly connected or detachably connected or integrally connected, they may be mechanically connected or connected, they may be directly connected or indirectly connected through intermediate members or communicate between the inside of the two elements. The meaning of the above terms in the present disclosure can be understood by one of ordinary skill in the art as appropriate. Where "connected" may include "electrically connected," the term "electrically connected" may include the case where constituent elements are connected together by elements having some electrical action. The "element having a certain electric action" is not particularly limited as long as it can transmit an electric signal between the connected constituent elements. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In this specification, a transistor refers to an element including at least three terminals of a gate electrode (gate electrode), a drain electrode, and a source electrode. The transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and a current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first pole may be a drain electrode, the second pole may be a source electrode, or the first pole may be a source electrode, and the second pole may be a drain electrode. In addition, the gate may also be referred to as a control electrode. In the case of using transistors having opposite polarities, or in the case of a change in current direction during circuit operation, the functions of the "source" and the "drain" may be exchanged with each other. Thus, in this specification, "source" and "drain" may be interchanged.

In the present specification, "parallel" means a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and therefore, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like is not strictly defined, and may be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, an approximate hexagon, or the like, and some small deformation due to a tolerance may exist, for example, a lead angle, an arc edge, deformation, or the like may exist.

The terms "about" and "approximately" as used herein refer to a situation where the limits are not strictly defined and where process and measurement errors are permitted. In this disclosure, "identical" includes cases where the values differ by less than 10%, such as cases where the values differ by less than 5%.

In this specification, a extending along the B direction means that a may include a main body portion and a sub portion connected to the main body portion, the main body portion being a line, a segment or a bar-like body, the main body portion extending along the B direction, and the main body portion extending along the B direction for a length greater than that of the sub portion extending along the other direction. The phrase "a extends in the B direction" in this specification means that the main body portion of a extends in the B direction.

The phrase "A and B are of the same layer structure" in the present specification means that A and B are formed simultaneously by the same patterning process. "identical layers" does not always mean that the thickness of the layers or the height of the layers are identical in cross-section. "the front projection of A includes the front projection of B" means that the front projection of B falls within the front projection range of A, or that the front projection of A covers the front projection of B.

In some implementations, the display panel may integrate the touch structure. The display panel may include a Liquid Crystal Display (LCD) substrate, or may be an Organic Light Emitting Diode (OLED) display substrate, or may be a plasma display device (PDP) display substrate, or may be an electrophoretic display (EPD) display substrate. For example, the display panel may include an OLED display substrate and a touch structure. The Touch structure may be disposed on the encapsulation layer of the display substrate, forming a structure with the Touch structure on the thin film encapsulation (Touch on Thin Film Encapsulation, touch on TFE for short). The display structure and the touch structure are integrated together, have advantages such as frivolous, collapsible, can satisfy product demands such as flexible folding, narrow frame.

In some examples, touch On TFE structures mainly include Flexible Multi-Layer overlay On Cell (FMLOC) structures and Flexible Single-Layer overlay On Cell (FSLOC) structures. FMLOC is based on the principle of mutual capacitance detection, and generally adopts two conductive layers to form a driving (Tx) electrode and an induction (Rx) electrode, and an integrated circuit (IC, INTEGRATED CIRCUIT) realizes touch control by detecting the mutual capacitance between the driving electrode and the induction electrode. FSLOC is based on the working principle of self-capacitance (or voltage) detection, and generally adopts a single conductive layer to form a touch electrode, and an integrated circuit realizes touch action by detecting the self-capacitance (or voltage) of the touch electrode.

The inventor notes in the research that in the display panel integrating the display structure and the touch structure, a touch inorganic insulating layer is arranged before the preparation of the conductive layer of the touch structure or between adjacent conductive layers of the touch structure, and the edge position of the touch inorganic insulating layer can be in direct contact with the inorganic insulating layer in the display structure to form an inorganic closed space, so that water vapor cannot enter. However, when the touch inorganic insulating layer has a boundary that cannot be in direct contact with the inorganic insulating layer in the display structure (for example, a boundary of the touch inorganic insulating layer located at a side of the bending region away from the display region) and the boundary is closer to the conductive layer of the display structure, if moisture intrusion occurs in the boundary, the moisture cannot overflow in the reliability process, which easily causes direct electrochemical corrosion of the signal trace of the conductive layer of the display structure. When a voltage difference exists between the signal wires, the corrosion condition of the signal wires is further aggravated.

The embodiment provides a display panel and a display device, which can improve the condition that signal wiring is corroded in the process of reliability.

The embodiment provides a display panel which comprises a substrate, a display structure layer, a packaging structure layer, a touch structure layer and a plurality of frame signal lines. The display structure layer is arranged on the substrate and comprises a plurality of display organic insulating layers and a plurality of display inorganic insulating layers, and the plurality of display organic insulating layers are arranged on one side of the plurality of display inorganic insulating layers away from the substrate. The packaging structure layer is positioned on one side of the display structure layer away from the substrate. The touch control structure layer is positioned on one side of the packaging structure layer far away from the substrate base plate and comprises a touch control inorganic insulating layer, wherein the touch control inorganic insulating layer comprises a first inorganic boundary part positioned in a first frame area, and the first inorganic boundary part is in direct contact with at least one display organic insulating layer in the plurality of display organic insulating layers and is not in direct contact with the plurality of display inorganic insulating layers. The plurality of frame signal lines are located in the first frame area, the plurality of frame signal lines are located on one side, far away from the substrate, of the plurality of display inorganic insulating layers and on one side, close to the substrate, of the touch inorganic insulating layers, and voltage differences exist between at least two adjacent frame signal lines in the plurality of frame signal lines. The display panel satisfies at least one of a front projection of a first inorganic boundary portion of the touch inorganic insulating layer on the substrate and a minimum distance between overlapping areas of the front projections of the at least two frame signal lines located at different conductive layers on the substrate is greater than 0, and a minimum distance between the front projections of the first inorganic boundary portion of the touch inorganic insulating layer on the substrate and the front projections of the at least two frame signal lines located at the same conductive layer closest to the touch inorganic insulating layer on the substrate is greater than 0.

In some examples, adjacent bezel signal lines may include bezel signal lines that are adjacent to each other in a plane parallel to the substrate, such as bezel signal lines that are located in the same conductive layer and have no other traces between each other, and bezel signal lines that are adjacent to each other in a direction perpendicular to the plane of the substrate, such as bezel signal lines that are located in adjacent conductive layers and have no other traces between each other in a direction perpendicular to the substrate.

In some examples, the plurality of frame signal lines with voltage differences are adjacent along a plane parallel to the substrate and located in the same conductive layer closest to the touch inorganic insulating layer, and then in the first frame region, the minimum distance between the front projection of the first inorganic boundary portion of the touch inorganic insulating layer on the substrate and the front projection of the plurality of frame signal lines with voltage differences on the substrate is greater than 0. In other words, in the first frame region, the first inorganic boundary portion of the touch inorganic insulating layer and the orthographic projections of the plurality of adjacent frame signal lines with the voltage difference on the substrate may not overlap.

In some examples, the plurality of frame signal lines with voltage differences are adjacent along the direction perpendicular to the substrate, and in the first frame area, the minimum distance between the front projection of the first inorganic boundary portion of the touch inorganic insulating layer on the substrate and the overlapping area of the front projection of the plurality of frame signal lines with voltage differences on the substrate is greater than 0. In other words, in the first frame area, the front projection of the first inorganic boundary portion of the touch inorganic insulating layer on the substrate and the overlapping area of the front projection of the plurality of frame signal lines with the voltage difference on the substrate may not overlap.

In some examples, the presence of a voltage difference between two bezel signal lines may mean that the two bezel signal lines are configured to transmit different signals. For example, one of the frame signal lines transmits a constant voltage signal, and the other frame signal line transmits a pulse signal. For another example, two frame signal lines transmit pulse signals, wherein when one frame signal line transmits a high-level signal, the other frame signal line transmits a low-level signal.

According to the display panel provided by the embodiment, the touch inorganic insulating layer is removed at the positions of the plurality of frame signal lines with the voltage difference, so that the corrosion of the frame signal lines caused by the invasion of water vapor from the first inorganic boundary part of the touch inorganic insulating layer, which is not in direct contact with the inorganic insulating layer of the display structure layer, can be improved. According to the embodiment, the corrosion condition of the frame signal line of the first frame area in the reliability process can be improved, and the display defect caused by the corrosion condition is avoided.

In some exemplary embodiments, a minimum distance between an orthographic projection of the first inorganic boundary portion of the touch inorganic insulating layer on the substrate and an overlapping region of orthographic projections of the at least two bezel signal lines having the voltage difference on the substrate may be greater than 20 micrometers. The distance setting of this example can improve the corruption condition of steam invasion to the frame signal line.

In some exemplary embodiments, the plurality of bezel signal lines may include at least one first bezel signal line and a plurality of second bezel signal lines. The plurality of second frame signal lines may be located in the same conductive layer, and the first frame signal line and the plurality of second frame signal lines may be located in different conductive layers. The first frame signal line may be configured to transmit a constant power signal, and a front projection of the first frame signal line on the substrate and a front projection of at least one of the plurality of second frame signal lines on the substrate may at least partially overlap. In some examples, the display structure layer may further include a plurality of display metal layers, and the plurality of second frame signal lines and the display metal layer closest to the touch structure layer among the plurality of display metal layers may have a same layer structure. For example, the plurality of display metal layers may include a first source drain metal layer, a second source drain metal layer and a third source drain metal layer on a side of the plurality of inorganic insulating layers of the display structure layer away from the substrate, the plurality of second frame signal lines and the third source drain metal layer may have a same layer structure, and the first frame signal lines may be located on a side of the plurality of second frame signal lines close to the substrate.

In some exemplary embodiments, the first frame region may include a first routing region, a bending region, and a second routing region sequentially disposed in a direction away from the effective region. The orthographic projection of the touch inorganic insulating layer on the substrate and the bending area can be free from overlapping, and the first inorganic boundary part of the touch inorganic insulating layer can be positioned in the second wiring area and adjacent to the bending area. In some examples, in order to ensure bending performance of the bending region, the bending region is not provided with a touch inorganic insulating layer, and the touch inorganic insulating layer comprises a first inorganic boundary portion near the bending region in the second routing region, wherein an edge of the first inorganic boundary portion can face the bending region. Since the first inorganic boundary portion is in direct contact with the display organic insulating layer of the display structure layer, and does not contact with the display inorganic insulating layer to form an inorganic closed space, there is a risk that moisture intrudes along an edge position of the first inorganic boundary portion. In the embodiment, the position relationship between the first inorganic boundary part of the touch inorganic insulating layer and the plurality of frame signal lines with voltage differences is adjusted in the second wiring area, so that the wiring corrosion condition existing in the setting area of the frame signal lines with voltage differences can be improved, and the abnormal display caused by the wiring corrosion condition is avoided.

In some exemplary embodiments, the first frame signal line and the plurality of second frame signal lines are both located in the second routing area. The first frame signal line may include at least one of a first power supply patch cord transmitting a first power supply signal, and a second power supply patch cord transmitting a second power supply signal. Wherein the first power signal may be greater than the second power signal. The plurality of second frame signal lines may include at least one of a plurality of first driving connection lines and a plurality of touch patch cords. The front projection of the first power supply switching wire on the substrate can at least partially overlap with the front projection of the at least one first driving connecting wire on the substrate, and the front projection of the second power supply switching wire on the substrate can at least partially overlap with the front projection of the at least one touch switching wire on the substrate.

In some exemplary embodiments, the display panel may further include an auxiliary organic insulating layer located in the first frame region, the auxiliary organic insulating layer being located at a side of the plurality of display organic insulating layers away from the substrate, and at a side of the touch inorganic insulating layer near the substrate, and an orthographic projection of the auxiliary organic insulating layer on the substrate may cover orthographic projections of the at least two frame signal lines on the substrate. In some examples, the orthographic projection of the first inorganic boundary portion of the touch inorganic insulating layer on the substrate and the orthographic projection of the auxiliary organic insulating layer on the substrate may partially overlap. This example can guarantee the cladding to many frame signal lines through setting up supplementary organic insulating layer.

The scheme of the present embodiment is illustrated by some examples below.

Fig. 1 is a schematic diagram of a display panel according to at least one embodiment of the disclosure. Fig. 1 is a schematic plan view of a display panel before a bending process is performed. In some examples, as shown in FIG. 1, the display panel may include an active area AA, and a bezel area BB surrounding the active area AA. For example, the frame region BB may include a first frame region B1 located at one side of the effective region AA, and a second frame region (e.g., may include an upper frame region B2, a left frame region B3, and a right frame region B4) located at the other side of the effective region AA. The first frame area B1 may be a lower frame of the display panel.

In some examples, as shown in fig. 1, the active area (ACTIVE AREA) AA may be a flat area configured to display a moving picture or a still image, and may also be configured to perform touch sensing. The effective area AA may be a display area or a touch area, and both the touch area and the display area in the following description refer to the effective area AA. In some examples, the active area AA may be rectangular, such as a rounded rectangle. In other examples, the active area AA may be circular or elliptical in other shapes. In other examples, the display panel may be a flexible panel, and thus the display panel may be changeable, such as curled, bent, folded, or rolled.

In some examples, as shown in fig. 1, the active area AA may include a plurality of subpixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of sub-pixels PX may be arrayed along the first direction D1 and the second direction D2. The first direction D1 crosses the second direction D2, for example, the first direction D1 may be perpendicular to the second direction D2. The plurality of gate lines GL may extend in the first direction D1 and be arranged in the second direction D2. The plurality of data lines DL may extend in the second direction D2 and be arranged in the first direction D1. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may cross to form a plurality of sub-pixel regions, and one sub-pixel PX may be disposed in each sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX and configured to supply data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX and configured to supply gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signal may include a scan signal and a light emission control signal, or may include a scan signal, a light emission control signal, and a reset control signal.

In some examples, as shown in fig. 1, the first direction D1 may be a direction parallel to an extending direction of the gate line GL in the display area AA, the first direction D1 may be also referred to as a row direction, and the second direction D2 may be a direction parallel to an extending direction of the data line DL in the display area AA, and the second direction D2 may be also referred to as a column direction.

In some examples, one pixel unit of the active area AA may include three sub-pixels, which may be red, green, and blue sub-pixels, respectively. In other examples, one pixel unit may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively, or four sub-pixels may include one red sub-pixel, one blue sub-pixel, and two green sub-pixels.

In some examples, one subpixel may include a pixel circuit and a light emitting element electrically connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Wherein, T in the circuit structure refers to a thin film transistor, C refers to a capacitor, the number in front of T represents the number of the thin film transistors in the circuit, and the number in front of C represents the number of the capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit may be P-type transistors or may be N-type transistors. The same type of transistor is adopted in the pixel circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In other examples, the plurality of transistors in the pixel circuit may include a P-type transistor and an N-type transistor.

In some examples, the plurality of transistors in the pixel circuit may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (LTPS, low Temperature Poly-Silicon), and the active layer of the Oxide thin film transistor adopts Oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, the Oxide thin film transistor has the advantages of low leakage current and the like, and the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display panel, namely an LTPS+oxide (LTPO) display panel, so that the advantages of the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

In some examples, the light emitting element may be any one of a light emitting Diode (LED, light Emitting Diode), an Organic LIGHT EMITTING Diode (OLED), a Quantum Dot LIGHT EMITTING Diode (QLED), a micro LED (including a mini-LED or micro-LED), and the like. For example, the light emitting element may be an OLED, and the light emitting element may emit red light, green light, blue light, white light, or the like under the driving of its corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined according to the need. In some examples, the light emitting element may include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element may be electrically connected to a corresponding pixel circuit. However, the present embodiment is not limited thereto.

In some examples, the shape of the light emitting elements of the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal. When one pixel unit comprises three sub-pixels, the light emitting elements of the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or horizontal character form, and when one pixel unit comprises four sub-pixels, the light emitting elements of the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or square form. However, the present embodiment is not limited thereto.

Fig. 2 is a schematic partial plan view of a touch area of a display panel according to at least one embodiment of the disclosure. In some examples, as shown in fig. 2, in which the display panel is integrated with a mutual capacitive touch structure, and a FMLOC structure is formed, the touch area AA may include a plurality of first touch units 530 and a plurality of second touch units 540. The first touch unit 530 may extend along the first direction D1, the plurality of first touch units 530 may be sequentially arranged along the second direction D2, the second touch unit 540 may extend along the second direction D2, and the plurality of second touch units 540 may be sequentially arranged along the first direction D1. Each of the first touch units 530 may include a plurality of first touch electrodes 531 and first connection parts 532 sequentially arranged along the first direction D1, and the first touch electrodes 531 and first connection parts 532 may be alternately disposed and sequentially connected. Each of the second touch units 540 may include a plurality of second touch electrodes 541 sequentially arranged along the second direction D2, the plurality of second touch electrodes 541 may be disposed at intervals, and adjacent second touch electrodes 541 may be connected to each other through the second connection portion 542. In some examples, the film layer of the second connection portion 542 may be different from the film layer of the first touch electrode 531 and the second touch electrode 541.

In some examples, as shown in fig. 2, the first touch electrode 531 and the second touch electrode 541 may be in the form of transparent conductive electrodes. In other examples, the first touch electrode 531 and the second touch electrode 541 may be in the form of a metal mesh, which may be formed by interleaving a plurality of metal wires, and the metal mesh may include a plurality of mesh patterns, which may be a polygon formed by a plurality of metal wires. The first touch electrode 531 and the second touch electrode 541 of metal mesh format have advantages of small resistance, small thickness, and fast reaction speed.

In some examples, as shown in fig. 2, the first touch electrode 531 and the second touch electrode 541 may have rhombic shapes, for example, may be a regular diamond, or a horizontally long diamond, or a vertically long diamond. In other examples, the first touch electrode 531 and the second touch electrode 541 may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, and embodiments of the present disclosure are not limited herein.

Fig. 3A is a schematic partial cross-sectional view illustrating an active area of a display panel according to at least one embodiment of the present disclosure. Fig. 3A illustrates an example of a structure of one sub-pixel of the active region. In this example, the same type of transistors in the pixel circuit is taken as an example, and for example, low-temperature polysilicon thin film transistors may be used for the transistors in the pixel circuit. In other examples, the plurality of transistors in the pixel circuit may employ low temperature polysilicon thin film transistors and oxide thin film transistors. In addition, in this example, a display panel integrated with a mutual capacitive touch structure and a FMLOC structure are taken as an example for illustration.

In some examples, as shown in fig. 3A, in a direction perpendicular to the display panel, an active area of the display panel may include a substrate base 10, and a circuit structure layer 20, a light emitting structure layer 30, a package structure layer 40, and a touch structure layer 50 sequentially disposed on the substrate base 10. The display structure layer may include a circuit structure layer 20 and a light emitting structure layer 30. The circuit structure layer 20 may include at least a pixel circuit of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light emitting structure layer 30 may include at least light emitting elements of a plurality of sub-pixels. The touch structure layer 50 uses the encapsulation structure layer 40 as a substrate. In some possible implementations, other film layers (e.g., color filter layers) may be disposed between the touch structure layer 50 and the encapsulation structure layer 40, which is not limited herein.

In some examples, the substrate base 10 may include a first flexible material layer, a first inorganic material layer, a base semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, the materials of the first flexible material layer and the second flexible material layer may be Polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water-oxygen resistance of the substrate base 10, and the materials of the base semiconductor layer may be amorphous silicon (a-Si). However, the present embodiment is not limited thereto.

In some examples, one thin film transistor 21 and one capacitor 22 included in each sub-pixel are illustrated in fig. 3A as an example. In some examples, the circuit structure layer 20 of the active region may include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source drain metal layer, a second source drain metal layer, and a third source drain metal layer disposed on the substrate base plate 10. The plurality of display metal layers of the display structure layer of the present example may include a first gate metal layer, a second gate metal layer, a first source drain metal layer, a second source drain metal layer, and a third source drain metal layer. A first gate insulating layer 101 may be disposed between the semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 103 may be disposed between the second gate metal layer and the first source drain metal layer, a passivation layer 104 and a first planarization layer 105 may be disposed between the first source drain metal layer and the second source drain metal layer, a second planarization layer 106 may be disposed between the second source drain metal layer and the third source drain metal layer, and a third planarization layer 107 may be disposed on a side of the third source drain metal layer away from the substrate 10. The plurality of display inorganic insulating layers of the display structure layer may include a first gate insulating layer 101, a second insulating layer 102, an interlayer insulating layer 103, and a passivation layer 104, and the plurality of display organic insulating layers of the display structure layer may include a first planarization layer 105, a second planarization layer 106, and a third planarization layer 107. However, the present embodiment is not limited thereto. In other examples, a buffer layer may be further disposed on a side of the semiconductor layer near the substrate, and the buffer layer may prevent harmful substances in the substrate from invading into the display panel, and may further increase adhesion of a film layer in the display panel on the substrate. In other examples, a Bottom light shielding metal layer (BSM, bottom SHIELDING METAL) may be disposed on a side of the buffer layer near the substrate, and the Bottom light shielding metal layer may be configured to at least partially cover an active layer of the thin film transistor of the pixel circuit to avoid external light from affecting the performance of the thin film transistor.

In some examples, the first gate metal layer, the second gate metal layer, the first source drain metal layer, the second source drain metal layer, and the third source drain metal layer may be made of a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), and may be a single-layer structure, or a multi-layer composite structure such as Ti/Al/Ti, or the like. The semiconductor layer may be made of amorphous indium gallium zinc Oxide (a-IGZO), zinc oxynitride (ZnON), indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene or polythiophene, etc., i.e., the present disclosure is applicable to transistors manufactured based on Oxide (Oxide) technology, silicon technology or organic technology.

In some examples, as shown in FIG. 3A, the semiconductor layer of the active area may include an active layer 210 of a thin film transistor 21. The active layer 210 of the thin film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 between the first region 2101 and the second region 2102. The first gate metal layer may include a gate 213 of the thin film transistor 21 and a first plate 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin film transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 10. The second gate metal layer may include a second plate 222 of the capacitor 22. The second plate 222 and the first plate 221 of the capacitor 22 may at least partially overlap in the orthographic projection of the substrate 10, e.g. the two may coincide. The first source drain metal layer may include a source electrode 211 and a drain electrode 212 of the thin film transistor 21. The interlayer insulating layer 103 may be provided with a plurality of via holes (e.g., including a first pixel via hole and a second pixel via hole) in the active region, the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the first pixel via hole may be removed to expose at least a portion of the surface of the first region 2101 of the active layer 210, and the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the second pixel via hole may be removed to expose at least a portion of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through a first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through a second pixel via. The second source drain metal layer may include a first switching electrode 231. The first switching electrode 231 may be electrically connected to the drain electrode 212 of the thin film transistor 21 of the pixel circuit through a third pixel via hole formed in the passivation layer 104 and the first planarization layer 105. The third source drain metal layer may include a second transfer electrode 232. The second switching electrode 232 may be electrically connected to the first switching electrode 231 located in the second source-drain metal layer through a fourth pixel via formed in the second planarization layer 106. The second switching electrode 232 may be electrically connected to the first electrode 301 (e.g., anode) of the light emitting element through a fifth pixel via formed in the third planarization layer 107. The present example may realize an electrical connection between the pixel circuit and the light emitting element through the first switching electrode 231 and the second switching electrode 232.

In some examples, the gate line of the active region may be located in the first gate metal layer, the data line of the active region may be located in the second source drain metal layer or the third source drain metal layer, and the high-potential power line of the active region may be located in at least one of the second source drain metal layer and the third source drain metal layer, for example. The present embodiment is not limited thereto. The circuit structure layer of this example can include three source drain metal layers, can avoid arranging more wiring in the single source drain metal layer to be favorable to realizing narrow frame structure.

In some examples, as shown in FIG. 3A, the light emitting structure layer 30 may include a pixel definition layer 304 and a plurality of light emitting elements. For example, each light emitting element may include a first electrode 301, an organic light emitting layer 302, and a second electrode 303 stacked. The first electrode 301 of the light emitting element may be an anode, and the first electrode 301 may be disposed on the third flat layer 107 and electrically connected to the second switching electrode 232 through a fifth pixel via formed in the third flat layer 107. The pixel defining layer 304 is disposed on the first electrode 301 and the third planarization layer 107, and the pixel defining layer 304 may be provided with a plurality of pixel openings, and one pixel opening may expose at least a portion of a surface of a corresponding one of the first electrodes 301. At least a portion of the organic light emitting layer 302 may be disposed within one pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light emitting layer 302 and connected to the organic light emitting layer 302. The organic light emitting layer 302 may emit light of a corresponding color under the driving of the first electrode 301 and the second electrode 303. The side of the pixel defining layer 304 remote from the substrate 10 may also be provided with a spacer layer, which may include a Plurality of Spacers (PS). In some examples, the pixel defining layer 434 may be made of polyimide, acryl, or polyethylene terephthalate, or the like.

In some examples, the organic light emitting Layer 302 of the light emitting element may include a light emitting Layer (EML, emitting Layer), and one or more film layers including a Hole injection Layer (HIL, hole Injection Layer), a Hole transport Layer (HTL, hole Transport Layer), a Hole Blocking Layer (HBL), an electron blocking Layer (EBL, electron Block Layer), an electron injection Layer (EIL, electron Injection Layer), and an electron transport Layer (ETL, electron Transport Layer). The first electrode 301 and the second electrode 303 can emit light according to a desired gray scale by using the light emission characteristics of the organic material.

In some examples, the light emitting layers of the different color light emitting elements may be different. For example, the red light emitting element includes a red light emitting layer, the green light emitting element includes a green light emitting layer, and the blue light emitting element includes a blue light emitting layer. In order to reduce the process difficulty and improve the yield, a common layer may be used for the hole injection layer and the hole transport layer on one side of the light emitting layer, and a common layer may be used for the electron injection layer and the electron transport layer on the other side of the light emitting layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer may be fabricated by one process (one evaporation process or one inkjet printing process), and isolation may be achieved by a surface level difference of the formed film layer or by surface treatment or the like. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light emitting layer may be formed by evaporation using a fine metal reticle (FMM, fine Metal Mask) or an Open Mask (Open Mask), or by an inkjet process.

In some examples, as shown in fig. 3A, the encapsulation structure layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of an inorganic material, the second encapsulation layer 402 may be made of an organic material, and the second encapsulation layer 402 may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403, so as to ensure that external moisture cannot enter the light emitting element. However, the present embodiment is not limited thereto. For example, the encapsulation structure layer may adopt an inorganic/organic/inorganic five-layer stacked structure.

In some examples, as shown in fig. 3A, the Touch structure layer 50 of the active area may include a Touch barrier layer (TBL, touch Barrier Layer) 501, a first Touch conductive layer (TMA, touch Metal a) 511, a Touch interlayer insulating layer (TLD) 502, a second Touch conductive layer (TMB, touch Metal B) 512, and a Touch protection layer (OC, optical Cover) 503, which are sequentially disposed in a direction perpendicular to the display panel.

In some examples, the first touch conductive layer 511 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connection parts, which may be formed through the same patterning process, and may be an integrally connected structure. The second touch conductive layer 512 may include a plurality of second connection portions, and the second connection portions may be connected to adjacent second touch electrodes through vias formed in the touch interlayer insulating layer 502. In other examples, the first touch conductive layer may include the first touch electrode, the second touch electrode, and the first connection, and the second touch conductive layer may include the second connection.

In some examples, the first touch electrode may be a driving (Tx) electrode and the second touch electrode may be a sensing (Rx) electrode. Or the first touch electrode may be a sense (Rx) electrode and the second touch electrode may be a drive (Tx) electrode.

In some examples, the touch barrier layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, and the touch protection layer 503 may be an organic insulating layer. For example, the touch barrier layer 501 and the touch interlayer insulating layer 502 may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. Polyimide (PI) or the like may be used as the touch protection layer 503. In this example, the touch inorganic insulating layer may include a touch barrier layer 501 and a touch interlayer insulating layer 502.

In other examples, the touch blocking layer 501 may be an inorganic insulating layer, and the touch interlayer insulating layer 502 and the touch protection layer 503 may be organic insulating layers. By arranging the touch interlayer insulating layer 502 as an organic insulating layer, the problem of cracks generated in the reliability test of the display panel (such as the problem of cracks generated in the inverted arch test of the foldable display panel) can be improved, so that the bending resistance of the display panel is improved, and the product yield and the competitiveness of the display panel are improved. In this example, the touch inorganic insulating layer may include a touch barrier layer 501.

In some examples, the first and second touch conductive layers 511 and 512 may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, ITO/Ag/ITO, or the like.

Fig. 3B is another schematic partial cross-sectional view of an active area of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in fig. 3B, only the first planarization layer 105 may be disposed between the first source drain metal layer and the second source drain metal layer of the circuit structure layer 20, and the passivation layer may be omitted. The rest of the structure of the display panel of this example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

Fig. 3C is another schematic partial cross-sectional view of an active area of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in fig. 3C, the present example illustrates the display panel integrated with the self-contained touch structure to form FSLOC structures. The touch structure layer 50 of the active area AA may include a touch barrier layer 501, a first touch conductive layer 511, and a touch protective layer 503 sequentially disposed in a direction perpendicular to the display panel. The first touch conductive layer 511 may include a plurality of touch electrodes. The touch blocking layer 501 may be an inorganic insulating layer, and the touch protection layer 503 may be an organic insulating layer. In this example, the touch inorganic insulating layer may include a touch barrier layer 501. The rest of the structure of the display panel of this example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

In some examples, as shown in FIG. 1, the touch structure layers of the left and right bezel areas B3 and B4 of the display panel may each include a plurality of touch outgoing lines 521. The plurality of touch outgoing lines 521 may be electrically connected to the first touch unit and the second touch unit in the active area AA, respectively. Taking the film structure shown in fig. 3A as an example, the touch outgoing lines 521 may be located in the first touch conductive layer or in the second touch conductive layer, or the touch outgoing lines 521 may be alternately arranged in the first touch conductive layer and the second touch conductive layer.

Fig. 4 is a schematic partial plan view of a first frame area of a display panel according to at least one embodiment of the disclosure. In some examples, as shown in fig. 1 and 4, the first frame region B1 of the display panel may include a first routing region B11, a bent region B12, and a second routing region B13 sequentially disposed in a direction away from the effective region AA. The first routing area B11 may be connected to the active area AA, and the first routing area B11 may be provided with at least a first power frame line 411, a second power frame line 412, a plurality of display outgoing lines, and a plurality of touch outgoing lines 521. The first power frame line 411 may extend in the first direction D1 in the first routing area B11 and may be configured to connect to a high potential power line in the active area AA, and the second power frame line 412 may extend in the first direction D1 in the first routing area B11 and may be configured to connect to a low potential power line in the third and fourth frame areas B13 and B14.

In some examples, the first power bezel 411 may be a dual-layer wiring structure, for example, including a first power wiring layer and a second power wiring layer, the first power wiring layer may be in a same layer structure with a first source drain metal layer of the active area, and the second power wiring layer may be in a same layer structure with a second source drain metal layer of the active area. The first power supply wiring layer and the second power supply wiring layer can be lapped in a large area by digging grooves formed by the first flat layer. The second power supply wiring layer can extend to the effective area and is connected with a high-potential power supply wire in the effective area.

In some examples, the second power frame line 412 may be a three-layer wiring structure, for example, including a third power wiring layer, a fourth power wiring layer, and a fifth power wiring layer, where the third power wiring layer may be in a same layer structure as the first source drain metal layer of the active area, the fourth power wiring layer may be in a same layer structure as the second source drain metal layer of the active area, and the fifth power wiring layer may be in a same layer structure as the third source drain metal layer of the active area. The third power supply wiring layer and the fourth power supply wiring layer can be lapped in a large area by digging out a groove formed by the first flat layer, and the fifth power supply wiring layer can be connected with the fourth power supply wiring layer through a plurality of through holes formed in the second flat layer. The fifth power supply wiring layer can be connected with a plurality of low-potential power supply connecting wires positioned in the third source drain metal layer in the effective area, for example, can be of an integrated structure, and realizes electric connection with the second power supply frame wire in the upper frame area.

In some examples, as shown in fig. 1, the plurality of display pins in the first routing area B11 may include at least a plurality of data pins 251, a plurality of driving pins (not shown). The plurality of data pinouts 251 may be electrically connected to the plurality of data lines DL within the active area AA, for example, the plurality of data pinouts 251 and the plurality of data lines DL may be electrically connected in one-to-one correspondence. The plurality of data outgoing lines 251 may be disposed in the first routing area B11 in a fanout routing manner and extend to the bending area B12. For example, the plurality of data pinouts 251 may be alternately arranged at the first gate metal layer and the second gate metal layer. The plurality of driving lead lines may extend from the left and right frame regions B3 and B4 to the first routing region B11, may be electrically connected with the gate driving circuits within the left and right frame regions B3 and B4, and may be configured to provide control signals to the gate driving circuits, for example, the control signals may include a start signal, a clock signal, and the like. The plurality of touch outgoing lines 521 may extend from the left frame area B3 and the right frame area B4 to the first routing area B11, and may be located at a side of the plurality of display outgoing lines away from the substrate.

In some examples, as shown in fig. 1 and 4, the inflection region B12 is connected between the first and second routing regions B11 and B13, and may be configured such that the second routing region B13 is bent to the rear surface of the active area AA. The bending area B12 may be provided with a plurality of bending connection lines, for example, may include a plurality of data bending connection lines 252, a plurality of driving bending connection lines (not shown), a plurality of touch bending connection lines 522, a first power bending connection line (not shown), and a second power bending connection line (not shown). The first power bending connection line can be electrically connected with the first power frame line 411 in the first routing area B11, and the second power bending connection line can be electrically connected with the second power frame line 412 in the first routing area B11. The plurality of data bending connection lines 252 may be electrically connected to the plurality of data outgoing lines 251, the plurality of driving bending connection lines may be electrically connected to the plurality of driving outgoing lines, and the plurality of touch bending connection lines 522 may be electrically connected to the plurality of touch outgoing lines 521.

In some examples, as shown in fig. 1, the plurality of bending connection lines may all extend along the second direction D2, and the plurality of bending connection lines may be of a same-layer structure. For example, taking the film structure shown in fig. 3A to 3C as an example, a plurality of bending connection lines may be located in the second source-drain metal layer. For example, the plurality of touch bending connection lines 522 may be located at opposite sides of the plurality of data bending connection lines 252 in the first direction D1. However, the present embodiment is not limited thereto.

In some examples, as shown in fig. 1, the second routing area B13 may be provided with a plurality of patch cords, for example, may include a plurality of data patch cords 253 and a plurality of touch patch cords 523. The plurality of data patch lines 253 may be electrically connected to the plurality of data flex connection lines 252, for example, in a one-to-one correspondence. The touch patch cords 523 may be electrically connected to the touch bending connection lines 522, for example, in a one-to-one correspondence.

In some examples, the first frame region B1 may include at least one first signal access region B131 and at least one second signal access region B132. Fig. 1 illustrates a first signal access area B131 and a second signal access area B132 as examples. In other examples, the display panel may be a large-sized panel or a folded panel, and the display panel may include a plurality of first signal access regions B131 or a plurality of second signal access regions B132, the plurality of first signal access regions B131 may be sequentially arranged along the first direction D1, and the plurality of second signal access regions B132 may be sequentially arranged along the first direction D1. The first signal access area B131 may be located at a side of the second signal access area B132 near the active area AA. For example, the second signal access area B132 may be located at a side of the first signal access area B131 away from the inflection area B12 in the second direction D2.

In some examples, as shown in fig. 1 and 4, the first signal access region B131 may also be referred to as a driving chip setting region. The first signal access region B131 may be provided with a plurality of first contact pads, and the plurality of first contact pads may be configured to be in bonding connection with at least one driving chip. For example, the driving chip may be configured to generate data signals required for driving the sub-pixels. For example, the plurality of first contact pads in the first signal access region B131 may include a first set of first contact pads and a second set of first contact pads, and the second set of first contact pads may be located on a side of the first set of first contact pads away from the bending region B12. The first set of first contact pads may be connected to the plurality of data patch cords 253.

In some examples, as shown in fig. 1 and 4, the second signal access zone B132 may also be referred to as a circuit-bound zone. The second signal access area B132 may be provided with a plurality of second contact pads. The plurality of second contact pads may be arranged in a row along the first direction D1, for example. The plurality of second contact pads may be configured for bonded connection with at least one circuit board, such as a flexible circuit board (FPC, flexible Printed Circuit). For example, an external circuit board may be configured to generate a touch signal provided to the touch structure layer and to receive a touch sensing signal. The second group of first contact pads in the first signal access area B131 may be electrically connected to the plurality of second contact pads through the plurality of pin connection lines for signal transmission between the first signal access area B131 and the second signal access area B132.

In some examples, the second routing region B13 may further include a first circuit region located at a side of the first signal access region B131 near the inflection region B12, and the first circuit region may be provided with a plurality of test circuits (not shown). The test circuit may be configured to be electrically connected to the plurality of data outlet lines 251 through the plurality of data patch lines 253 and the plurality of data flex connection lines 252, and to provide test data signals to the plurality of data lines DL within the active area AA during a test phase. The first circuit region may further include a plurality of electrostatic discharge circuits to provide a path for electrostatic discharge. For example, the plurality of data bending connection lines 252 may be electrically connected to the test circuit after being connected through the plurality of data patch lines 253, and the plurality of data patch lines 253 may be located on a side of the plurality of data bending connection lines 252 close to the substrate, so as to facilitate routing connected to the test circuit. For example, the plurality of data patch lines 253 may be alternately arranged on the first gate metal layer and the second gate metal layer.

The structure in the second routing area B13 is illustrated in fig. 4. Two first signal access areas B131 are illustrated in fig. 4, and a plurality of data patch cords 253 in fig. 4 are illustrated in their entirety.

In some examples, as shown in fig. 4, the second routing area B13 may further be provided with a plurality of first power supply switching lines (e.g., two first power supply switching lines 413a and 413B) and a plurality of second power supply switching lines (e.g., three second power supply switching lines 414a, 414B and 414 c). The plurality of first power supply patch cords can be connected with the first power supply frame line 411 in the first wiring area B11 through a plurality of first power supply bending connecting lines of the bending area B12, and the plurality of second power supply patch cords can be connected with the second power supply frame line 412 in the first wiring area B11 through a plurality of second power supply bending connecting lines of the bending area B12.

In some examples, the second power supply patch cord 414a, the first power supply patch cord 413a, the second power supply patch cord 414c, the first power supply patch cord 413b, and the second power supply patch cord 414b are sequentially arranged along the first direction D1. The second power patch cords 414a and 414b may extend at least along the second direction D2. The first power patch cords 413a and 413b and the second power patch cord 414c may be substantially n-shaped. Taking the first power patch cord 413a as an example, the first power patch cord 413a may include a first main body portion extending along the first direction D1, and a first extension portion and a second extension portion extending along the second direction D2, where the first extension portion is connected to one end of the first main body portion, and the second extension portion is connected to the other end of the first main body portion. The first extension of the first power patch cord 413a is adjacent to the second power patch cord 414a, and the second extension is adjacent to the second power patch cord 414 c. The first and second extension portions of the first power patch cord 413a may extend to be connected with corresponding second contact pads within the second signal access region B132.

In some examples, the first power supply switching wires 413a and 413B and the second power supply switching wires 414a and 414B in the second routing area B13 may be of a dual-layer routing structure, for example, may include a routing layer having a same layer structure as the first source drain metal layer of the active area and a routing layer having a same layer structure as the second source drain metal layer, and the second power supply switching wire 414c may be of a three-layer routing structure, for example, may include a routing layer having a same layer structure as the first source drain metal layer of the active area, a routing layer having a same layer structure as the second source drain metal layer of the active area, and a routing layer having a same layer structure as the third source drain metal layer of the active area.

Fig. 5 is a schematic diagram of a partial routing of the region S1 in fig. 4. In some examples, as shown in fig. 4 and 5, the second routing region B13 may further be provided with a plurality of driving transmission lines 61, a plurality of first driving connection lines 621a and 621B, and a plurality of second driving connection lines 622a and 622B. The plurality of driving transmission lines 61 may be connected to the plurality of driving outgoing lines of the first routing area B11 through a plurality of driving bending connection lines of the bending area B12. The plurality of driving transmission lines 61 may include a plurality of first driving transmission lines 611a and 611b, and a plurality of second driving transmission lines 612a and 612b. The plurality of first driving transmission lines 611a and the plurality of second driving transmission lines 612a may be located at one side of the plurality of data patch lines 253 along the first direction D1, and the plurality of first driving transmission lines 611b and the plurality of second driving transmission lines 612b may be located at the other side of the plurality of data patch lines 253 along the first direction D1. The plurality of first driving transmission lines 611a may be connected with the plurality of second driving connection lines 622a through the plurality of first driving connection lines 621 a. The plurality of first driving transmission lines 611b may be connected with the plurality of second driving connection lines 622b through the plurality of first driving connection lines 621 b. For example, the plurality of first driving transmission lines 611a and the plurality of first driving connection lines 621a may be electrically connected in a one-to-one correspondence, and the plurality of first driving connection lines 621a and the plurality of second driving connection lines 622a may be electrically connected in a one-to-one correspondence.

In some examples, the plurality of first driving connection lines 621a may be located at a side of the first signal access region B131 near the inflection region B12, and the plurality of first driving connection lines 621B may be located at a side of the second first signal access region B131 near the inflection region B12. The plurality of second driving connection lines 622a and 622B may be located at the middle region of the two first signal access regions B131.

In some examples, the plurality of second contact pads of the second signal access area B132 may include two first group second contact pads 811a and 811B, two second group second contact pads 812a and 812B, two third group second contact pads 813a and 813B, two fourth group second contact pads 814a and 814B, four fifth group second contact pads 815a, 815B, 815c and 815d, and four sixth group second contact pads 816a, 816B, 816c and 816d. In the first direction D1, two third sets of second contact pads 813a and 813b may be located at the middle of two first sets of second contact pads 811a and 811b, second sets of second contact pads 812a and 812b may be located at both sides of two first sets of second contact pads 811a and 811b, fourth set of second contact pads 814a may be located at a side of second set of second contact pads 812a remote from first set of second contact pads 811a, and fourth set of second contact pads 814b may be located at a side of second set of second contact pads 812b remote from first set of second contact pads 811 b.

In some examples, the plurality of second contact pads within the first set of second contact pads 811a are configured to connect with the second set of first contact pads within the first signal access region B131, and the plurality of second contact pads within the first set of second contact pads 811B are configured to connect with the second set of first contact pads within the second first signal access region B131. The plurality of second contact pads within the second set of second contact pads 812a may be configured to connect with the plurality of second drive transmission lines 612a, and the plurality of second contact pads within the second set of second contact pads 812b may be configured to connect with the plurality of second drive transmission lines 612 b. The plurality of second contact pads within the third set of second contact pads 813a may be configured to be connected to the plurality of second driving connection lines 622a, and the plurality of second contact pads within the third set of second contact pads 813b may be configured to be connected to the plurality of second driving connection lines 622 b. The plurality of second contact pads within the fourth set of second contact pads 814a and 814b may be configured to connect with the plurality of touch patch cords 523. The plurality of second contact pads within the fifth group of second contact pads 815a and 815b may be configured to connect with the first power supply 413a, and the plurality of second contact pads within the fifth group of second contact pads 815c and 815d may be configured to connect with the first power supply 413 b. The plurality of second contact pads within the sixth set of second contact pads 816a may be configured to connect with the second power supply patch cord 414a, the plurality of second contact pads within the sixth set of second contact pads 816d may be configured to connect with the second power supply patch cord 414b, and the plurality of second contact pads within the sixth set of second contact pads 816b and 816c may be configured to connect with the second power supply patch cord 414 c.

In some examples, the first frame region B1 may have a first midline along the first direction D1, the first midline extending along the second direction D2, and the tracks within the second track region B13 may be arranged substantially symmetrically about the first midline.

In some examples, as shown in fig. 4 and 5, the plurality of second driving transmission lines 612a of the plurality of driving transmission lines 61 within the second routing area B13 may be connected to the second set of second contact pads 812a, the plurality of first driving transmission lines 611a may be connected to the third set of second contact pads 813a through the plurality of first driving connection lines 621a and the plurality of second driving connection lines 622a, and the second set of second contact pads 812a and the third set of second contact pads 813a may be located at both sides of the first set of first contact pads 811a along the first direction D1. The present example can satisfy the number of second contact pads required for driving the transmission line, for example, can support the requirement of folding the display panel, by arranging the second contact pads connected to the driving transmission line on both sides of the first group of second contact pads.

In some examples, as shown in fig. 5, the plurality of first driving transmission lines 611a and the plurality of second driving transmission lines 612a may be sequentially arranged along the first direction D1. For example, the plurality of first driving transmission lines 611a may be located at a side of the plurality of second driving transmission lines 612a near the first body portion of the first power supply switching line 413 a. In other examples, the plurality of first driving transmission lines 611a and the plurality of second driving transmission lines 612a may be alternately arranged along the first direction D1, or partially alternately arranged.

In some examples, as shown in fig. 5, the plurality of first and second driving transmission lines 611a and 612a may be located at a side of the first and second power transfer lines 413a and 414a near the substrate. For example, the plurality of first driving transmission lines 611a and the plurality of second driving transmission lines 612a may have the same layer structure as the first gate metal layer or the second gate metal layer in the active area. The plurality of first driving connection lines 621a may be located at a side of the first power supply connection line 413a remote from the substrate. The front projection of the first power patch cord 413a on the substrate and the front projection of the plurality of first driving connection lines 621a on the substrate may at least partially overlap. For example, the front projection of each of the first driving connection lines 621a on the substrate and the front projection of the first power supply connection line 413a on the substrate may partially overlap. For example, the plurality of first driving connection lines 621a may have a same layer structure as the third source drain metal layer in the active area, and the plurality of second driving connection lines 622a may have a same layer structure as the first source drain metal layer in the active area.

Fig. 6 is a schematic partial plan view of the region S1 in fig. 4. Fig. 7 is a schematic plan view of a portion of the region S2 in fig. 4. Fig. 8A is a schematic partial cross-sectional view along PP' in fig. 6. Fig. 8B is a schematic partial cross-sectional view along the QQ' direction in fig. 6.

In some examples, as shown in fig. 6 to 8B, the plurality of first driving connection lines 621a may extend at least in the first direction D1 and be sequentially arranged in the second direction D2 in a direction away from the bending region B12. There may be overlap between the front projection of the plurality of first driving connection lines 621a on the substrate and the front projection of the first power supply connection line 413a on the substrate. For example, the front projection of each of the first driving connection lines 621a on the substrate and the front projection of the first power supply connection line 413a on the substrate may partially overlap. The plurality of second driving link lines 622a may be located at a side of the plurality of first driving link lines 621a near the substrate.

In some examples, as shown in fig. 8A and 8B, the plurality of data patch lines of the second routing area B13 may include a plurality of first data patch lines 253a having a same layer structure as the first gate metal layer of the active area and a plurality of second data patch lines 253B having a same layer structure as the second gate metal layer of the active area. The first power patch cord 413a may include a sixth power trace layer 413-1 having a same layer structure as the first source drain metal layer of the active area, and a seventh power trace layer 413-2 having a same layer structure as the second source drain metal layer of the active area. The seventh power trace layer 413-2 may be electrically connected to the sixth power trace layer 413-1 over a large area by a groove formed in the first planarization layer 105. The plurality of first driving connection lines 621a may have the same layer structure as the third source drain metal layer of the active area. The plurality of second driving connection lines 622a may be, for example, in the same layer structure as the first source drain metal layer of the active area. The first power patch cord 413a of this example may be disposed between the plurality of first driving connection lines 621a and the plurality of data patch cords 253 as a shielding layer, and signal crosstalk may be prevented from being generated between the first driving connection lines 621a and the data patch cords 253.

In some examples, taking the film structure shown in fig. 3A and 3B as an example, the touch inorganic insulating layer of the first frame area B1 may include a touch barrier layer and a touch interlayer insulating layer that are stacked, and taking the film structure shown in fig. 3C as an example, the touch inorganic insulating layer of the first frame area B1 may include a touch barrier layer. The orthographic projection of the touch inorganic insulating layer and the bending region B12 on the substrate base plate can not overlap. The touch inorganic insulating layer includes a first inorganic boundary 505 located in the second routing area B13, and an edge 5051 of the first inorganic boundary 505 near the bending area B12 may be a non-linear edge.

In some examples, to ensure the bending performance of the bending region B12, the bending region B12 is not provided with a touch inorganic insulating layer. The touch inorganic insulating layer has a first inorganic boundary 505 near the bending region B12 in the second routing region B13, and an edge 5051 of the first inorganic boundary 505 faces the bending region B12. Since the first inorganic boundary portion 505 is in direct contact with the display organic insulating layer (e.g., the third planarization layer 107), and is not in direct contact with the display inorganic insulating layer to form an inorganic enclosed space, there is a risk that moisture intrudes along the edge position of the first inorganic boundary portion 505. The plurality of first driving connection lines are configured to transmit a plurality of control signals provided to the gate driving circuit, a voltage difference exists between adjacent ones of the plurality of first driving connection lines, and the first power supply patch cord is configured to transmit a constant first power supply signal (e.g., a constant high voltage signal), and a voltage difference exists between the plurality of first driving connection lines and the first power supply patch cord. Under the acceleration of the voltage difference between high and low, the area is easy to quickly generate the wiring corrosion condition, so that abnormal display is caused. According to the touch control inorganic insulating layer, the relative position relation between the touch control inorganic insulating layer and the plurality of first driving connecting wires and the first power supply switching wire is adjusted, so that the corrosion risk of vapor invasion to the first driving connecting wires is improved.

In some examples, as shown in fig. 6 to 8B, the edge 5051 of the first inorganic boundary portion 505 of the touch inorganic insulating layer may be located at a side of the plurality of first driving connection lines 621a away from the bending region B12. The overlapping area of the orthographic projection of the first inorganic boundary portion 505 on the substrate and the orthographic projection of the first power patch cord 413a and the plurality of first driving connection lines 621a on the substrate may not overlap. In other words, the first inorganic boundary 505 does not cover the overlapping area of the first power patch cord 413a and the plurality of first driving connection lines 621a in the orthographic projection of the substrate.

In some examples, as shown in fig. 6 and 7, the front projection of the first inorganic boundary portion 505 on the substrate and the front projections of the plurality of first driving connection lines 621a on the substrate may not overlap. The front projection of the first inorganic boundary 505 on the substrate and the front projection of the first power patch cord 413a on the substrate may partially overlap.

In some examples, as shown in fig. 8A, along the second direction D2, an edge 5051 of the first inorganic boundary portion 505 of the touch inorganic insulating layer, and the first power patch cord 413a and the plurality of first driving connection lines 621a may have a first distance L1 between overlapping areas of the orthographic projection of the substrate. As shown in fig. 8B, along the first direction D1, the edge 5051 of the first inorganic boundary 505 of the touch inorganic insulating layer, and the overlapping area of the first power patch cord 413a and the plurality of first driving patch cords 621a in the orthographic projection of the substrate may have a second distance L2. The first distance L1 and the second distance L2 may be greater than 20 microns. For example, the first distance L1 and the second distance L2 may be the same. As another example, the first distance L1 may be greater than the second distance L2.

In some examples, as shown in fig. 8A and 8B, the second routing area B13 may be provided with a fourth flat layer (i.e. the aforementioned auxiliary organic insulating layer) 108, and the fourth flat layer 108 may be located on a side of the third flat layer 107 away from the substrate 10, and on a side of the first inorganic boundary 505 of the touch inorganic insulating layer close to the substrate 10. The orthographic projection of the fourth flat layer 108 on the substrate may cover the orthographic projection of the plurality of first driving connection lines 621a on the substrate. The front projection of the fourth flat layer 108 on the substrate and the front projection of the first power patch cord 414a on the substrate may partially overlap. For example, the fourth planarization layer 108 may have the same layer structure as the pixel defining layer of the active region, or may be an organic insulating layer prepared by a new step between the third planarization layer and the pixel defining layer. In the etching process of the touch inorganic insulating layer in the second routing area B13, there is a situation that the organic insulating layer (for example, the third planarization layer 107) below the etched portion, and by setting the fourth planarization layer 108, the present example can ensure the routing coverage of the third source drain metal layer with the same layer structure.

In some examples, as shown in fig. 8A and 8B, the orthographic projection of the fourth planar layer 108 on the substrate and the orthographic projection of the first inorganic boundary portion 505 on the substrate may partially overlap. There is a partial overlap between the edge of the fourth flat layer 108 and the edge 5051 of the first inorganic boundary portion 505 of the touch inorganic insulating layer. The edge 5051 of the first inorganic boundary portion 505 may encapsulate the edge of the fourth planar layer 108 adjacent the first inorganic boundary portion 505.

According to the touch control inorganic insulating layer, the touch control inorganic insulating layer above the overlapping area of the first power supply switching wire and the plurality of first driving connecting wires is removed, and the situation that water vapor invades through the edge of the first inorganic boundary part of the touch control inorganic insulating layer to cause wiring corrosion can be improved.

Fig. 8C is another partial cross-sectional view along PP' in fig. 6. In some examples, as shown in fig. 8C, the second routing region B13 may not be provided with the fourth planarization layer 108. The thickness of the third flat layer 107 in the second routing area B13 may be greater than or equal to the thickness of the third flat layer 107 in the effective area, so as to ensure that the routing in the second routing area B13 and the third source drain metal layer are covered. The rest of the description of the display panel of this embodiment can refer to the description of the foregoing embodiments, so that the description thereof is omitted here.

In other examples, the plurality of display metal layers of the display structure layer of the active region may include a first source drain metal layer and a second source drain metal layer. The first power supply patch cord and the first power supply metal layer can be of the same-layer structure, and the plurality of first driving connecting lines and the second source drain metal layer can be of the same-layer structure. In other examples, the plurality of display metal layers of the display structure of the active area may include a first source drain metal layer, a second source drain metal layer, a third source drain metal layer, and a fourth source drain metal layer that are sequentially disposed, where the plurality of first driving connection lines may be in a same layer structure with the fourth source drain metal layer, and the first power supply patch cord may be located on a side of the plurality of first driving connection lines, which is close to the substrate. The positional relationship between the first inorganic boundary portion of the touch inorganic insulating layer and the first power supply patch cord and the plurality of first driving connection lines may be as described above.

Fig. 9 is a partial plan view of fig. 5. Fig. 10A is a schematic partial cross-sectional view along RR' in fig. 9. Fig. 10B is a schematic partial cross-sectional view along UU' in fig. 9.

In some examples, taking the film layer structure shown in fig. 3A and 3B as an example, when the touch interlayer insulating layer is an organic insulating layer and the touch patch cords of the second routing area B13 are arranged on the first touch conductive layer and the second touch conductive layer, the touch patch cords are easily corroded due to water vapor and residual corrosion factors in the touch interlayer insulating layer. Therefore, as shown in fig. 9 to 10B, the plurality of touch patch cords 523 may have the same layer structure as the third source/drain metal layer in the active area. In other examples, when the display structure layer includes a plurality of source-drain metal layers, the plurality of touch patch cords may have the same layer structure as the source-drain metal layer closest to the touch structure layer. For example, the display structure layer includes a first source drain metal layer and a second source drain metal layer, and the plurality of touch patch cords and the second source drain metal layer may be in the same layer structure.

In some examples, the second power patch cord 414a may be located on a side of the plurality of touch patch cords 523 that is close to the substrate. For example, the second power patch cord 414a may include an eighth power trace layer 414-1 having a same layer structure as the first source drain metal layer of the active area and a ninth power trace layer 414-2 having a same layer structure as the second source drain metal layer of the active area. The ninth power trace layer 414-2 may be electrically connected to the eighth power trace layer 414-1 over a large area by a groove formed in the first planarization layer 105. The second power supply patch cord 414a of this example may serve as a shielding layer to avoid signal crosstalk between the plurality of touch patch cords 523 and the wiring (including, for example, the plurality of driving transmission lines 61 shown in fig. 5) having the same layer structure as the second gate metal layer and the first gate metal layer.

In some examples, the plurality of touch patch cords 523 may be configured to transmit a positive signal, e.g., in a voltage range of 1.5V to 3.5V, and the second power patch cord 414a is configured to transmit a negative signal. A voltage difference exists between the second power patch cord 414a and the plurality of touch patch cords 523. The corrosion risk of vapor intrusion to the plurality of touch patch cords is improved by adjusting the relative positional relationship of the touch inorganic insulating layer, the plurality of touch patch cords and the second power patch cord.

In some examples, in the interface area of the bending area B12 and the second routing area B13, the plurality of touch bending connection lines 522 may implement electrical connection with the plurality of touch patch lines 523 through a plurality of first touch connection electrodes (including, for example, a plurality of first touch connection electrodes 524a and 524B), a plurality of second touch connection electrodes 525, and a plurality of third touch connection electrodes 526a and 526B. The plurality of first touch connection electrodes 524a may have a same layer structure as the first gate metal layer of the active area, the plurality of first touch connection electrodes 524b may have a same layer structure as the second gate metal layer of the active area, the plurality of second touch connection electrodes 525 may have a same layer structure as the second source drain metal layer of the active area, and the plurality of third touch connection electrodes 526a and 526b may have a same layer structure as the first source drain metal layer of the active area.

In some examples, as shown in fig. 10A, one touch bending connection line 522 may be connected to one end of a first touch connection electrode 524a (or a first touch connection electrode 524 b) through one third touch connection electrode 526a, and the other end of the first touch connection electrode 524a (or the first touch connection electrode 524 b) may be connected to a second touch connection electrode 525 through one third touch connection electrode 526b, and the second touch connection electrode 525 may be connected to one touch patch line 523. In other examples, the third touch connection electrode may be omitted, and the first touch connection electrode may be directly connected to the second touch connection electrode and the touch bending connection line.

In some examples, in the first direction D1, a crack detection patch cord (including crack detection patch cords 601 and 602, for example) may be disposed on a side of the plurality of touch patch cords 523 near the edge of the display panel. The crack detection patch cords 601 and 602 may be configured to detect whether a crack exists in the touch structure layer. The crack detection patch cord 601 may be, for example, in a same layer structure as the first gate metal layer, and the crack detection patch cord 602 may be, for example, in a same layer structure as the second gate metal layer.

In some examples, as shown in fig. 9 to 10B, the front projection of the first inorganic boundary portion 505 of the touch inorganic insulating layer on the substrate may not overlap with the overlapping area of the front projections of the second power patch cord 414a and the plurality of touch patch cords 523 on the substrate. In other words, the first inorganic boundary 505 does not cover the overlapping area of the orthographic projection of the second power supply patch cord 414a and the plurality of touch patch cords 523 on the substrate. For example, the front projection of the first inorganic boundary 505 on the substrate and the front projection of the plurality of touch pads 523 on the substrate may not overlap. The front projection of the first inorganic boundary 505 on the substrate and the front projection of the second power supply patch cord 414a on the substrate may partially overlap. In other examples, the front projection of the first inorganic boundary 505 on the substrate may not overlap with the front projection of the second power supply patch cord 414a and the plurality of touch patch cords 523 on the substrate, and may partially overlap with the front projection of the second power supply patch cord 414a on the substrate.

In some examples, as shown in fig. 10B, along the first direction D1, an edge 5051 of the first inorganic boundary portion 505 of the touch inorganic insulating layer, and the second power supply patch cord 414a and the plurality of touch patch cords 523 may have a third distance L3 between overlapping areas of the orthographic projection of the substrate. The third distance L3 may be greater than 20 microns. For example, the third distance L3 may be the same as the aforementioned first distance L1.

According to the touch control inorganic insulating layer, the touch control inorganic insulating layer above the overlapping area of the second power supply switching wire and the plurality of touch control switching wires is removed, and the situation that water vapor invades through the edge of the first inorganic boundary part of the touch control inorganic insulating layer to cause wiring corrosion can be improved. The rest of the description of the display panel of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

In other examples, except for the position close to the bending region, the first inorganic boundary portion of the touch inorganic insulating layer in the first frame region does not contact with the display inorganic insulating layer, and the positions of the plurality of frame signal lines with voltage differences can be all adopted in the mode of the embodiment to etch the touch inorganic insulating layer, so that the position relationship between the first inorganic boundary portion of the touch inorganic insulating layer and the corresponding frame signal line is adjusted to improve the routing corrosion condition.

Fig. 11 is a schematic diagram of a display device according to at least one embodiment of the disclosure. In some examples, as shown in fig. 11, the display device 91 includes a display panel 910. The display panel 910 may be an OLED display panel. The display device 91 may be any product or component with display and touch control functions, such as an OLED display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator. However, the present embodiment is not limited thereto.

In the description of the present specification, a description referring to the terms "one embodiment," "some embodiments," "examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims

1. A display panel, comprising:

The substrate comprises an effective area and a first frame area positioned at one side of the effective area;

the display structure layer is positioned on the substrate and comprises a plurality of display organic insulating layers and a plurality of display inorganic insulating layers, and the plurality of display organic insulating layers are positioned on one side of the plurality of display inorganic insulating layers away from the substrate;

the packaging structure layer is positioned at one side of the display structure layer away from the substrate base plate;

The touch control structure layer is positioned on one side of the packaging structure layer far away from the substrate base plate and comprises a touch control inorganic insulating layer, wherein the touch control inorganic insulating layer comprises a first inorganic boundary part positioned in the first frame area, and the first inorganic boundary part is in direct contact with at least one display organic insulating layer in the plurality of display organic insulating layers and is not in direct contact with the plurality of display inorganic insulating layers;

the touch control device comprises a substrate, a plurality of display inorganic insulating layers, a plurality of frame signal lines, a touch control inorganic insulating layer, a plurality of display inorganic insulating layers, a plurality of touch control inorganic insulating layers and a plurality of display inorganic insulating layers, wherein the plurality of frame signal lines are positioned in the first frame region, the plurality of frame signal lines are positioned at one side of the plurality of display inorganic insulating layers far away from the substrate and at one side of the touch control inorganic insulating layers close to the substrate, and voltage differences exist between at least two adjacent frame signal lines in the plurality of frame signal lines;

the display panel satisfies at least one of:

The minimum distance between the orthographic projection of the first inorganic boundary part of the touch inorganic insulating layer on the substrate and the overlapping area of orthographic projections of the at least two frame signal lines positioned on different conducting layers on the substrate is larger than 0;

The minimum distance between the orthographic projection of the first inorganic boundary part of the touch inorganic insulating layer on the substrate and the orthographic projection of the at least two frame signal lines of the same conducting layer closest to the touch inorganic insulating layer on the substrate is larger than 0.

2. The display panel of claim 1, wherein a minimum distance between an orthographic projection of the first inorganic boundary portion of the touch inorganic insulating layer on the substrate and an overlapping region of orthographic projections of the at least two bezel signal lines on the substrate is greater than 20 micrometers.

3. The display panel of claim 1, wherein the plurality of frame signal lines comprises at least one first frame signal line and a plurality of second frame signal lines, the plurality of second frame signal lines being on a same conductive layer, the first frame signal line and the plurality of second frame signal lines being on different conductive layers;

The first frame signal line is configured to transmit a constant power signal, and a front projection of the first frame signal line on the substrate overlaps at least a portion of a front projection of at least one of the plurality of second frame signal lines on the substrate.

4. The display panel of claim 3, wherein the display structure layer further comprises a plurality of display metal layers, and the plurality of second frame signal lines and the display metal layer closest to the touch structure layer are of a same layer structure.

5. The display panel of claim 4, wherein the plurality of display metal layers comprises a first source drain metal layer, a second source drain metal layer and a third source drain metal layer on a side of the plurality of display inorganic insulating layers away from the substrate, the plurality of second frame signal lines and the third source drain metal layer are of a same layer structure, and the first frame signal lines are on a side of the plurality of second frame signal lines close to the substrate.

6. The display panel according to any one of claims 3 to 5, wherein the first frame region includes a first wiring region, a bending region, and a second wiring region sequentially disposed in a direction away from the effective region;

the orthographic projection of the touch inorganic insulating layer on the substrate base plate is not overlapped with the bending area;

the first inorganic boundary part of the touch inorganic insulating layer is positioned in the second wiring area and is adjacent to the bending area.

7. The display panel of claim 6, wherein the display structure layer comprises a plurality of sub-pixels located in the active area and a plurality of data lines connected to the plurality of sub-pixels;

The substrate base plate also comprises a second frame area positioned on the other sides of the effective area, wherein the second frame area is provided with a grid driving circuit, and the grid driving circuit is configured to provide grid control signals for the plurality of sub-pixels;

The first frame area further comprises at least one first signal access area which is positioned at one side of the second wiring area far away from the bending area, wherein the first signal access area is provided with a plurality of first contact pads;

The second wiring area is provided with at least one first power supply switching line, a plurality of data switching lines, a plurality of first driving transmission lines, a plurality of first driving connecting lines and a plurality of second driving connecting lines, wherein the first power supply switching lines are configured to transmit constant first power supply signals;

The plurality of data lines are connected with a part of the first contact pads of the first signal access area through the plurality of data patch cords; the first driving transmission lines are connected with the second driving connection lines through the first driving connection lines and configured to transmit control signals provided for the grid driving circuit, and the first driving connection lines are positioned at one side of the first signal access area close to the bending area;

the first frame signal line comprises the first power supply switching line, and the plurality of second frame signal lines comprise the plurality of first driving connecting lines.

8. The display panel of claim 7, wherein the plurality of first drive connection lines are located on a side of the plurality of first drive transmission lines and the plurality of second drive connection lines remote from the substrate;

the first power supply switching wires are located on one side, far away from the substrate, of the plurality of data switching wires, and are located on one side, close to the substrate, of the plurality of first driving connecting wires.

9. The display panel of claim 7, wherein the first frame region further comprises a second signal access region on a side of the first signal access region remote from the inflection region, the second signal access region being provided with a plurality of second contact pads;

The second wiring area is also provided with a plurality of second drive transmission lines, and the second drive transmission lines and the first drive transmission lines are positioned on the same side of the first signal access area;

The plurality of second contact pads includes at least one first set of second contact pads, at least one second set of second contact pads, and at least one third set of second contact pads;

The first group of second contact pads are connected with a part of first contact pads in the first signal access area;

the second group of second contact pads are connected with the plurality of second driving transmission lines;

the third group of second contact pads are connected with the plurality of second driving connecting wires;

The second set of second contact pads and the third set of second contact pads are located on both sides of the first set of second contact pads.

10. The display panel of claim 6, wherein the second routing area is provided with at least one second power patch cord configured to transmit a constant second power signal, and a plurality of touch patch cords;

the first frame signal line comprises the second power supply switching line, and the plurality of second frame signal lines comprise the plurality of touch switching lines.

11. The display panel according to claim 1, further comprising an auxiliary organic insulating layer in the first frame region, the auxiliary organic insulating layer being located on a side of the plurality of display organic insulating layers away from the substrate and on a side of the touch inorganic insulating layer closer to the substrate;

and the orthographic projection of the auxiliary organic insulating layer on the substrate covers the orthographic projection of the at least two frame signal lines on the substrate.

12. The display panel of claim 11, wherein a front projection of the first inorganic boundary portion of the touch inorganic insulating layer at the substrate overlaps a front projection portion of the auxiliary organic insulating layer at the substrate.

13. The display panel of claim 1, wherein the touch structure layer comprises a touch barrier layer, a first touch conductive layer, a touch interlayer insulating layer, a second touch conductive layer, and a touch protective layer sequentially disposed on the packaging structure layer, and wherein the touch inorganic insulating layer comprises the touch barrier layer or the touch barrier layer and the touch interlayer insulating layer.

14. A display device comprising the display panel according to any one of claims 1 to 13.