CN119208388A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN119208388A CN119208388A CN202411238806.4A CN202411238806A CN119208388A CN 119208388 A CN119208388 A CN 119208388A CN 202411238806 A CN202411238806 A CN 202411238806A CN 119208388 A CN119208388 A CN 119208388A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims description 38
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 205
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本公开涉及一种半导体器件及其制备方法，涉及集成电路技术领域，其中，源极位于衬底上；介电芯位于源极背离衬底的一侧；沟道层位于介电芯、源极之间，且覆盖介电芯的底面及侧壁，沟道层的顶面高于介电芯的顶面并形成位于介电芯上方的凹槽；导电插塞至少部分位于凹槽内，导电插塞的底面低于沟道层的顶面；漏极位于沟道层与导电插塞之间，漏极的侧壁被部分导电插塞覆盖，至少能够在确保半导体器件体积不增加的情况下，提高半导体器件的性能及可靠性。
The present disclosure relates to a semiconductor device and a preparation method thereof, and relates to the technical field of integrated circuits, wherein a source electrode is located on a substrate; a dielectric core is located on a side of the source electrode facing away from the substrate; a channel layer is located between the dielectric core and the source electrode, and covers the bottom surface and side walls of the dielectric core, the top surface of the channel layer is higher than the top surface of the dielectric core and forms a groove located above the dielectric core; a conductive plug is at least partially located in the groove, and the bottom surface of the conductive plug is lower than the top surface of the channel layer; a drain electrode is located between the channel layer and the conductive plug, and the side walls of the drain electrode are partially covered by the conductive plug, so that the performance and reliability of the semiconductor device can be improved while at least ensuring that the volume of the semiconductor device does not increase.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technology, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
With the rapid development of semiconductor technology, the demands of the market for integrated circuits for integration level, performance and reliability are increasing. The market is continually increasing for the number of integrated transistors per unit area, requiring smaller transistor structures and more compact design layouts, which presents challenges for improving the performance and reliability of semiconductor devices.
Therefore, how to improve the performance and reliability of the semiconductor device without increasing the structure volume of the transistor is one of the technical problems to be solved.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a semiconductor device and a method for manufacturing the same that can improve the performance and reliability of the semiconductor device, at least while ensuring that the semiconductor device does not increase in size.
According to various embodiments of the present disclosure, a first aspect of the present disclosure provides a semiconductor device including a substrate, a source electrode, a dielectric core, a channel layer, a conductive plug and a drain electrode, the source electrode is located on the substrate, the dielectric core is located on a side of the source electrode facing away from the substrate, the channel layer is located between the dielectric core and the source electrode and covers a bottom surface and a side wall of the dielectric core, a top surface of the channel layer is higher than a top surface of the dielectric core and forms a groove located above the dielectric core, the conductive plug is located at least partially within the groove, a bottom surface of the conductive plug is lower than a top surface of the channel layer, the drain electrode is located between the channel layer and the conductive plug, and a side wall of the drain electrode is covered by a portion of the conductive plug.
According to the semiconductor device in the embodiment, the source electrode is arranged on the substrate, the dielectric core is arranged on one side of the source electrode, which is away from the substrate, the channel layer is arranged between the dielectric core and the source electrode and covers the bottom surface and the side wall of the dielectric core to form the U-shaped channel layer, the top surface of the channel layer is higher than the top surface of the dielectric core and forms the groove above the dielectric core, so that the conductive plug is arranged at least partially in the groove, the bottom surface of the conductive plug is lower than the top surface of the channel layer, and the drain electrode is arranged between the channel layer and the conductive plug, so that the side wall of the drain electrode is covered by a part of the conductive plug, the contact area of the drain electrode and the conductive plug is increased under the condition that the volume of the semiconductor device is not increased, the volume of the conductive plug is relatively increased, the connection impedance of the conductive plug and the drain electrode is reduced, and the performance and the reliability of the semiconductor device are improved.
In some embodiments, the conductive plug has a longitudinal section of a T shape, and the bottom surface of the conductive plug contacts the top surface of the dielectric core, so that the conductive plug is partially positioned in a groove formed on the top surface of the channel layer and positioned above the dielectric core, and the volume of the conductive plug is relatively increased without increasing the volume of the semiconductor device, so that a drain electrode covered by a part of the conductive plug is formed on the side wall of the groove, and the contact area between the conductive plug and the drain electrode is further increased.
In some embodiments, the conductive plug further comprises a first portion positioned in the groove and a second portion positioned above the first portion, the semiconductor device further comprises an interconnection column positioned on the top surface of the second portion, and a vertical center line of the second portion is between the vertical center line of the first portion and the vertical center line of the interconnection column, so that the specific position of the interconnection column on the conductive plug can be conveniently set according to the actual requirement for preparing the integrated circuit, the requirement for the integration level of the integrated circuit is met, and the complexity and cost of the preparation process are reduced.
In some embodiments, the thicknesses of the drains on both sides of the conductive plugs are equal, so that the dimensions and performance of the drains on both sides of the conductive plugs are kept as uniform as possible, thereby improving the performance and reliability of the semiconductor device.
In some embodiments, the bottom surface of the conductive plug is lower than the bottom surface of the drain and extends into the dielectric core, so that the volume of the conductive plug is further increased without increasing the volume of the semiconductor device, and the connection impedance between the conductive plug and the drain is reduced.
In some embodiments, the semiconductor device further comprises a gate dielectric layer and a gate conductive layer, wherein the gate conductive layer is positioned on the outer side wall of the channel layer, the gate dielectric layer is positioned between the gate conductive layer and the channel layer, and the top surface of the gate dielectric layer is higher than the bottom surface of the conductive plug.
In some embodiments, a second aspect of the present disclosure provides a semiconductor device fabrication method comprising:
providing a substrate, wherein the substrate comprises a source electrode;
forming an intermediate layer on one side of the source electrode, which is away from the substrate, wherein the intermediate layer comprises a groove exposing part of the source electrode;
forming a channel layer covering the sidewalls of the trench and the exposed source electrode;
Forming a dielectric core in the groove, wherein the top surface of the channel layer is higher than the top surface of the dielectric core and a groove positioned above the dielectric core is formed;
forming a drain electrode on the side wall of the groove;
Forming a conductive plug at least partially in the groove, wherein the bottom surface of the conductive plug is lower than the top surface of the channel layer, and the side wall of the drain electrode is covered by part of the conductive plug.
In some embodiments, forming a drain on a sidewall of the recess includes:
and forming a drain electrode covering the side wall of the groove and the top surface of the dielectric core.
In some embodiments, forming a drain on a sidewall of the recess includes:
forming a drain electrode material layer which covers the side wall of the groove and the top surface of the dielectric core along with the shape;
At least the drain material layer on the top surface of the dielectric core is removed, and the drain material layer remaining on the sidewalls of the recess is used to form the drain.
In some embodiments, the over etching forms a recess towards the dielectric core during the removal of the drain material layer on the top surface of the dielectric core, the conductive plug is partially positioned in the recess to further increase the volume of the conductive plug without increasing the volume of the semiconductor device, thereby reducing the connection resistance between the conductive plug and the drain, and in the actual process, the over etching forms a recess towards the dielectric core during the removal of the drain material layer on the top surface of the dielectric core, thereby ensuring that the drain material layer on the top surface of the dielectric core is completely removed, and the drains positioned on both sides of the conductive plug are isolated.
In some embodiments, forming a conductive plug at least partially within a recess includes:
Forming a barrier layer which covers the top surface of the dielectric core and the drain electrode;
and forming a conductive layer filling the groove, wherein the barrier layer and the conductive layer are used for jointly forming a conductive plug.
In the above embodiment, after the barrier layer covering the top surface of the dielectric core and the drain electrode is formed, the conductive layer filling the recess is formed, so that the formation of a current leakage channel due to the entry of metal ions between the conductive layers into the dielectric core is avoided, thereby improving the performance and reliability of the semiconductor device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the disclosure;
Fig. 2 is a schematic view showing a longitudinal section structure of a semiconductor structure obtained in step S20 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 3 is a schematic view showing a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a gate conductive portion in step S40 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
Fig. 4 is a schematic view showing a longitudinal cross-sectional structure of a semiconductor structure obtained after forming an intermediate layer and an isolation layer in step S40 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 5 is a schematic view showing a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a gate conductive layer in step S40 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
Fig. 6 is a schematic view showing a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a gate dielectric layer in step S40 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
Fig. 7 is a schematic view showing a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a trench in step S40 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
Fig. 8 is a schematic view showing a longitudinal cross-sectional structure of a semiconductor structure obtained after forming an initial channel layer and a dielectric core in step S80 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 9 is a schematic view showing a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a drain material layer in step S100 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
Fig. 10 is a schematic view showing a longitudinal cross-sectional structure of a semiconductor structure obtained after forming a drain in step S100 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 11 is a schematic view showing a longitudinal section structure of a semiconductor structure obtained after forming a conductive plug in step S110 in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
Fig. 12 is a schematic view showing a longitudinal section structure of a semiconductor structure after forming an isolation structure in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 13 is a schematic view showing a longitudinal section structure of a semiconductor structure obtained after forming an interconnection pillar in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 14a is a schematic view showing a longitudinal sectional structure of a semiconductor device according to an embodiment of the present disclosure;
fig. 14b is a schematic view showing a longitudinal sectional structure of a semiconductor device provided in another embodiment of the present disclosure;
fig. 15 is a schematic view showing a longitudinal sectional structure of a semiconductor device provided in still another embodiment of the present disclosure;
fig. 16 is a schematic view showing a longitudinal sectional structure of a semiconductor device provided in still another embodiment of the present disclosure.
Reference numerals illustrate:
100. Substrate, 1, first metal layer, 2, first barrier layer, 1211, gate conductive material layer, 10, source, 1000, stack, 20, dielectric core, 31, initial channel layer, 30, channel layer, 23, recess, 231, recess, 40, conductive plug, 41, first portion, 42, second portion, 401, barrier layer, 402, conductive layer, 403, isolation recess, 101, initial trench, 11, trench, 61, gate dielectric layer, 62, gate conductive layer, 51, drain material layer, 50, drain, 60, gate, 80, interlayer dielectric layer, 110, isolation structure, 111, first dielectric layer, 112, second dielectric layer, 90, interconnect post, 12, intermediate layer, 13, isolation layer, 121, gate conductive portion, 122, isolation portion.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section, for example, a first doping type could be termed a second doping type, and, similarly, a second doping type could be termed a first doping type, a doping type different from the second doping type, such as, for example, the first doping type could be P-type and the second doping type could be N-type, or the first doping type could be N-type and the second doping type could be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Referring to fig. 1, in some embodiments, a method for manufacturing a semiconductor device is provided, including steps S20 to S110, in which:
Step S20, providing a substrate, wherein the substrate comprises a source electrode;
step S40, forming an intermediate layer on one side of the source electrode, which is away from the substrate, wherein the intermediate layer comprises a groove exposing part of the source electrode;
Step S60, forming a channel layer covering the side wall of the groove and the exposed source electrode;
Step S80, forming a dielectric core in the groove, wherein the top surface of the channel layer is higher than the top surface of the dielectric core and a groove positioned above the dielectric core is formed;
Step S100, forming a drain electrode on the side wall of the groove;
and S110, forming a conductive plug at least partially positioned in the groove, wherein the bottom surface of the conductive plug is lower than the top surface of the channel layer, and the side wall of the drain electrode is covered by part of the conductive plug.
In some embodiments, referring to fig. 2, the material of the substrate 100 provided in step S20 may include, but is not limited to, semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 100 is a semiconductor structure that provides mechanical support and electrical properties for fabricating a semiconductor device, and the substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a III/V semiconductor substrate or a II/VI semiconductor substrate. Those skilled in the art may select the type of substrate 100 according to the type of transistor formed on the substrate 100, and thus the type of substrate 100 should not limit the scope of the present disclosure.
As an example, referring to fig. 2, the first metal layer 1, the first barrier layer 2, the source electrode 10, the interlayer dielectric layer 80, and the gate conductive material layer 1211 are sequentially stacked on the substrate 100 in a direction away from the substrate 100, for example, the first metal layer 1, the first barrier layer 2, the source electrode 10, the interlayer dielectric layer 80, and the gate conductive material layer 1211 may be sequentially formed by using a chemical vapor deposition or physical vapor deposition (Physical vapor deposition, PVD) process, and the like, and the chemical vapor deposition process may include, but is not limited to, one or more of an Atmospheric Pressure Chemical Vapor Deposition (APCVD), a Low pressure chemical vapor deposition (Low-pressure CVD), a Plasma enhanced chemical vapor deposition (Plasma-ENHANCED CVD, PECVD), and the like, for example, the Low pressure chemical vapor deposition may have good step coverage, and the Low pressure chemical vapor deposition may be used to increase a deposition rate and an output and reduce a process cost, and the Low pressure chemical vapor deposition may not require an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process, and may reduce a carrier gas pollution.
As an example, with continued reference to fig. 2, the material of the first metal layer 1 may include, but is not limited to, at least one of titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper, and the like. The material of the first barrier layer 2 may include, but is not limited to, at least one of a titanium nitride layer, a cobalt layer, a platinum layer, a titanium tungsten layer, and the like. The material of the source electrode 10 may include, but is not limited to, at least one of a semiconductor material, a metal silicide, and the like. The material of interlayer dielectric layer 80 may include, but is not limited to, at least one of silicon dioxide, silicon nitride, silicon oxynitride, amorphous carbon, etc. The material of the gate conductive material layer 1211 may include, but is not limited to, at least one of indium tin oxide, copper, tungsten, aluminum, copper alloy, titanium nitride, a nitride button, tantalum nitride, and the like.
In some embodiments, referring to FIG. 3, forming the intermediate layer 12 in step S40 may include patterning the gate conductive material layer 1211 to obtain a plurality of gate conductive portions 121 spaced apart along the OX direction. The patterning may include a Self-aligned double patterning (Self-Aligned Double Patterning, SADP) process or a Self-aligned quadruple patterning (Self-Aligned Quadruple Patterning, SAQP) process, among others.
In some embodiments, referring to fig. 4, forming the intermediate layer 12 in step S40 may include forming spacers 122 in gaps between adjacent gate conductive portions 121 along the OX direction, where the gate conductive portions 121 and the spacers 122 are alternately arranged in sequence along the OX direction to form the intermediate layer 12. For example, the spacer 122 between the gate conductive portions 121 adjacent in the OX direction may be formed using a deposition process or a spin-on glass (Spin on Glass Coating, SOG) process. The material of the isolation portion 122 may include, but is not limited to, at least one of silicon oxide (SiO 2), silicon nitride (Si 3N4), silicon oxynitride (SiON), or the like.
In some embodiments, referring still to fig. 4, after forming the spacers 122, a deposition process may be used to form the isolation layer 13 overlying the intermediate layer 12. The material of the isolation layer 13 may include, but is not limited to, at least one of silicon oxide (SiO 2), silicon nitride (Si 3N4), silicon oxynitride (SiON), or the like.
In some embodiments, referring to fig. 5, forming the intermediate layer 12 in step S40 may include forming a plurality of initial trenches 101 penetrating the isolation layer 13 and the plurality of gate conductive portions 121 in a direction perpendicular to the substrate 100, for example, the OY direction, the remaining gate conductive portions 121 constituting gate conductive layers 62 arranged at intervals in the OX direction, the initial trenches 101 being located between the gate conductive layers 62 adjacent in the OX direction. For example, a patterned photoresist layer (not shown) may be formed on the top surface of the isolation layer 13, wherein the patterned photoresist layer includes an opening pattern (not shown) for defining the initial trench 101, then the isolation layer 13 and the gate conductive portions 121 are etched by using the patterned photoresist layer as a mask to obtain a plurality of initial trenches 101 penetrating the isolation layer 13 and the plurality of gate conductive portions 121 along the OY direction, and the remaining gate conductive portions 121 form gate conductive layers 62 arranged at intervals along the OX direction.
In some embodiments, referring to FIG. 6, after forming the initial trench 101 and before forming the channel layer, a deposition process is used to form a gate dielectric material layer (not shown) covering the top surface of the remaining isolation layer 13 and the sidewalls and bottom surface of the initial trench 101, and a dry etching process is used to remove the gate dielectric material layer on the top surface of the remaining isolation layer 13 and the bottom surface of the initial trench 101, and the remaining gate dielectric material layer is used to form the gate dielectric layer 61.
In some embodiments, referring to fig. 7, after forming the gate dielectric layer 61 and before forming the channel layer, a dry etching process may be used to remove the interlayer dielectric layer 80 exposed by the plurality of initial trenches 101 and located between the gate dielectric layers 61 adjacent to each other in the OX direction, so as to obtain a plurality of trenches 11 spaced apart in the OX direction and exposing a portion of the source electrode 10.
In some embodiments, referring to FIG. 8, forming the channel layer 30 covering the sidewalls of the trench 11 and the exposed source electrode 10 in step S60 may include forming an initial channel layer 31 covering the top surface of the remaining isolation layer 13, the sidewalls of the trench 11, and the exposed source electrode 10 using a deposition process.
In some embodiments, referring to FIG. 8, forming the dielectric core 20 in the trench 11 in step S80 may include forming a dielectric material (not shown) filling the trench 11 by a deposition process or a spin-on-glass (Spin On Glass coating, SOG) process, etching back the dielectric material to obtain the dielectric core 20 with a top surface level with the top surface of the gate conductive layer 62, and the recess 23 above the dielectric core 20. The material of the dielectric core 20 may include, but is not limited to, at least one of silicon oxide (SiO 2), silicon nitride (Si 3N4), silicon oxynitride (SiON), or the like.
In some embodiments, referring to FIG. 9, forming the drain 50 on the sidewall of the recess 23 in step S100 may include forming a drain material layer 51 conformally covering the exposed surface of the initial channel layer 31 and the top surface of the dielectric core 20 using an ALD deposition process. The material of the drain material layer 51 may include, but is not limited to, at least one of a semiconductor material, a metal silicide, and the like.
In some embodiments, referring to fig. 10, a dry etching process may be used to remove at least the drain material layer 51 on the top surface of the remaining isolation layer 13, resulting in the drain 50 being located in the recess 23.
In some embodiments, referring to fig. 10, the initial channel layer 31 on the top surface of the remaining isolation layer 13 may be removed simultaneously during the process of removing the drain material layer 51 on the top surface of the remaining isolation layer 13, so as to obtain the channel layer 30, and obtain the drain 50 covering the sidewall of the recess 23 and the top surface of the dielectric core 20, thereby reducing the complexity and cost of the manufacturing process.
In some embodiments, referring to fig. 10, the drain material layer 51 on the top surface of the dielectric core 20, the drain material layer 51 remaining in the recess 23 and on the sidewall of the channel layer 30 may be removed simultaneously during the process of removing the drain material layer 51 on the top surface of the remaining isolation layer 13 to form the drain 50.
In some embodiments, referring to fig. 10, during the removal of the drain material layer 51 on the top surface of the remaining isolation layer 13 and the top surface of the dielectric core 20, a recess 231 facing the dielectric core 20 may be formed by overetching, so that a conductive plug 40 to be subsequently prepared is partially located in the recess 231, thereby realizing a further increase in the volume of the conductive plug 40 without increasing the volume of the semiconductor device, and thus reducing the connection resistance of the conductive plug 40 to the drain.
In some embodiments, referring to fig. 11, the step S110 of forming the conductive plug 40 at least partially located in the recess 23 includes forming a barrier material layer (not shown) covering the top surface of the remaining isolation layer 13 and the side wall of the drain electrode 50 and the top surface of the dielectric core 20 by a deposition process, then forming a conductive material layer (not shown) on the exposed surface of the barrier material layer, wherein the conductive material layer and the barrier material layer at least fill the remaining gaps of the recess 23, planarizing the top surface of the conductive material layer, removing a portion of the conductive material layer and a portion of the barrier material layer located on the top surface of the remaining isolation layer 13 by photolithography and etching processes, wherein the remaining conductive material layer is used to form the conductive layer 402, the remaining barrier material layer is used to form the barrier layer 401, and the conductive layer 402 is used to form the conductive plug 40, thereby obtaining the conductive plug 40 and the isolation recess 403 alternately arranged along the OX direction. The barrier material layer can prevent metal ions during formation of the conductive material layer from entering the dielectric core 20 to form a current leakage path, thereby improving the performance and reliability of the semiconductor device.
With continued reference to fig. 11, a gate conductive layer 62 is disposed on the outer sidewall of the channel layer 30, a gate dielectric layer 61 is disposed between the gate conductive layer 62 and the channel layer 30, the top surface of the gate dielectric layer 61 is higher than the bottom surface of the conductive plug 40, and the gate dielectric layer 61 and the gate conductive layer 62 are used to jointly form the gate 60.
In some embodiments, referring to fig. 11, the gate 60 may partially surround the channel layer 30 to relatively increase the contact area between the gate 60 and the channel layer 30, thereby improving the performance and reliability of the device.
In some embodiments, the gate may circumferentially surround the channel layer to form a gate-all-around structure, further increasing the contact area between the gate and the channel layer, and improving the performance and reliability of the device.
In some embodiments, referring to fig. 12, a first dielectric layer 111 is formed on a sidewall of the isolation trench 403, and then a second dielectric layer 112 is formed in the isolation trench 403, where the first dielectric layer 111 and the second dielectric layer 112 are used to form the isolation structure 110 together, and the isolation structure 110 at least fills the isolation trench 403. A planarization process may be employed such that the top surface of isolation structures 110 is flush with the top surface of conductive plugs 40. The material of the first dielectric layer 111 includes, but is not limited to, silicon nitride. The material of the second dielectric layer 112 includes, but is not limited to, silicon oxide. The isolation structure formed by the silicon nitride and silicon oxide stack can relieve the warp stress of the substrate 100 caused by the adjacent conductive plugs 40.
In some embodiments, referring to fig. 13, the conductive plug 40 further includes a first portion 41 located in the recess 23 and a second portion 42 located above the first portion 41, and the semiconductor device further includes an interconnection pillar 90 located on a top surface of the second portion 42, wherein a vertical center line 42a of the second portion 42 is between the vertical center line 41a of the first portion 41 and the vertical center line 90a of the interconnection pillar 90, so that a specific position of the interconnection pillar 90 on the conductive plug 40 is set according to an actual requirement for manufacturing an integrated circuit, thereby reducing complexity and cost of a manufacturing process while meeting the requirement for the integrated circuit integration.
In some embodiments, referring to fig. 13, an atomic layer deposition (Atomic Layer Deposition, ALD) process is used to form a drain material layer 51 conformally covering the exposed surface of the initial channel layer 31 and the top surface of the dielectric core 20, so that the thicknesses of the drains 50 eventually located at both sides of the conductive plugs 40 are equal, and the dimensions and performance of the drains 50 at both sides of the conductive plugs 40 are kept as uniform as possible, thereby improving the performance and reliability of the semiconductor device.
In some embodiments, referring to fig. 14a, a semiconductor device is provided, which includes a substrate 100, a source electrode 10, a dielectric core 20, a channel layer 30, a conductive plug 40 and a drain electrode, wherein the source electrode 10 is located on the substrate 100, the dielectric core 20 is located on a side of the source electrode 10 facing away from the substrate 100, the channel layer 30 is located between the dielectric core 20 and the source electrode 10 and covers a bottom surface and a sidewall of the dielectric core 20, a top surface of the channel layer 30 is higher than the top surface of the dielectric core 20 and forms a recess 23 located above the dielectric core 20, the conductive plug 40 is located at least partially within the recess 23, a bottom surface of the conductive plug 40 is lower than a top surface of the channel layer 30, the drain electrode is located between the channel layer 30 and the conductive plug 40, and a sidewall of the drain electrode is covered by a portion of the conductive plug 40.
As an example, with continued reference to fig. 14a, by disposing the source 10 on the substrate 100, the dielectric core 20 on a side of the source 10 facing away from the substrate 100, the channel layer 30 between the dielectric core 20 and the source 10 and covering the bottom surface and the side walls of the dielectric core 20, a U-shaped channel layer 30 is formed, the top surface of the channel layer 30 is higher than the top surface of the dielectric core 20 and forming the recess 23 above the dielectric core 20, thereby disposing the conductive plug 40 at least partially within the recess 23 such that the bottom surface of the conductive plug 40 is lower than the top surface of the channel layer 30, and disposing the drain 50 between the channel layer 30 and the conductive plug 40 such that the side walls of the drain 50 are covered by a portion of the conductive plug 40.
In some embodiments, referring to fig. 14a, the conductive plug 40 has a longitudinal section of "T" shape, and the bottom surface of the conductive plug 40 contacts the top surface of the dielectric core 20, so that the conductive plug 40 is partially located in the recess 23 formed on the top surface of the channel layer 30 and located above the dielectric core 20, and the volume of the conductive plug 40 is relatively increased without increasing the volume of the semiconductor device, so that the drain covered by a portion of the conductive plug 40 is formed on the sidewall of the recess 23, and the contact area between the conductive plug 40 and the drain is further increased.
In some embodiments, referring to fig. 14a, the conductive plug 40 further includes a first portion 41 located in the recess 23 and a second portion 42 located above the first portion 41, the semiconductor device further includes an interconnection pillar 90, the interconnection pillar 90 is located on a top surface of the second portion 42, and a vertical center line 42a of the second portion 42 is located between the vertical center line 41a of the first portion 41 and the vertical center line 90a of the interconnection pillar 90, so that a specific position of the interconnection pillar 90 on the conductive plug 40 is set according to an actual requirement for manufacturing an integrated circuit, thereby reducing complexity and cost of a manufacturing process while meeting the requirement for the integrated circuit integration.
In some embodiments, referring to fig. 14b, the differences between fig. 14a and 14b include that the bottom surface of the conductive plug 40 contacts the top surface of the dielectric core 20 in fig. 14a, the drain 50 is located on the outer sidewall of the conductive plug 40, and the drain 50 includes a first portion 50a located between the bottom surface of the conductive plug 40 and the source 10 in fig. 14b, and a second portion 50b located on the outer sidewall of the conductive plug 40. Fig. 14b increases the contact area between the conductive plug 40 and the drain 50 with respect to fig. 14a, so that the connection resistance between the conductive plug 40 and the drain 50 can be reduced.
In some embodiments, referring to fig. 15, the bottom surface of the conductive plug 40 is lower than the bottom surface of the drain 50 and extends into the dielectric core 20, so as to further increase the volume of the conductive plug 40 without increasing the volume of the semiconductor device, thereby reducing the connection resistance between the conductive plug 40 and the drain, and the conductive plug 40 extends into the dielectric core 20, thereby reducing the complexity and cost of the manufacturing process in practical application scenarios.
In some embodiments, referring to fig. 14a, 14b or 15, the thicknesses of the drain electrodes 50 on both sides of the conductive plugs 40 are equal, so that the dimensions and performance of the drain electrodes on both sides of the conductive plugs 40 are kept as uniform as possible, thereby improving the performance and reliability of the semiconductor device.
In some embodiments, referring to fig. 14a, 14b or 15, the semiconductor device further includes a gate dielectric layer 61 and a gate conductive layer 62, wherein the gate conductive layer 62 is located on an outer sidewall of the channel layer 30, the gate dielectric layer 61 is located between the gate conductive layer 62 and the channel layer 30, and a top surface of the gate dielectric layer 61 is higher than a bottom surface of the conductive plug 40. The gate dielectric layer 61 and the gate conductive layer 62 are used to jointly form the gate electrode 60.
In some embodiments, the gate may partially surround the channel layer to relatively increase the contact area between the gate and the channel layer, thereby improving the performance and reliability of the device.
In some embodiments, the gate may circumferentially surround the channel layer to form a gate-all-around structure, further increasing the contact area between the gate and the channel layer, and improving the performance and reliability of the device.
With continued reference to fig. 15 and 16, the differences between fig. 16 and fig. 15 include that the drain 50 in fig. 16 is located outside the recess 23 and between the bottom surface of the conductive plug 40 and the top surface of the channel layer 30. Compared with fig. 16, in fig. 15, at least the contact area between the drain electrode 50 and the conductive plug 40 is increased without increasing the volume of the semiconductor device, and the volume of the conductive plug 40 is relatively increased, so that the connection impedance between the conductive plug 40 and the drain electrode 50 is reduced, and the performance and reliability of the semiconductor device are improved.
In some embodiments, a memory is provided that includes a semiconductor device in any of the embodiments of the present application.
In some embodiments, a memory is provided, including a memory fabricated using the semiconductor device fabrication method of any of the embodiments of the present application.
In some embodiments, an electronic apparatus is provided that includes the semiconductor device of any of the embodiments of the present application.
In some embodiments, an electronic device is provided that includes a memory in any of the embodiments of the present application.
The aforementioned electronic devices are, for example, but not limited to, consumer electronic products, home electronic products, vehicle-mounted electronic products, financial terminal products, and other suitable types of electronic products. The consumer electronic products are mobile phones, tablet computers, notebook computers, desktop displays, computer integrated machines and the like. Household electronic products are, for example, intelligent door locks, televisions, refrigerators, wearable devices and the like. The vehicle-mounted electronic products are, for example, vehicle-mounted navigator, vehicle-mounted DVD and the like. Financial terminal products such as terminals for ATM machines, self-service transactions, etc.
It should be noted that, for brevity, in the structural diagrams given in the following embodiments, other structural diagrams with different view angles of the structures related to the invention points of the embodiments of the present disclosure may be referred to each other, except for the corresponding cross-sectional structural diagrams.
The technical features of the foregoing embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the foregoing embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.
Claims (10)
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