CN119208384A - Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle - Google Patents

Abstract

The application discloses a semiconductor device, a preparation method, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors. The semiconductor body further comprises a first region of the first conductivity type, a well region of the second conductivity type and a second region of the second conductivity type, the second region and at least part of the first surface being connected to the source of the semiconductor device to form a schottky contact. The Schottky contact reduces the conduction voltage drop and reverse recovery time of the semiconductor device and reverse recovery energy consumption, enhances the conduction performance and anti-surge current capability of the body diode, solves the problem that holes enter the drift layer in the follow current process, reduces the risk of double-click degradation of the device, and avoids the external follow current diode, thereby reducing the complexity of circuit design and the cost of a system.

Description

Semiconductor device, manufacturing method thereof, power module, power conversion circuit and vehicle

Technical Field

The application belongs to the technical field of semiconductors, and particularly relates to a semiconductor device, a manufacturing method of the semiconductor device, a power module, a power conversion circuit and a vehicle.

Background

In a silicon carbide Metal-Oxide-Semiconductor Field-Effect Transistor (SiC MOSFET), a situation of body diode freewheeling often occurs in practical application, however, the body diode has a high turn-on voltage due to the characteristics of silicon carbide materials, which can cause a large loss, so that in the specific semiconductor application fields of photovoltaic inversion, motor driving, DCDC conversion and the like, a diode is generally required to be connected in parallel in a module as a reverse recovery diode, thereby forming a complete loop. Parallel diodes, however, incur additional costs and are limited by the form of the module package.

Disclosure of Invention

The embodiment of the application provides a semiconductor device, which comprises a semiconductor body, a trench gate structure, a source electrode and a drain electrode. The semiconductor body is provided of a first conductivity type and includes opposing first and second surfaces, the first surface being provided with a gate trench extending from the first surface into the semiconductor body, the trench gate structure being located within the gate trench. The semiconductor body further includes a first region configured to be of a first conductivity type, the first region being disposed at the first surface. The semiconductor body further includes a well region of the second conductivity type disposed on a side of the first region remote from the first surface. In addition, the semiconductor body further comprises a second region provided as a second conductivity type, which extends from the first surface into the semiconductor body. In addition, the source electrode is positioned on the first surface, and the second region and at least part of the first surface are connected with the source electrode to form a Schottky contact. The drain electrode is positioned on the second surface.

In some embodiments, the second regions are configured in at least two, sequentially arranged along a first direction parallel to the first surface.

In some embodiments, the semiconductor device further includes a schottky contact layer between the first surface and the source electrode and electrically connected to the second region.

In some embodiments, the semiconductor body further includes a source trench disposed at the first surface and extending into the semiconductor body. The semiconductor body further includes a third region of the second conductivity type disposed on the source trench surface. The semiconductor device further includes a first structure disposed in the source trench and electrically connected to the source.

In some embodiments, the first structure and the trench gate structure each comprise polysilicon.

In the embodiment of the application, the second region which is set to be of the second conductivity type and the semiconductor body which is set to be of the first conductivity type form a PN junction, and the second region and at least part of the first surface are connected with the source electrode to form Schottky contact, so that the problem that holes enter the drift layer in the follow current process can not occur, the risk of double-click degradation of the device is reduced, the conduction voltage drop and the reverse recovery time of the semiconductor device are reduced, the reverse recovery energy consumption is reduced, the conduction performance and the surge current resistance of the body diode are enhanced, the external follow current diode can be avoided, the complexity of circuit design and the system cost can be reduced, and the reliability of the silicon carbide MOSFET device is improved. In the application process of the related field, parallel diodes are not needed, so that the cost is reduced and the limitation of a module packaging form is avoided.

On the other hand, the embodiment of the application also provides a preparation method of the semiconductor device, which comprises the following steps S10-S50:

Step S10, forming a well region, a first region and a gate trench on the semiconductor body. Wherein the semiconductor body is provided of a first conductivity type and comprises a first surface and a second surface arranged opposite to each other, the gate trench extending from the first surface into the semiconductor body. The first region is set to be of a first conductivity type and is disposed on the first surface. The well region is arranged as the second conductivity type and is arranged on one side of the first region away from the first surface.

Step S20 of forming a second region, the second region being provided as a second conductivity type and extending from the first surface into the semiconductor body.

And S30, forming a trench gate structure in the gate trench.

And S40, forming a source electrode on the first surface, and connecting the second region and at least part of the first surface with the source electrode to form a Schottky contact.

And S50, forming a drain electrode on the second surface.

In some embodiments, during the formation of the gate trench, a source trench is also formed at the first surface, the source trench extending from the first surface into the semiconductor body. In the process of forming the second region, a third region is also formed on the surface of the source trench. In forming the trench gate structure in the gate trench, a first structure is also formed in the source trench.

According to the preparation method provided by the embodiment of the application, the second region is formed on the semiconductor body in the process of preparing the semiconductor device, and the second region and at least part of the first surface of the semiconductor body are connected with the source electrode to form the Schottky contact, so that the preparation method is simpler. The semiconductor device prepared by the preparation method provided by the embodiment can reduce the conduction voltage drop and the reverse recovery time of the semiconductor device, reduce the reverse recovery energy consumption, enhance the conduction performance and the surge current resistance of the body diode, avoid the problem that holes enter the drift layer in the follow current process, reduce the double-click degradation risk of the device, avoid the external follow current diode, and further reduce the design complexity and the system cost of the circuit and improve the reliability of the silicon carbide MOSFET device by the Schottky contact formed by connecting the second region and at least part of the first surface of the semiconductor body with the source electrode. In the application process of the related field, parallel diodes are not needed, so that the cost is reduced and the limitation of a module packaging form is avoided.

On the other hand, the embodiment of the application also provides a power module, which comprises a substrate and the semiconductor device of any embodiment, wherein the substrate is used for bearing the semiconductor device.

In yet another aspect, embodiments of the present application further provide a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and the semiconductor device of any of the embodiments described above is electrically connected to the circuit board.

In yet another aspect, an embodiment of the present application further provides a vehicle, where the vehicle includes a load and the power conversion circuit according to the above embodiment, and the power conversion circuit is configured to convert ac power into dc power, convert ac power into ac power, convert dc power into dc power, or convert dc power into ac power, and then input the ac power into the load.

The power module, the power conversion circuit, and the vehicle have the same structure and beneficial technical effects as those of the semiconductor device provided in some of the above embodiments, and are not described herein.

Drawings

The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

fig. 3 to 13 are views illustrating steps for manufacturing a semiconductor device according to an embodiment of the present application;

Fig. 14 is a schematic structural diagram of a power module according to an embodiment of the present application;

fig. 15 is a schematic structural diagram of a power conversion circuit according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a vehicle according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments obtained by a person skilled in the art based on the embodiments provided by the present application fall within the scope of protection of the present application.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, the expression "connected" and its derivatives may be used. The term "coupled" is used in a broad sense, e.g., as a fixed connection, as a removable connection, or as a unitary body, as a direct connection, as an indirect connection via an intermediary, e.g., where some embodiments are described, the term "coupled" may be used to indicate that two or more elements are in direct physical or electrical contact with each other.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are idealized exemplary figures. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

Examples of the embodiments are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements throughout or elements having like or similar functionality. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.

Silicon carbide materials are widely studied and paid attention to in the field of semiconductor technology because of their superior physical properties. The high-temperature high-power electronic device has the advantages of high input impedance, high switching speed, high working frequency, high temperature and high pressure resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.

Because the MOSFET device often has time to generate the situation of body diode freewheeling in practical application, however, the body diode has too high starting voltage due to the characteristics of silicon carbide material, which can cause larger loss, so that in the specific semiconductor application fields of photovoltaic inversion, motor driving, DCDC conversion and the like, a diode is often required to be connected in parallel in a module as a reverse recovery diode, thereby forming a complete loop. Parallel diodes, however, can cause additional costs and are limited by the form of the module package.

In view of the above problems, an embodiment of the present application provides a semiconductor device, as shown in fig. 1, and fig. 1 is a schematic structural diagram of the semiconductor device according to the embodiment of the present application.

As shown in fig. 1, the semiconductor device 10 includes a semiconductor body 101, a trench gate structure 102, a source 103, and a drain 104. The "semiconductor body 101" herein includes a substrate and an epitaxial layer. The semiconductor body 101 is provided of a first conductivity type and comprises opposite first and second surfaces P1, P2, the first surface P1 being provided with a gate trench T1, the gate trench T1 extending from the first surface P1 into the semiconductor body 101, a trench gate structure 102 being located within the gate trench T1, a first insulating layer 105 being further formed within the gate trench T1 for protecting the trench gate structure 102, a gate isolating dielectric layer 106 being further provided on the first surface P1, the gate isolating dielectric layer 106 covering the trench gate structure 102 for isolating and protecting the trench gate structure 102.

The source 103 is located on the first surface P1, and the drain 104 is located on the second surface P2.

In addition, the semiconductor body 101 further comprises a first region 107 provided as a first conductivity type, a well region 108 provided as a second conductivity type, and a second region 109 provided as a second conductivity type, wherein the first region 107 is provided at the first surface P1, the well region 108 is provided at a side of the first region 107 remote from the first surface P1, and the second region 109 extends from the first surface P1 into the semiconductor body 101. And, the second region 109 and at least a portion of the first surface P1 are connected to the source 103 to form a schottky contact.

In the embodiment of the present application, in the semiconductor body 101 and the first region 107 are both of the first conductivity type, the well region 108 and the second region 109 are both of the second conductivity type, and the first conductivity type is N-type and the second conductivity type is P-type, based on this, the first region 107, the well region 108 and the semiconductor body 101 form an NPN junction, and the second region 109 and the semiconductor body 101 form a PN junction. The trench gate structure 102, the source 103, and the drain 104 constitute three electrodes of the semiconductor device 10.

Since the second region 109 and at least a portion of the first surface P1 are connected to the source 103 to form a schottky contact, a schottky barrier is formed there, which has an asymmetric current-voltage characteristic allowing current to easily pass in forward bias and preventing current flow in reverse bias.

The Schottky contact has lower conduction voltage drop, and when the Schottky contact is switched from a forward conduction state to a reverse blocking state, the Schottky contact does not need to undergo the processes of charge storage and depletion, can be quickly recovered in reverse, and reduces the reverse recovery time. In addition, because the reverse recovery time of the Schottky contact is shorter, the stored charge is less in the process of switching the on state to the off state, so that the energy consumed in the reverse recovery process is also less, the reverse recovery energy consumption is reduced, and the efficiency of the circuit is improved.

In summary, the schottky contact formed by connecting the second region 109 and at least part of the first surface P1 with the source 103 reduces the on-voltage drop and the reverse recovery time of the semiconductor device 10, reduces the reverse recovery energy consumption, enhances the on-performance and the anti-surge current capability of the body diode, and in addition, the problem that holes enter the drift layer in the freewheeling process does not occur, reduces the risk of double-click degradation of the device, and does not need to be externally connected with the freewheeling diode, thereby reducing the complexity of circuit design and the system cost and improving the reliability of the silicon carbide MOSFET device. In the application process of the related fields of photovoltaic inversion, motor driving, DCDC conversion and the like, parallel diodes are not needed, so that the cost is reduced and the limitation of a module packaging form is avoided.

In some embodiments, as shown in fig. 1, the second regions 109 are configured in at least two, sequentially arranged along a first direction (X-axis direction as shown in fig. 1) parallel to the first surface P1.

The second region 109 serves to improve the electric field distribution and reduce the edge effect, thereby reducing leakage current under reverse bias. By optimizing the structural design of the second region 109, the electric field distribution is facilitated to be optimized to prevent failure caused by electric field concentration, and stability and reliability of the schottky contact in long-term operation can be improved.

In some embodiments, as shown in fig. 1, the semiconductor device 10 further includes a schottky contact layer 110, where the schottky contact layer 110 is located between the first surface P1 and the source 103 and is electrically connected to the second region 109.

The schottky contact layer 110 may include at least one of nickel (Ni) or titanium (Ti) or nickel-titanium alloy (NiTi alloy metal).

In some embodiments, as shown in fig. 1, the semiconductor body 101 further includes a source trench T2, and the source trench T2 is disposed on the first surface P1 and extends into the semiconductor body 101. In addition, the semiconductor body 101 further comprises a third region 111 provided as the second conductivity type, the third region 111 being provided at the surface of the source trench T2. The semiconductor device 10 further includes a first structure 112, where the first structure 112 is disposed in the source trench T2 and is electrically connected to the source 103.

Illustratively, as shown in fig. 1, a second insulating layer 113 is further formed in the source trench T2 for protecting the first structure 112. An ohmic contact layer 114 is further disposed on the first surface P1, and the ohmic contact layer 114 may be disposed in the same layer as the schottky contact layer 110, and the ohmic contact layer 114 covers the third region 111 and covers the first structure 112. The ohmic contact layer 114 may employ at least one of titanium (Ti) or molybdenum (Mo).

An ohmic contact layer 114 is provided between the semiconductor body 101 and the source 103 for forming an ohmic contact, which is based on a good electron exchange between metal and semiconductor, forming a low-impedance connection whose current-voltage characteristics are symmetrical, i.e. allowing a current to pass, both forward and reverse biased.

The third region 111 is of the same conductivity type as the well region 108 and is of the second conductivity type. Taking the first conductivity type as N type and the second conductivity type as P type as an example, in the semiconductor device 10 shown in fig. 1, the outlet of the vertical channel of the trench MOSFET device is directly connected with the open drift region, the junction field effect (JEFT effect) is completely eliminated, and compared with the planar MOSFET device, the semiconductor device has the advantages of smaller on-resistance and on-voltage drop and higher integration level. The second region 109 and the third region 111 may each optimize the electric field distribution within the semiconductor body 101, thereby protecting the trench gate structure 102 from breakdown of the first insulating layer 105 at trench corner locations.

In some embodiments, the first structure 112 and the trench gate structure 102 each comprise polysilicon. Based on this, it is advantageous to realize a self-aligned process, reduce parasitic capacitance of the device, and adjust a threshold voltage by a doping process. In addition, the melting point of the polysilicon is higher, which is beneficial to improving the reliability of the device.

On the other hand, the embodiment of the application also provides a preparation method of the semiconductor device, as shown in fig. 2, fig. 2 is a flowchart of a method for preparing the semiconductor device provided by the embodiment of the application, and fig. 3 to fig. 13 are each step diagram of preparing the semiconductor device provided by the embodiment of the application.

As shown in FIG. 2, the preparation method comprises the following steps S10 to S50:

In step S10, as shown in fig. 3-4, a well region 108, a first region 107 and a gate trench T1 are formed on the semiconductor body 101, wherein the semiconductor body 101 is provided of a first conductivity type and comprises a first surface P1 and a second surface P2 arranged opposite to each other, the gate trench T1 extending from the first surface P1 into the semiconductor body 101. The "semiconductor body 101" here comprises a substrate and an epitaxial layer, and "extending into the semiconductor body 101" refers to extending into the epitaxial layer. The first region 107 is provided to be of the first conductivity type and is provided to the first surface P1. The well region 108 is provided to be of the second conductivity type and is provided at a side of the first region 107 remote from the first surface P1.

Illustratively, as shown in fig. 3, the semiconductor body 101 has an N-type conductivity, and on the first surface P1 of the semiconductor body 101, a mask is formed by a photolithography process, an ion implantation region is defined, and p+ ion implantation is performed to form a well region 108. After removing the mask, the mask is formed again by a photolithography process, an ion implantation region is defined, and n+ ion implantation is performed, forming a first region 107. Wherein the implantation energy is controlled to control the ion implantation depth, so that the first region 107 is located on the first surface P1, and the well region 108 is located on a side of the first region 107 away from the first surface P1.

Thereafter, as shown in fig. 4, a gate trench T1 is formed by an etching process.

In some embodiments, during the formation of the gate trench T1, a source trench T2 is also formed at the first surface P1, the source trench T2 extending from the first surface P1 into the semiconductor body 101.

In step S20, as shown in fig. 5, a second region 109 is formed, which second region 109 is provided as a second conductivity type and extends from the first surface P1 into the semiconductor body 101.

In some embodiments, during the formation of the second region 109, a third region 111 is also formed at the surface of the source trench T2.

Illustratively, as shown in fig. 5, ion implantation regions are defined and masked to perform an ion implantation process, ultimately forming second region 109 and third region 111. The ion implantation process can be performed in multiple times and the implantation energy can be adjusted according to the implantation depth. For example, P+ ion implantation is performed 4 to 5 times, the implantation energy ranges from 40 to 1200keV according to different trench depths, and the total dose is 1E15 to 4E15.

In some embodiments, after forming the second region 109 and the third region 111, field limiting rings or junction terminations are defined in the termination region and ion implantation is completed. The field limiting rings are used for limiting the distribution of the electric field so as to control the concentration of the electric field and prevent the electric field from being excessively concentrated at the edge of the device, so that the risk of edge breakdown is reduced, and the stability and the reliability of the device are enhanced. The junction termination is used to reduce the electric field strength in the region and reduce the concentration of the electric field at the PN junction termination, thereby improving the reverse breakdown voltage of the device. The two structures can be arranged at the same time according to the function of the device and related requirements, and only one of the structures can be arranged.

And then, depositing a carbon film on the surface of the device, performing high-temperature annealing activation, and removing the carbon film after the annealing activation is completed. The process is helpful for activating doped ions and repairing lattice defects caused by ion implantation and other processes, and is beneficial for improving the yield and reliability of devices.

In step S30, as shown in FIGS. 6-8, a trench gate structure 102 is formed in the gate trench T1.

In some embodiments, during the formation of trench gate structure 102 within gate trench T1, first structure 112 is also formed within source trench T2.

Illustratively, as shown in fig. 6, the gate oxide medium on the side wall and the bottom is first thermally oxidized in the trench by a high-temperature gate oxide process, that is, the first insulating layer 105 is formed in the gate trench T1 and the second insulating layer 113 is formed in the source trench T2, where the first insulating layer 105 and the second insulating layer 113 are typically silicon dioxide, so as to provide good electrical insulation performance, prevent current leakage, and the first insulating layer 105 also functions to protect the trench gate structure 102. The third region 111 formed as described above can play a role of reverse shielding, alleviate the problem of electric field concentration of the trench gate structure 102 at the bottom of the trench, and prevent the first insulating layer 105 from being broken down at the corner position of the trench.

Then, as further shown in fig. 7, polysilicon is deposited and the excess is removed, the deposited polysilicon material is patterned into a specific shape, i.e., the trench gate structure 102 is eventually formed within the gate trench T1 and the first structure 112 is formed within the source trench T2.

For subsequent processing, as shown in fig. 8, a gate isolation dielectric layer 106 is formed, and the gate isolation dielectric layer 106 covers the trench gate structure 102 for isolating and protecting the trench gate structure 102.

In step S40, as shown in FIG. 9-FIG. 11, a source 103 is formed on the first surface P1, and the second region 109 and at least part of the first surface P1 are connected to the source 103 to form a Schottky contact.

As shown in fig. 9, a source metal window is defined by a mask patterning process, and a desired ohmic contact layer 114 is formed on the first surface P1 by using the mask as a shielding deposition metal. The ohmic contact layer 114 is illustratively metallic nickel.

Next, as shown in fig. 10, after removing the mask, a new mask is formed again and patterned to define a schottky window, and a schottky metal is deposited with the mask as a shielding material, so as to form a schottky contact layer 110 on the first surface P1. Illustratively, the schottky metal is titanium metal.

Then, as shown in fig. 11, a source electrode 103 is formed on the first surface P1, and the source electrode 103 is located on a side of the schottky contact layer 110 away from the semiconductor body 101 and is electrically connected to the schottky contact layer 110 and the ohmic contact layer 114.

Illustratively, in some embodiments, as shown in FIG. 11, aluminum thickening metal is deposited by sputtering or evaporation to form the source 103.

Thereafter, as shown in fig. 12, a passivation layer 115 is deposited and a pad window V1 is formed by etching, an insulating material is spin-coated on the surface of the passivation layer 115 and cured after development exposure, and an insulating dielectric layer 116 is formed on the surface. The pad window V1 is used for subsequent electrical connection with other elements.

In step S50, as shown in FIG. 13, a drain electrode 104 is formed on the second surface P2. Specifically, by thinning the second surface P2, the thickness of the semiconductor body 101 is reduced and a relatively flat surface is formed, followed by depositing metal and annealing to form an ohmic contact for the drain 104.

Thus, the semiconductor device 10 is completed.

In the above preparation method, during the formation of each structure of the semiconductor device 10, the second region 109 and at least part of the first surface P1 are connected with the source 103 to form schottky contact, so that the process is simpler, no additional production cost is added, the schottky contact enables the on-voltage drop and the reverse recovery time of the semiconductor device 10 to be lower, the reverse recovery energy consumption is reduced, the on-performance and the surge current resistance of the body diode are enhanced, in addition, the problem that holes enter the drift layer during the follow current process can not occur, the risk of double-click degradation of the device is reduced, no external follow current diode is needed, and the device integration level is improved. In the application process of the related fields of photovoltaic inversion, motor driving, DCDC conversion and the like, an additional parallel diode is not needed, so that the application cost of the related fields is reduced, and the semiconductor device 10 prepared by the method has higher integration level and is less limited by a packaging form.

On the other hand, the embodiment of the application also provides a power module, and fig. 14 is a schematic structural diagram of the power module provided by the embodiment of the application.

As shown in fig. 14, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments, and the substrate 201 is used to carry the semiconductor device 10.

For example, the power module 200 may function as one of a power amplifier for amplifying the power of an electrical signal, a power converter, a power controller, a power management module, or a power regulator. The power converter is used to convert electrical energy from one form to another, for example, the power converter may be an AC/DC converter or a DC/DC converter. The power controller is used for controlling the device of the power flow. The power management module is used for managing power supply and ensuring that power is stably and efficiently distributed to different parts of the electronic equipment. The power regulator is used to regulate the power output to meet the needs of a particular application.

On the other hand, the embodiment of the application also provides a power conversion circuit, and fig. 15 is a schematic structural diagram of the power conversion circuit according to the embodiment of the application.

As shown in fig. 15, the power conversion circuit 300 includes a circuit board 301 and the semiconductor device 10 in any of the above embodiments, the semiconductor device 10 is electrically connected to the circuit board 301, and the power conversion circuit 300 may be used for current conversion, voltage conversion, or power factor correction.

For example, the power conversion circuit 300 may be used as one of an AC/DC converter for converting alternating current to direct current, an AC/AC converter for converting alternating current to alternating current, a DC/DC converter for converting direct current to direct current, a DC/AC inverter for converting direct current to alternating current, a DC/AC inverter for increasing the power factor of the power supply, and a power factor correction (Power Factor Correction, PFC) circuit for reducing harmonic pollution of the power grid.

On the other hand, the embodiment of the application also provides a vehicle, and fig. 16 is a schematic structural diagram of the vehicle provided by the embodiment of the application.

As shown in fig. 16, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment, and the power conversion circuit 300 is configured to convert alternating current into direct current, alternating current into alternating current, direct current into direct current, or direct current into alternating current, and then input the alternating current into the load 401 for supplying power to the load 401.

The foregoing is merely illustrative of the embodiments of the present application, and the present application is not limited thereto, and any person skilled in the art will recognize that changes and substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A semiconductor device, comprising: A semiconductor body, which is set to a first conductivity type, includes a first surface and a second surface which are arranged opposite to each other, wherein the first surface is provided with a gate trench, and the gate trench extends from the first surface into the semiconductor body; the semiconductor body also includes a first region which is set to the first conductivity type, and the first region is arranged on the first surface; the semiconductor body also includes a well region which is set to the second conductivity type, and the well region is arranged on a side of the first region away from the first surface; the semiconductor body also includes a second region which is set to the second conductivity type, and the second region extends from the first surface into the semiconductor body; A trench gate structure, located in the gate trench; A source electrode is located on the first surface; the second region and at least a portion of the first surface are connected to the source electrode to form a Schottky contact; The drain is located on the second surface. 2 . The semiconductor device according to claim 1 , wherein the second regions are configured as at least two and are arranged in sequence along a first direction parallel to the first surface. 3 . The semiconductor device according to claim 1 , further comprising a Schottky contact layer, wherein the Schottky contact layer is located between the first surface and the source electrode and is electrically connected to the second region. 4. The semiconductor device according to claim 1 is characterized in that the semiconductor body also includes a source trench, which is arranged on the first surface and extends into the semiconductor body; the semiconductor body also includes a third region set to a second conductivity type, and the third region is arranged on the surface of the source trench; the semiconductor device also includes a first structure, which is arranged in the source trench and electrically connected to the source. 5 . The semiconductor device according to claim 4 , wherein both the first structure and the trench gate structure comprise polysilicon. 6. A method for preparing a semiconductor device, comprising: A well region, a first region and a gate trench are formed on a semiconductor body, wherein the semiconductor body is set to a first conductivity type and includes a first surface and a second surface arranged opposite to each other, and the gate trench extends from the first surface into the semiconductor body; the first region is set to a first conductivity type and is arranged on the first surface; the well region is set to a second conductivity type and is arranged on a side of the first region away from the first surface; forming a second region, wherein the second region is set to a second conductivity type and extends from the first surface into the semiconductor body; forming a trench gate structure in the gate trench; A source electrode is formed on the first surface, and the second region and at least a portion of the first surface are connected to the source electrode to form a Schottky contact; A drain electrode is formed on the second surface. 7. The preparation method according to claim 6, characterized in that, in the process of forming the gate trench, a source trench is also formed on the first surface, and the source trench extends from the first surface into the semiconductor body; In the process of forming the second region, a third region is also formed on the surface of the source trench; During the process of forming the trench gate structure in the gate trench, a first structure is also formed in the source trench. 8. A power module, comprising: At least one semiconductor device according to any one of claims 1 to 5; A substrate is used to carry the semiconductor device. 9. A power conversion circuit, characterized in that the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board. 10. A vehicle, characterized in that it comprises: a load and the power conversion circuit as claimed in claim 9, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.