CN119208249A - Method for forming semiconductor structure - Google Patents
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- CN119208249A CN119208249A CN202310769429.6A CN202310769429A CN119208249A CN 119208249 A CN119208249 A CN 119208249A CN 202310769429 A CN202310769429 A CN 202310769429A CN 119208249 A CN119208249 A CN 119208249A
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Abstract
A method for forming a semiconductor structure comprises the steps of providing a wafer, forming a metal structure in the wafer, enabling the surface of the wafer to be exposed out of the top of the metal structure, detecting the warping degree of the surface of the wafer, heating the metal structure according to the warping degree detection result, and cooling the metal structure after the heating. The invention improves the warping degree of the wafer surface, has simple and easy operation process and higher process compatibility with a mature platform, and is favorable for obtaining a semiconductor structure with higher surface quality.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductor packaging, in particular to a method for forming a semiconductor structure.
Background
The TSV (Through-Silicon Vias) technology is the core of advanced packaging technology. The TSV has a distinct point from conventional packaging techniques in that the fabrication of the TSV may be integrated into different stages of the fabrication process. The completion of a through silicon via prior to the wafer fabrication CMOS or BEOL step is commonly referred to as TSV-First. At this time, the TSV can be fabricated before the front-end metal interconnect of the Fab factory to achieve Core-to-Core connection. The scheme is studied more in the field of high-performance devices such as microprocessors at present and is mainly used as an alternative scheme of SoC. The TSV-First can also be manufactured after the CMOS is completed, and then the device manufacturing and the rear-end packaging are completed. TSV-Middle refers to the TSV being implemented before the front-end and back-end processes of wafer fabrication. And placing the TSV after the back-end-of-line is commonly referred to as TSV-Last.
TSVs increase the speed of the interconnect signal by reducing the interconnect distance, reducing the interconnect resistance. After the TSV is completed, it is usually necessary to make subsequent Metal lines and to continue stacking using Fusion Bonding or Hybrid Bonding.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which is beneficial to obtaining the semiconductor structure with higher surface quality.
In order to solve the problems, the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a wafer, forming a metal structure in the wafer, exposing the top of the metal structure on the surface of the wafer, detecting the warpage of the surface of the wafer, heating the metal structure according to the detection result of the warpage, and cooling the metal structure after the heating.
Optionally, in the step of detecting the warpage of the wafer surface, the warpage values of different areas of the wafer surface are obtained, and in the step of heating the metal structure according to the warpage detection result, the metal structure of each area is respectively heated according to the warpage values of each area of the wafer surface.
Optionally, in the step of heating the metal structure of each region according to the warpage value of each place on the wafer surface, the lower the warpage value of the region corresponding to the surrounding region is, the higher the set temperature for heating the metal structure is relative to the surrounding region.
Optionally, in the step of performing heat treatment on the metal structure according to the result of the warp detection, a corresponding heating parameter is set according to the result of the warp detection, so as to perform heat treatment on the metal structure under the heating parameter.
Optionally, in the step of performing heat treatment on the metal structure according to the result of the warp detection, the metal structure is subjected to heat treatment by using an electromagnetic induction heating method.
Optionally, in the step of providing the wafer, the wafer is placed on a stage, an electromagnetic induction coil is arranged in the stage, and in the step of heating the metal structure according to the result of warpage detection, the electromagnetic induction heating coil is used for heating the metal structure.
Optionally, a plurality of electromagnetic induction coils are disposed in the stage, and the plurality of electromagnetic induction coils are uniformly distributed in a projection area of the wafer on the surface of the stage.
Optionally, the step of performing heat treatment on the metal structure according to the result of the warp detection is further used for performing expansion treatment on the metal structure.
Optionally, in the step of providing the wafer, the step of forming the metal structure includes patterning the wafer to form a plurality of through holes, forming a metal material layer filling the through holes and covering the surface of the wafer, planarizing the metal material layer, removing the metal material layer higher than the surface of the wafer, and retaining the metal material layer located in the through holes as the metal structure.
Optionally, the metal structure is cooled, and the forming method further comprises flattening the surface of the wafer and removing the part of the metal structure protruding from the surface of the wafer.
Optionally, in the step of providing the wafer, the metal structure includes one or more of a through silicon via interconnect structure, a metal through via interconnect structure, or a metal line.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the embodiment of the invention, the metal structure is heated according to the result of the warp detection, and then cooled, so that the metal structure can be heated according to the actual concave-convex condition of the wafer surface, and then cooled, the concave-convex condition of the wafer surface is adjusted by controlling the expansion and contraction degree of the metal structure, namely, the warp degree of the wafer surface is adjusted, the warp degree of the wafer surface can be improved without depositing an additional film layer, the process is simple and easy to operate, the process compatibility with a mature platform is higher, and the semiconductor structure with higher surface quality is favorable to be obtained.
Drawings
FIGS. 1-3 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
Fig. 4 shows a graph of an example of the volume-warp change value of the metal structure after heat treatment under the same temperature condition.
Detailed Description
As known from the background art, the size of the Through-Silicon-Via (TSV) is larger than that of the Via of the Wafer (Wafer) conventional process, and the diameter of the TSV Via is typically 3um-15um and the depth is typically 3um-120 um. Since the subsequent interior of the TSV cavity needs to be filled with a metal, such as Cu, this can greatly change the warp (Warpage) of Wafer. The tortuosity (Bow) value of Wafer is made large, creating two problems as follows.
(1) Subsequent Metal (Metal) line fabrication typically uses a conventional photolithographic etching (Litho ET) and planarization (ECP) Process, where Litho requires very high power to Wafer Warpage, which can result in Litho focus failure when Wafer surface is uneven, i.e., warpage is poor, and there is no way for Litho Process to proceed normally.
(2) During Bonding, there are often special requirements on Wafer Warpage, and it is desirable that Top Wafer and Bottom Wafer be Warpage as small as possible, i.e., that the two wafers be as flat as possible, which would otherwise cause Bonding problems.
There are several commonly used ways to improve Wafer Warpage after TSV Loop:
(1) Warpage to improve Wafer by depositing a film Warpage of Wafer can be controlled by depositing a film such as an oxide film on Wafer. Generally, the film deposition is a high temperature process, and after the film deposition, the heat expansion coefficient of CTE (coefficient of thermal expansion) of different materials is different in the process of cooling to room temperature, and compared with the Si of the substrate, the shrinkage degree of different film layers is different, so that horizontal friction forces in different directions can be generated, and the Warpage of Wafer is changed.
(2) Post-processing the deposited film structure, such as ultraviolet curing (UV Cure), the UV Cure can further increase the tensile stress of the deposited film, and the principle is that the hydrogen content of the deposited material can be reduced through ultraviolet radiation, so that the stress value of the film is increased. Meanwhile, the radiation wavelength of UV Cure can be controlled to replace an unwanted hydrogen bond (for example, replace an N-H bonding Si-H bond), the content of Si-N bond is increased (wherein the Si-N bond determines the tensile stress of a material), and the tensile stress of a film layer is increased, so that the warping degree of Wafer is better controlled.
At present, the improvement WAFER WARPAGE is mainly realized by depositing a film layer, the subsequent processes of Litho Etch, ECP, CMP and the like are needed to manufacture Metal wires for connection, as the thickness of the film layer to be etched is increased by adding the deposited film layer, the thickness of photoresist is correspondingly increased, the thickness of the etched film layer is increased, the etching difficulty is correspondingly increased, the depth-to-width ratio of holes is increased, the filling difficulty of ECP is increased, and after the depth-to-width ratio of the holes is increased, the thickness of copper behind ECP is correspondingly increased, so that the Process time of Cu CMP is also prolonged.
The hole size of the TSV is large, the depth can reach tens of micrometers, the diameter is also in the order of micrometers, the quantity of Cu filled in the TSV is large, the CTE difference of Cu is large, if WAFER WARPAGE is improved by depositing a film layer, the film layer to be deposited is very thick, and the requirement of large-scale mass production cannot be met.
Meanwhile, only Warpage of the whole surface Wafer can be adjusted in the mode, and fine adjustment of WAFER WARPAGE of the sub-areas cannot be achieved.
In order to solve the problems, the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a wafer, forming a metal structure in the wafer, exposing the top of the metal structure on the surface of the wafer, detecting the warpage of the surface of the wafer, heating the metal structure according to the detection result of the warpage, and cooling the metal structure after the heating.
According to the embodiment of the invention, the metal structure is heated according to the result of the warp detection, the metal structure can be heated in a targeted manner according to the actual concave-convex condition of the wafer surface, then the metal structure is cooled, the concave-convex condition of the wafer surface is adjusted by controlling the expansion and contraction degree of the metal structure, namely the warp of the wafer surface is adjusted, the warp of the wafer surface can be improved without depositing an additional film layer, the process is simple and easy to operate, the process compatibility with a mature platform is higher, and the semiconductor structure with higher surface quality is obtained.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 3 are schematic structural views corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 1, a wafer 200 is provided, a metal structure 210 is formed in the wafer 200, and the top of the metal structure 210 is exposed on the surface of the wafer 200.
Wafer 200 is used for bonding with a wafer to be integrated in a subsequent process.
The wafer 200 has a circuit structure, after the bonding of the device wafer 200 and the wafer to be integrated is realized, the wafer to be integrated and the circuit structure in the wafer 200 can be electrically connected, so that the normal function of the packaging structure is realized, the wafer 200 is also used for realizing the vertical conduction with the wafer to be integrated, and the electrical property of the device of the wafer to be integrated is led out, so that the 3D packaging between the wafer and the wafer is realized.
In this embodiment, the material of wafer 200 comprises silicon. In other embodiments, the material of the wafer may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the wafer may be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the wafer may be a material suitable for process requirements or easy integration.
In this embodiment, in the step of providing the wafer 200, the metal structure 210 includes one or more of a through-silicon via interconnect structure, a metal through-hole interconnect structure, or a metal line.
As an example, in the present embodiment, the metal structure 210 is a Through-Silicon-Via (TSV) structure for implementing vertical conduction of the wafer 200, that is, electrical connection with other circuits can be implemented Through the TSV structure in the wafer 200.
In other embodiments, the metal structure may be other metal hole structures.
The wafer 200 is stacked in three dimensions with a greater density and smaller form factor by the TSV structure, and greatly improves chip speed and reduces chip power consumption.
In the present embodiment, the step of providing the wafer 200 includes patterning the wafer 200 to form a plurality of through holes.
The plurality of vias is used to provide spatial locations for forming the metal structure 210.
In this embodiment, a metal material layer is formed to fill the through holes and cover the surface of the wafer 200.
The metal material layer is used to form the metal structure 210.
The metal material layer covers the entire wafer 200, and thus, the formation of a metal material book may affect the warpage of the surface of the wafer 200.
In this embodiment, the metal material layer is planarized, the metal material layer higher than the surface of the wafer 200 is removed, and the metal material layer located in the through hole remains as the metal structure 210.
The larger coverage area of the metal material layer, the planarized metal material layer may also affect the warpage of the wafer 200 surface.
Referring to fig. 2, in the step of providing the wafer 200, the wafer 200 is placed on the stage 100, and the electromagnetic coil 110 is disposed in the stage 100.
An electromagnetic coil 110 is disposed within the stage 100 for subsequent heat treatment of the metal structure 210 in the wafer 200.
In the present embodiment, a plurality of electromagnetic induction coils 110 are disposed in the stage 100, and the plurality of electromagnetic induction coils 110 are uniformly distributed in a projection area of the wafer 200 on the surface of the stage 100.
The electromagnetic induction coils 110 are uniformly distributed, so that in the subsequent process of heating the metal structure 210 in the wafer 200, the heating is relatively uniform, and the electromagnetic induction coils 110 which can be used for heating are uniformly distributed in each region of the wafer 200.
Specifically, in the present embodiment, the plurality of electromagnetic induction coils 110 may be uniformly arranged in a plurality of concentric circles sequentially surrounded from small to large, or the plurality of electromagnetic induction coils 110 may be uniformly arranged in an array of a matrix.
In this embodiment, the warp detection is performed on the surface of the wafer 200.
The surface of the wafer 200 is subjected to warpage detection, so as to perform subsequent targeted heating treatment according to the detection result.
In this embodiment, in the step of performing warpage detection on the surface of the wafer 200, the warpage values of different areas of the surface of the wafer 200 are obtained.
The warp values of different areas of the surface of the wafer 200 are obtained, that is, the warp values of the whole surface of the whole wafer 200 are obtained, and the warp values can represent the concave-convex condition of the surface of the wafer 200 in detail, so that the surface of the wafer is adjusted more accurately according to the warp values.
The warp detection results of the three wafers 200 are shown in fig. 3 (a), (b) and (c).
In this embodiment, the metal structure 210 is subjected to heat treatment according to the result of the warp detection.
The metal structure 210 is heated according to the result of the warp detection, so that the roughness of the wafer 200 in different areas can be adjusted by utilizing the expansion of the metal structure 210 in different areas, thereby adjusting the warp value of the wafer 200.
In the present embodiment, according to the result of the warp detection, the metal structure 210 is heated in a targeted manner, instead of heating the entire wafer 200, so that the warp of the wafer 200 in different regions can be adjusted in a targeted manner by adjusting the metal structure 210 in each region.
In the embodiment, in the step of performing the heat treatment on the metal structure 210 according to the result of the warp detection, the heat treatment is performed on the metal structure 210 of each region according to the warp value of each region on the surface of the wafer 200.
According to the warp value of each area on the surface of the wafer 200, the metal structures 210 of each area are respectively subjected to heat treatment, that is, the metal structures 210 of the wafer 200 can be subjected to partition treatment, and according to the warp value of each area, the metal structures 210 of different areas are subjected to heat treatment corresponding to different temperatures, so that the wafers 200 of different areas can be subjected to warp adjustment in different degrees in a targeted manner, and the wafer 200 with better flatness can be obtained.
Specifically, in this embodiment, the electromagnetic induction coil 110 capable of independently controlling parameters such as power and frequency is added to different areas by designing a special machine. According to the distribution of the wafer warpage, parameters of each region are adjusted by regions by using the principle of induction heating, so that the temperature of the metal structure 210 of each region is controlled, the expansion degree of the metal structure 210 of different regions is controlled, and the wafer warpage is finely adjusted to an ideal value.
In this embodiment, in the step of performing the heat treatment on the metal structure 210 of each region according to the warpage value of each portion of the surface of the wafer 200, the set temperature for performing the heat treatment on the metal structure 210 is higher for the surrounding region in the region with the lower warpage value for the surrounding region.
The higher the set temperature for heating the metal structure 210, the greater the degree of expansion of the metal structure 210, and therefore, in a region with a lower warp value relative to the surrounding region, the higher the set temperature for heating the metal structure 210 relative to the surrounding region, the greater the warp of the wafer 200 in the region by the metal structure 210 can be improved, so that the warp value in the region tends to be similar to the warp values in other surrounding regions, and the surface flatness of the whole wafer 200 is facilitated to be improved.
Specifically, in the step of performing the heat treatment on the metal structure 210 according to the result of the warp detection in the present embodiment, the corresponding heating parameters are set according to the result of the warp detection to perform the heat treatment on the metal structure 210 under the heating parameters.
In this embodiment, in the step of performing the heat treatment on the metal structure 210 according to the result of the warp detection, the metal structure 210 is subjected to the heat treatment by using an electromagnetic induction heating method.
The electromagnetic induction heating method is used for heating the metal structure 210, so that the effect of heating only the metal structure 210 in the wafer 200 is realized, the electromagnetic induction heating method is used for heating the metal structure 210, the partition heating can be realized, the metal structures 210 in different areas of the wafer 200 are respectively heated, the targeted heating treatments of different temperatures for different warping areas are realized, and the warping degree of different areas of the wafer 200 is adjusted in a targeted manner.
Specifically, in the present embodiment, in the step of heat-treating the metal structure 210 according to the result of the warp detection, the metal structure 210 is heat-treated by the electromagnetic induction heating coil 110.
In this embodiment, the step of performing the heat treatment on the metal structure 210 according to the result of the warp detection is also used for performing the expansion treatment on the metal structure 210.
The expansion treatment, such as copper expansion treatment, is performed on the metal structure 210, so that the metal structure 210 fills the space better, the probability of having gaps in the metal structure 210 is reduced, and the performance of the semiconductor structure is improved.
In this embodiment, the step of performing the heat treatment on the metal structure 210 according to the result of the warp detection and the step of performing the expansion treatment on the metal structure 210 are simultaneously implemented by using one heat treatment, which is beneficial to improving the process efficiency.
In this embodiment, after the heating process, the metal structure 210 is cooled.
After the heating treatment, the metal structure 210 is cooled, and the wafer 200 is adjusted in surface warpage by the metal structure 210 by expansion and contraction.
In the method for forming a semiconductor structure provided in this embodiment, the surface of the wafer 200 is subjected to warp detection, the metal structure 210 is heated according to the result of warp detection, and after the heating treatment, the metal structure 210 is cooled, in this embodiment, the metal structure 210 is heated according to the result of warp detection, the metal structure 210 can be heated pertinently according to the actual concave-convex condition of the surface of the wafer 200, and then cooled, the concave-convex condition of the surface of the wafer 200 is adjusted by controlling the expansion and contraction degree of the metal structure 210, that is, the warp degree of the surface of the wafer 200 is adjusted, the deposition of an additional film layer is not required, the warp degree of the surface of the wafer 200 can be improved, the process is simple and easy to operate, and the process compatibility with a mature platform is higher, thereby being beneficial to obtaining a semiconductor structure with higher surface quality.
Referring to table 1, a temperature-warp experimental result data table is shown, specifically, table 1 shows warp detection results after heat treatment is performed on the Wafer 200 at different temperatures, wherein the heat treatment time is set to be 60 minutes (min), the heat treatment temperatures are set to be 410 ℃, 350 ℃ and 200 ℃, respectively, a Bow X change indicates a warp change value of the Wafer 200 in the X direction, a Bow Y change indicates a warp change value of the Wafer 200 in the Y direction, and from the change degrees of the warp values after heat treatment is performed on the two wafers 200 (Wafer 1 and Wafer 2) at different temperatures in table 1, it can be seen that the warp of the surface of the Wafer 200 can be better improved by the heat treatment of the embodiment, and that the higher the heat treatment temperature is, the larger the warp improvement of the Wafer 200 can be seen.
| Wafer 1 | Wafer 2 | |||
| Bow X change | Bow Y changes | Bow X change | Bow Y changes | |
| 410°C60min | 57.42 | 54.30 | 56.66 | 50.95 |
| 350°C60min | 30.03 | 22.88 | 28.60 | 22.73 |
| 200°C60min | 25.61 | 19.15 | 27.67 | 19.76 |
TABLE 1
Referring to fig. 4, there is shown a graph of the volume-warp change value of the metal structure 210 after the heat treatment under the same temperature condition, wherein the abscissa is the volume of the metal structure 210, and the ordinate is the warp change value before and after the heat treatment of the wafer 200, and the embodiment heat-treats the wafer 200 having different volumes of the metal structure 210 under the same temperature condition, as can be seen from fig. 4, the warp change value of the wafer 200 and the volume of the metal structure 210 are positively correlated under the same temperature condition, correspondingly, the mechanism is because the thermal expansion coefficients of the material (e.g., copper) of the metal structure 210 and the material (e.g., silicon) of the wafer 200 are different, so that the larger the volume of the internal metal material is, that is, the larger the volume of the metal structure 210 is, the larger the warp change of the wafer is.
In this embodiment, after cooling the metal structure 210, the forming method further includes planarizing the surface of the wafer 200 and removing the portion of the metal structure 210 protruding from the surface of the wafer 200.
After cooling the metal structure 210, the surface of the wafer 200 is planarized, and the portion of the metal structure 210 protruding from the surface of the wafer 200 is removed, which is beneficial to improving the surface flatness of the wafer 200.
In this case, the metal structure 210 on the surface of the wafer 200 has less protrusions, so that the surface of the wafer 200 is planarized, and the portion of the metal structure 210 protruding from the surface of the wafer 200 is removed, which has less influence on the warpage of the surface of the wafer 200.
Referring to table 2, the experimental results of the warp change values after different planarization processes are shown in the table, specifically, in this embodiment, after forming the metal material layer filling the through hole and covering the surface of the wafer 200 in the step of forming the metal structure 210, the metal material layer needs to be planarized to remove the metal material layer on the surface of the wafer 200, and the metal material layer in the through hole is remained as the metal structure 210, which is the first planarization process, i.e. 1st CMP (CHEMICAL MECHANICAL planarization) in table 2.
Then, in order to improve the warpage of the wafer 200, a heating process is used to heat different positions of the wafer 200 in a partitioning manner, then the metal in the metal structure 210 is heated to expand, and a certain bump is formed on the surface of the wafer 200, so that a planarization process is required to be performed on the metal material of the bump to remove the portion of the metal structure 210 protruding from the surface of the wafer 200, which is the second planarization process, i.e. 2nd CMP in table 2.
Specifically, the second planarization process is a polishing rework (CMP Rework) process, so generally, compared to the first planarization process, the second planarization process has smaller removal amount, smaller pressure on the wafer 200, and shorter process time, and thus, the second planarization process has less influence on the warpage of the wafer 200.
In addition, the area of the metal structure 210 in the wafer 200 tends to be small, so that the second planarization process has a small influence on the warpage of the wafer 200.
As an example, after the wafer 200 is subjected to the heat treatment at the process temperature of 410 ℃ for a process time of 60 minutes (min), the thickness of the bump of the metal structure 210 is about 2000 a, and after the second planarization treatment is performed, the thickness of the remaining bump is about 400 a to 500 a, i.e., the removal amount of the second planarization treatment is small.
As an example, the total time of the first planarization process is 1025 seconds(s), the total time of the second planarization process is 30s, and the time of the second planarization process is shorter than that of the first planarization process, and thus the action time on the wafer 200 is shorter.
Referring to table 2, for both wafers 200 (Wafer 1 and Wafer 2), the warp change values after the first planarization process and the second planarization process were performed were collected. After the first planarization process, the warp value of the wafer is changed greatly, and after the second planarization process, the warp value of the wafer is changed slightly, so it can be seen that the second planarization process has a small influence on the warp value of the wafer 200.
TABLE 2
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (11)
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| CN121204645A (en) * | 2025-11-27 | 2025-12-26 | 上海微釜半导体设备有限公司 | Diffusion deposition method based on furnace tube equipment and furnace tube equipment |
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| CN121204645A (en) * | 2025-11-27 | 2025-12-26 | 上海微釜半导体设备有限公司 | Diffusion deposition method based on furnace tube equipment and furnace tube equipment |
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