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CN119207246A - Method for avoiding bad pixels in frame buffer circuit in micro display chip - Google Patents

Method for avoiding bad pixels in frame buffer circuit in micro display chip Download PDF

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Publication number
CN119207246A
CN119207246A CN202411732891.XA CN202411732891A CN119207246A CN 119207246 A CN119207246 A CN 119207246A CN 202411732891 A CN202411732891 A CN 202411732891A CN 119207246 A CN119207246 A CN 119207246A
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pixel
address
frame buffer
pixel data
data
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CN119207246B (en
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张婧姣
孙雷
潘安练
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Beijing Digital Optical Core Integrated Circuit Design Co ltd
Hunan University
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Beijing Digital Optical Core Integrated Circuit Design Co ltd
Hunan University
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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Abstract

The invention relates to the technical field of micro display, and discloses a dead pixel avoiding method of a frame buffer circuit in a micro display chip, which is used for writing in and reading each address of the frame buffer circuit so as to determine the dead pixel address in the frame buffer circuit, wherein the dead pixel address cannot be used for correctly implementing writing in and reading out; the method comprises the steps of determining row and column positions of pixel points of an LED array corresponding to the bad point addresses, carrying out pixel data compensation operation on each bad point address, and driving the pixel points of the LED array corresponding to each bad point address based on the result of the pixel data compensation operation carried out by each bad point address. The invention can correctly display the picture even if the frame buffer circuit has a large number of circuit defects, and avoid display errors caused by the abnormality of the frame buffer circuit.

Description

Dead pixel avoidance method for frame buffer circuit in micro display chip
Technical Field
The invention relates to the technical field of micro display, in particular to a dead pixel avoidance method of a frame buffer circuit in a micro display chip.
Background
The Micro display chip in the prior art generally refers to a Micro-LED or Micro-OLED Micro display chip, and the Micro-LED or Micro-OLED Micro display chip refers to a display technology that self-luminous micron-level LEDs or OLEDs are taken as luminous pixel units and assembled on a driving panel to form a high-density LED array. The micro display chip has the advantages of small size, high integration level, self-luminescence and the like, and has the advantages of display brightness, resolution, contrast, energy consumption, service life, response speed, thermal stability and the like. Based on the above advantages, the display device based on the micro display chip can be manufactured as a miniature and portable product.
Because the micro display chip adopts a high integration design, and the display driving mode of the micro display chip is generally digital scanning driving at present, an integrated frame buffer circuit is generally required in the micro display chip, namely, the micro display chip receives video signals and stores the video signals in a frame buffer under different video interfaces, such as SPI or MIPI interfaces. The digital scanning driving method takes out video data from the frame buffer according to the specific scanning sequence, and writes the video data into the pixel array to realize display. This results in a large number of frame buffer circuits in the chip, which often occupies a large area of the chip. And the yield of the chip is positively correlated with the chip area, i.e. the larger the chip area is, the lower the yield is. Therefore, when there is a frame buffer in the chip, the frame buffer circuit is damaged, such as the buffer circuit at some position is abnormal, resulting in abnormal pixel data displayed.
Therefore, in the prior art, there is a need for a dead pixel avoidance method that can keep the micro display chip to perform normal display when a storage error occurs in a frame buffer circuit of the micro display chip.
Disclosure of Invention
The technical aim of the invention is to provide a dead pixel avoidance method of a frame buffer circuit in a micro display chip, according to which the micro display chip can be kept to normally display when the frame buffer circuit of the micro display chip has a storage error.
In order to achieve the technical purpose, the invention provides a dead pixel avoidance method of a frame buffer circuit in a micro display chip, which comprises the following steps:
Writing and reading each address of the frame buffer circuit to determine a bad point address in the frame buffer circuit, wherein the bad point address cannot be used for correctly performing writing and reading operations;
determining row and column positions of pixel points of the LED array corresponding to the bad point address;
The pixel data compensation operation is carried out for each bad point address, and the process of the compensation operation comprises the steps of reading pixel data corresponding to a plurality of surrounding pixel points of the pixel point corresponding to the bad point address, and calculating and obtaining the pixel data of the pixel point corresponding to the bad point address according to the pixel data corresponding to the plurality of surrounding pixel points;
and driving the LED array pixel points corresponding to each bad point address based on the result of the pixel data compensation operation performed by each bad point address.
In one embodiment, reading the pixel data corresponding to a plurality of pixels around the pixel corresponding to the defective pixel address includes reading the pixel data D 1 of the adjacent left pixel and the pixel data D 2 of the adjacent right pixel of the same row of pixels of the pixel corresponding to the defective pixel address, and averaging the pixel data D 1 and the pixel data D 2.
In one embodiment, reading the pixel data corresponding to a plurality of pixels around the pixel corresponding to the defective pixel address includes reading the pixel data D 1 of the adjacent upper pixel and the pixel data D 2 of the adjacent lower pixel of the same column of pixels of the pixel corresponding to the defective pixel address, and averaging the pixel data D 1 and the pixel data D 2.
In one embodiment, reading the pixel data corresponding to a plurality of pixels around the pixel corresponding to the defective pixel address includes reading the pixel data D 11、D12、……、D1n of the n pixels on the left side and the pixel data D 21、D22、……、D2n of the pixel on the right side adjacent to the same row of pixels of the pixel corresponding to the defective pixel address, and performing a weighted average operation on the pixel data D 11、D12、……、D1n and the pixel data D 21、D22、……、D2n.
In one embodiment, reading the pixel data corresponding to a plurality of pixels around the pixel corresponding to the defective pixel address includes reading the pixel data D 11、D12、……、D1n of the n adjacent upper pixels and the pixel data D 21、D22、……、D2n of the lower adjacent pixels of the same column of pixels of the pixel corresponding to the defective pixel address, and performing a weighted average operation on the pixel data D 11、D12、……、D1n and the pixel data D 21、D22、……、D2n.
In one embodiment, reading the pixel data corresponding to a plurality of pixels around the pixel corresponding to the defective pixel address includes reading the pixel data D 1 of the adjacent left pixel and the pixel data D 2 of the adjacent right pixel of the same row of pixels corresponding to the defective pixel address, simultaneously reading the pixel data D 3 of the adjacent upper pixel and the pixel data D 4 of the adjacent lower pixel of the same column of pixels corresponding to the defective pixel address, and averaging the pixel data D 1, the pixel data D 2, the pixel data D 3, and the pixel data D 4.
In one embodiment, reading the pixel data corresponding to a plurality of pixels around the pixel corresponding to the defective pixel address includes reading the pixel data D 11、D12、……、D1n of the n adjacent left pixels, the pixel data D 21、D22、……、D2n of the n adjacent right pixels, the pixel data D 31、D32、……、D3n of the n adjacent upper pixels and the pixel data D 41、D42、……、D4n of the n adjacent lower pixels of the same column of pixels, and performing a weighted average operation on the pixel data D 11、D12、……、D1n, the pixel data D 21、D22、……、D2n, the pixel data D 31、D32、……、D3n, and the pixel data D 41、D42、……、D4n of the same row of pixels corresponding to the defective pixel address.
In one embodiment, determining the bad point address in the frame buffer circuit, where the write-read operation cannot be performed correctly, further includes recording the error bit in the error data fed back by the bad point address.
In one embodiment, when the number of defective pixel addresses exceeds a predetermined threshold, a pixel data compensation operation is performed for each defective pixel address.
One or more embodiments of the present invention may have the following advantages over the prior art:
The invention can correctly display the picture by compensating the pixel data of the specific dead pixel of the frame buffer circuit with problems even if a large number of circuit defects occur in the frame buffer circuit, thereby avoiding display errors caused by the abnormality of the frame buffer circuit.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention, without limitation to the invention. In the drawings:
FIG. 1 is a schematic diagram of the structure of a micro display chip of the present invention;
FIG. 2 is a flow chart of a dead pixel avoidance method of a frame buffer circuit according to a first embodiment of the present invention;
FIG. 3 is a flow chart of a dead pixel avoidance method of a frame buffer circuit according to a second embodiment of the present invention;
FIG. 4 is a flow chart of a dead pixel avoidance method of a frame buffer circuit according to a third embodiment of the present invention;
FIG. 5 is a flowchart illustrating a dead pixel avoidance method of a frame buffer circuit according to a fourth embodiment of the present invention;
FIG. 6 is a flowchart illustrating a dead pixel avoidance method of a frame buffer circuit according to a fifth embodiment of the present invention;
FIG. 7 is a flowchart illustrating a dead pixel avoidance method of a frame buffer circuit according to a sixth embodiment of the present invention;
fig. 8 is a flowchart of a dead pixel avoidance method of the frame buffer circuit according to the seventh embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.
Spatial relationship terms such as "under", "above", "over" and the like may be used herein for convenience of description to describe one element or feature as illustrated in the figures in relation to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Example 1
As shown in fig. 1 and 2, the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, the frame buffer circuit includes address bits and corresponding data bits, and each storage address in the frame buffer circuit corresponds to one display pixel in the LED array. For example, when the frame buffer circuit inputs 8 bits of data bit width and the resolution of the led array is 640x480 (i.e., there are 640 columns, 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address holds one pixel, then address 0 represents 1 st row 1 st column, address 10 represents 1 st row 11 th column, address 639 represents 1 st row 640 th column, address 640 represents 2 nd row 1 st column, address 1280 represents 3 rd row 1 st column. When the SRAM bit width is 16 bits, one address holds two pixels, that is, address 0 represents the 1 st row, 1 st and 2 nd column pixels, and the 8bit higher pixel is the 1 st column or 2 nd column pixel which can be preset, and the same is true. Address 319 represents row 1, columns 639-630. The bit widths of the other different SRAMs representing one address holding a plurality of pixels can be preset.
As shown in fig. 2, the dead pixel avoidance method of the frame buffer circuit of the present embodiment includes:
s100, writing and reading operation is carried out on each address of the frame buffer circuit so as to determine a dead point address in the frame buffer circuit, wherein the dead point address cannot be used for correctly implementing writing and reading operation.
In this embodiment, the frame buffer circuit is accessed by setting a register through the I2C or SPI interface, that is, the address bits and the data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the frame buffer data is 8bit wide, the address bit wide is 16bit, when the register 0x00[0] is set to 1, the debug mode is entered, the frame buffer is controlled by the register, when 0x00[0] is 0, the normal operation mode is adopted, and the frame buffer is controlled by the normal video read/write function. When the frame buffer circuit enters the debug mode, the register 0x00 1 represents writing when it is 1, the register 0x00 1 represents reading when it is 0, the register 0x00 2 represents operation enabling of the frame buffer when it is 1, and the register 0x00 2 represents no operation of the frame buffer when it is 0.
Data is written into the frame buffer circuit, and a frame buffer address is set first, for example, two register control addresses of {0x02,0x01}, 0x02,0x01} =0, 0x02,0x01} =1, and 1 address. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, when data 0x5a is written to address 5, {0x02,0x01} = 5, 0x03=0x5a, 0x00[0] = 1,0x00[1] = 1,0x00[2] = 1 is set, and the writing operation is completed. The value of address 5 is read out and stored in register 0x 04. For example, {0x02,0x01} = 5,0x00[0] = 1,0x00[1] = 0,0x00[2] = 1, the read operation is completed, and the data of the frame buffer read-out interface is stored in the 0x04 register. The value of the 0x04 register is read out through the i2c or the spi interface to obtain the value of the frame buffer.
Each address is traversed, and the address is read after writing 0x00 value, read after writing 0xff value, read after writing 0x55 value, and read after writing 0xaa value. I.e. test value of 0x00,0xff,0x55,0xa four values. When the read value is different from the write value, the frame buffer of the address is considered to be problematic, i.e., the address is stored as an error address in the microdisplay.
S200, determining row and column positions of pixel points of the LED array corresponding to the bad point address.
S300, performing pixel data compensation operation on each bad point address, wherein the process of the compensation operation comprises the following steps:
And reading pixel data D 1 of adjacent left-side pixels and pixel data D 2 of adjacent right-side pixels of the same row of pixels corresponding to the pixel address. The pixel data is gray-scale data or brightness data when the LED pixel array is displayed.
And calculating an average value, namely (D 1+D2)/2, of the pixel data D 1 and the pixel data D 2, wherein the average value is the pixel data of the pixel point corresponding to the bad point address when the pixel point is displayed.
S400, driving the LED array pixel point corresponding to each bad point address based on the result of the pixel data compensation operation performed by each bad point address.
Example 2
As shown in fig. 1 and 3, the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, the frame buffer circuit includes address bits and corresponding data bits, and each storage address in the frame buffer circuit corresponds to one display pixel in the LED array. For example, when the frame buffer circuit inputs 8 bits of data bit width and the resolution of the led array is 640x480 (i.e., there are 640 columns, 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address holds one pixel, then address 0 represents 1 st row 1 st column, address 10 represents 1 st row 11 th column, address 639 represents 1 st row 640 th column, address 640 represents 2 nd row 1 st column, address 1280 represents 3 rd row 1 st column. When the SRAM bit width is 16 bits, one address holds two pixels, that is, address 0 represents the 1 st row, 1 st and 2 nd column pixels, and the 8bit higher pixel is the 1 st column or 2 nd column pixel which can be preset, and the same is true. Address 319 represents row 1, columns 639-630. The bit widths of the other different SRAMs representing one address holding a plurality of pixels can be preset.
As shown in fig. 3, the dead pixel avoidance method of the frame buffer circuit of the present embodiment includes:
s100, writing and reading operation is carried out on each address of the frame buffer circuit so as to determine a dead point address in the frame buffer circuit, wherein the dead point address cannot be used for correctly implementing writing and reading operation.
In this embodiment, the frame buffer circuit is accessed by setting a register through the I2C or SPI interface, that is, the address bits and the data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the frame buffer data is 8bit wide, the address bit wide is 16bit, when the register 0x00[0] is set to 1, the debug mode is entered, the frame buffer is controlled by the register, when 0x00[0] is 0, the normal operation mode is adopted, and the frame buffer is controlled by the normal video read/write function. When the frame buffer circuit enters the debug mode, the register 0x00 1 represents writing when it is 1, the register 0x00 1 represents reading when it is 0, the register 0x00 2 represents operation enabling of the frame buffer when it is 1, and the register 0x00 2 represents no operation of the frame buffer when it is 0.
Data is written into the frame buffer circuit, and a frame buffer address is set first, for example, two register control addresses of {0x02,0x01}, 0x02,0x01} =0, 0x02,0x01} =1, and 1 address. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, when data 0x5a is written to address 5, {0x02,0x01} = 5, 0x03=0x5a, 0x00[0] = 1,0x00[1] = 1,0x00[2] = 1 is set, and the writing operation is completed. The value of address 5 is read out and stored in register 0x 04. For example, {0x02,0x01} = 5,0x00[0] = 1,0x00[1] = 0,0x00[2] = 1, the read operation is completed, and the data of the frame buffer read-out interface is stored in the 0x04 register. The value of the 0x04 register is read out through the i2c or the spi interface to obtain the value of the frame buffer.
Each address is traversed, and the address is read after writing 0x00 value, read after writing 0xff value, read after writing 0x55 value, and read after writing 0xaa value. I.e. test value of 0x00,0xff,0x55,0xa four values. When the read value is different from the write value, the frame buffer of the address is considered to be problematic, i.e., the address is stored as an error address in the microdisplay.
S200, determining row and column positions of pixel points of the LED array corresponding to the bad point address.
S300, performing pixel data compensation operation on each bad point address, wherein the process of the compensation operation comprises the following steps:
and reading pixel data D 1 of adjacent upper side pixel points and pixel data D 2 of adjacent lower side pixel points of the same column of pixels corresponding to the pixel point address. The pixel data is gray-scale data or brightness data when the LED pixel array is displayed.
And calculating an average value, namely (D 1+D2)/2, of the pixel data D 1 and the pixel data D 2, wherein the average value is the pixel data of the pixel point corresponding to the bad point address when the pixel point is displayed.
S400, driving the LED array pixel point corresponding to each bad point address based on the result of the pixel data compensation operation performed by each bad point address.
Example 3
As shown in fig. 1 and 4, the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, the frame buffer circuit includes address bits and corresponding data bits, and each storage address in the frame buffer circuit corresponds to one display pixel in the LED array. For example, when the frame buffer circuit inputs 8 bits of data bit width and the resolution of the led array is 640x480 (i.e., there are 640 columns, 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address holds one pixel, then address 0 represents 1 st row 1 st column, address 10 represents 1 st row 11 th column, address 639 represents 1 st row 640 th column, address 640 represents 2 nd row 1 st column, address 1280 represents 3 rd row 1 st column. When the SRAM bit width is 16 bits, one address holds two pixels, that is, address 0 represents the 1 st row, 1 st and 2 nd column pixels, and the 8bit higher pixel is the 1 st column or 2 nd column pixel which can be preset, and the same is true. Address 319 represents row 1, columns 639-630. The bit widths of the other different SRAMs representing one address holding a plurality of pixels can be preset.
As shown in fig. 4, the dead pixel avoidance method of the frame buffer circuit of the present embodiment includes:
s100, writing and reading operation is carried out on each address of the frame buffer circuit so as to determine a dead point address in the frame buffer circuit, wherein the dead point address cannot be used for correctly implementing writing and reading operation.
In this embodiment, the frame buffer circuit is accessed by setting a register through the I2C or SPI interface, that is, the address bits and the data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the frame buffer data is 8bit wide, the address bit wide is 16bit, when the register 0x00[0] is set to 1, the debug mode is entered, the frame buffer is controlled by the register, when 0x00[0] is 0, the normal operation mode is adopted, and the frame buffer is controlled by the normal video read/write function. When the frame buffer circuit enters the debug mode, the register 0x00 1 represents writing when it is 1, the register 0x00 1 represents reading when it is 0, the register 0x00 2 represents operation enabling of the frame buffer when it is 1, and the register 0x00 2 represents no operation of the frame buffer when it is 0.
Data is written into the frame buffer circuit, and a frame buffer address is set first, for example, two register control addresses of {0x02,0x01}, 0x02,0x01} =0, 0x02,0x01} =1, and 1 address. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, when data 0x5a is written to address 5, {0x02,0x01} = 5, 0x03=0x5a, 0x00[0] = 1,0x00[1] = 1,0x00[2] = 1 is set, and the writing operation is completed. The value of address 5 is read out and stored in register 0x 04. For example, {0x02,0x01} = 5,0x00[0] = 1,0x00[1] = 0,0x00[2] = 1, the read operation is completed, and the data of the frame buffer read-out interface is stored in the 0x04 register. The value of the 0x04 register is read out through the i2c or the spi interface to obtain the value of the frame buffer.
Each address is traversed, and the address is read after writing 0x00 value, read after writing 0xff value, read after writing 0x55 value, and read after writing 0xaa value. I.e. test value of 0x00,0xff,0x55,0xa four values. When the read value is different from the write value, the frame buffer of the address is considered to be problematic, i.e., the address is stored as an error address in the microdisplay.
S200, determining row and column positions of pixel points of the LED array corresponding to the bad point address.
S300, performing pixel data compensation operation on each bad point address, wherein the process of the compensation operation comprises the following steps:
And reading pixel data D 11、D12、……、D1n of n adjacent left-side pixels and pixel data D 21、D22、……、D2n of the adjacent right-side pixels of the same row of pixels corresponding to the pixel address. Wherein D 11 is the pixel data of the pixel closest to the pixel corresponding to the bad point address on the left side, D 12 is the pixel data of the pixel next closest to the pixel corresponding to the bad point address on the left side, and so on, D 21 is the pixel data of the pixel closest to the pixel corresponding to the bad point address on the right side, D 22 is the pixel data of the pixel next closest to the pixel corresponding to the bad point address on the right side, and so on.
The pixel data is gray-scale data or brightness data when the LED pixel array is displayed.
And performing weighted average operation on the pixel data D 11、D12、……、D1n and the pixel data D 21、D22、……、D2n to obtain a pixel data compensation operation value, where the pixel data compensation operation value is the pixel data of the pixel point corresponding to the defective pixel address when displaying.
The weighted average operation is as follows:
[(D11+D21)*m1+(D12+D22)*m2+……+(D1n+D2n)*mn]/n
The m 1,……,mn is a weight coefficient, and the m 1,……,mn may be configured such that the weight of the pixel data of the selected pixel close to the pixel corresponding to the defective pixel address is greater, and the weight of the pixel data of the selected pixel far away from the pixel corresponding to the defective pixel address is smaller.
S400, driving the LED array pixel point corresponding to each bad point address based on the result of the pixel data compensation operation performed by each bad point address.
Example 4
As shown in fig. 1 and 5, the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, the frame buffer circuit includes address bits and corresponding data bits, and each storage address in the frame buffer circuit corresponds to one display pixel in the LED array. For example, when the frame buffer circuit inputs 8 bits of data bit width and the resolution of the led array is 640x480 (i.e., there are 640 columns, 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address holds one pixel, then address 0 represents 1 st row 1 st column, address 10 represents 1 st row 11 th column, address 639 represents 1 st row 640 th column, address 640 represents 2 nd row 1 st column, address 1280 represents 3 rd row 1 st column. When the SRAM bit width is 16 bits, one address holds two pixels, that is, address 0 represents the 1 st row, 1 st and 2 nd column pixels, and the 8bit higher pixel is the 1 st column or 2 nd column pixel which can be preset, and the same is true. Address 319 represents row 1, columns 639-630. The bit widths of the other different SRAMs representing one address holding a plurality of pixels can be preset.
As shown in fig. 5, the dead pixel avoidance method of the frame buffer circuit of the present embodiment includes:
s100, writing and reading operation is carried out on each address of the frame buffer circuit so as to determine a dead point address in the frame buffer circuit, wherein the dead point address cannot be used for correctly implementing writing and reading operation.
In this embodiment, the frame buffer circuit is accessed by setting a register through the I2C or SPI interface, that is, the address bits and the data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the frame buffer data is 8bit wide, the address bit wide is 16bit, when the register 0x00[0] is set to 1, the debug mode is entered, the frame buffer is controlled by the register, when 0x00[0] is 0, the normal operation mode is adopted, and the frame buffer is controlled by the normal video read/write function. When the frame buffer circuit enters the debug mode, the register 0x00 1 represents writing when it is 1, the register 0x00 1 represents reading when it is 0, the register 0x00 2 represents operation enabling of the frame buffer when it is 1, and the register 0x00 2 represents no operation of the frame buffer when it is 0.
Data is written into the frame buffer circuit, and a frame buffer address is set first, for example, two register control addresses of {0x02,0x01}, 0x02,0x01} =0, 0x02,0x01} =1, and 1 address. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, when data 0x5a is written to address 5, {0x02,0x01} = 5, 0x03=0x5a, 0x00[0] = 1,0x00[1] = 1,0x00[2] = 1 is set, and the writing operation is completed. The value of address 5 is read out and stored in register 0x 04. For example, {0x02,0x01} = 5,0x00[0] = 1,0x00[1] = 0,0x00[2] = 1, the read operation is completed, and the data of the frame buffer read-out interface is stored in the 0x04 register. The value of the 0x04 register is read out through the i2c or the spi interface to obtain the value of the frame buffer.
Each address is traversed, and the address is read after writing 0x00 value, read after writing 0xff value, read after writing 0x55 value, and read after writing 0xaa value. I.e. test value of 0x00,0xff,0x55,0xa four values. When the read value is different from the write value, the frame buffer of the address is considered to be problematic, i.e., the address is stored as an error address in the microdisplay.
S200, determining row and column positions of pixel points of the LED array corresponding to the bad point address.
S300, performing pixel data compensation operation on each bad point address, wherein the process of the compensation operation comprises the following steps:
And reading pixel data D 11、D12、……、D1n of n adjacent upper side pixels and pixel data D 21、D22、……、D2n of an adjacent lower side pixel of the same column of pixels corresponding to the pixel address. Wherein D 11 is the pixel data of the pixel closest to the pixel corresponding to the bad point address on the upper side, D 12 is the pixel data of the pixel closest to the pixel corresponding to the bad point address on the upper side, and so on, D 21 is the pixel data of the pixel closest to the pixel corresponding to the bad point address on the lower side, D 22 is the pixel data of the pixel closest to the pixel corresponding to the bad point address on the lower side, and so on.
The pixel data is gray-scale data or brightness data when the LED pixel array is displayed.
And performing weighted average operation on the pixel data D 11、D12、……、D1n and the pixel data D 21、D22、……、D2n to obtain a pixel data compensation operation value, where the pixel data compensation operation value is the pixel data of the pixel point corresponding to the defective pixel address when displaying.
The weighted average operation is as follows:
[(D11+D21)*m1+(D12+D22)*m2+……+(D1n+D2n)*mn]/n
The m 1,……,mn is a weight coefficient, and the m 1,……,mn may be configured such that the weight of the pixel data of the selected pixel close to the pixel corresponding to the defective pixel address is greater, and the weight of the pixel data of the selected pixel far away from the pixel corresponding to the defective pixel address is smaller.
S400, driving the LED array pixel point corresponding to each bad point address based on the result of the pixel data compensation operation performed by each bad point address.
Example 5
As shown in fig. 1 and 6, the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, the frame buffer circuit includes address bits and corresponding data bits, and each storage address in the frame buffer circuit corresponds to one display pixel in the LED array. For example, when the frame buffer circuit inputs 8 bits of data bit width and the resolution of the led array is 640x480 (i.e., there are 640 columns, 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address holds one pixel, then address 0 represents 1 st row 1 st column, address 10 represents 1 st row 11 th column, address 639 represents 1 st row 640 th column, address 640 represents 2 nd row 1 st column, address 1280 represents 3 rd row 1 st column. When the SRAM bit width is 16 bits, one address holds two pixels, that is, address 0 represents the 1 st row, 1 st and 2 nd column pixels, and the 8bit higher pixel is the 1 st column or 2 nd column pixel which can be preset, and the same is true. Address 319 represents row 1, columns 639-630. The bit widths of the other different SRAMs representing one address holding a plurality of pixels can be preset.
As shown in fig. 6, the dead pixel avoidance method of the frame buffer circuit of the present embodiment includes:
s100, writing and reading operation is carried out on each address of the frame buffer circuit so as to determine a dead point address in the frame buffer circuit, wherein the dead point address cannot be used for correctly implementing writing and reading operation.
In this embodiment, the frame buffer circuit is accessed by setting a register through the I2C or SPI interface, that is, the address bits and the data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the frame buffer data is 8bit wide, the address bit wide is 16bit, when the register 0x00[0] is set to 1, the debug mode is entered, the frame buffer is controlled by the register, when 0x00[0] is 0, the normal operation mode is adopted, and the frame buffer is controlled by the normal video read/write function. When the frame buffer circuit enters the debug mode, the register 0x00 1 represents writing when it is 1, the register 0x00 1 represents reading when it is 0, the register 0x00 2 represents operation enabling of the frame buffer when it is 1, and the register 0x00 2 represents no operation of the frame buffer when it is 0.
Data is written into the frame buffer circuit, and a frame buffer address is set first, for example, two register control addresses of {0x02,0x01}, 0x02,0x01} =0, 0x02,0x01} =1, and 1 address. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, when data 0x5a is written to address 5, {0x02,0x01} = 5, 0x03=0x5a, 0x00[0] = 1,0x00[1] = 1,0x00[2] = 1 is set, and the writing operation is completed. The value of address 5 is read out and stored in register 0x 04. For example, {0x02,0x01} = 5,0x00[0] = 1,0x00[1] = 0,0x00[2] = 1, the read operation is completed, and the data of the frame buffer read-out interface is stored in the 0x04 register. The value of the 0x04 register is read out through the i2c or the spi interface to obtain the value of the frame buffer.
Each address is traversed, and the address is read after writing 0x00 value, read after writing 0xff value, read after writing 0x55 value, and read after writing 0xaa value. I.e. test value of 0x00,0xff,0x55,0xa four values. When the read value is different from the write value, the frame buffer of the address is considered to be problematic, i.e., the address is stored as an error address in the microdisplay.
S200, determining row and column positions of pixel points of the LED array corresponding to the bad point address.
S300, performing pixel data compensation operation on each bad point address, wherein the process of the compensation operation comprises the following steps:
And reading pixel data D 1 of adjacent left side pixels and pixel data D 2 of adjacent right side pixels of the same row of pixels corresponding to the pixel addresses, and simultaneously reading pixel data D 3 of adjacent upper side pixels and pixel data D 4 of adjacent lower side pixels of the same column of pixels corresponding to the pixel addresses. The pixel data is gray-scale data or brightness data when the LED pixel array is displayed.
And average values of the pixel data D 1, the pixel data D 2, the pixel data D 3 and the pixel data D 4, namely (D 1+D2+D3+D4)/4, are obtained, and the average value is the pixel data of the pixel point corresponding to the bad point address when displaying.
S400, driving the LED array pixel point corresponding to each bad point address based on the result of the pixel data compensation operation performed by each bad point address.
Example 6
As shown in fig. 1 and 7, the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, the frame buffer circuit includes address bits and corresponding data bits, and each storage address in the frame buffer circuit corresponds to one display pixel in the LED array. For example, when the frame buffer circuit inputs 8 bits of data bit width and the resolution of the led array is 640x480 (i.e., there are 640 columns, 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address holds one pixel, then address 0 represents 1 st row 1 st column, address 10 represents 1 st row 11 th column, address 639 represents 1 st row 640 th column, address 640 represents 2 nd row 1 st column, address 1280 represents 3 rd row 1 st column. When the SRAM bit width is 16 bits, one address holds two pixels, that is, address 0 represents the 1 st row, 1 st and 2 nd column pixels, and the 8bit higher pixel is the 1 st column or 2 nd column pixel which can be preset, and the same is true. Address 319 represents row 1, columns 639-630. The bit widths of the other different SRAMs representing one address holding a plurality of pixels can be preset.
As shown in fig. 7, the dead pixel avoidance method of the frame buffer circuit of the present embodiment includes:
s100, writing and reading operation is carried out on each address of the frame buffer circuit so as to determine a dead point address in the frame buffer circuit, wherein the dead point address cannot be used for correctly implementing writing and reading operation.
In this embodiment, the frame buffer circuit is accessed by setting a register through the I2C or SPI interface, that is, the address bits and the data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the frame buffer data is 8bit wide, the address bit wide is 16bit, when the register 0x00[0] is set to 1, the debug mode is entered, the frame buffer is controlled by the register, when 0x00[0] is 0, the normal operation mode is adopted, and the frame buffer is controlled by the normal video read/write function. When the frame buffer circuit enters the debug mode, the register 0x00 1 represents writing when it is 1, the register 0x00 1 represents reading when it is 0, the register 0x00 2 represents operation enabling of the frame buffer when it is 1, and the register 0x00 2 represents no operation of the frame buffer when it is 0.
Data is written into the frame buffer circuit, and a frame buffer address is set first, for example, two register control addresses of {0x02,0x01}, 0x02,0x01} =0, 0x02,0x01} =1, and 1 address. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, when data 0x5a is written to address 5, {0x02,0x01} = 5, 0x03=0x5a, 0x00[0] = 1,0x00[1] = 1,0x00[2] = 1 is set, and the writing operation is completed. The value of address 5 is read out and stored in register 0x 04. For example, {0x02,0x01} = 5,0x00[0] = 1,0x00[1] = 0,0x00[2] = 1, the read operation is completed, and the data of the frame buffer read-out interface is stored in the 0x04 register. The value of the 0x04 register is read out through the i2c or the spi interface to obtain the value of the frame buffer.
Each address is traversed, and the address is read after writing 0x00 value, read after writing 0xff value, read after writing 0x55 value, and read after writing 0xaa value. I.e. test value of 0x00,0xff,0x55,0xa four values. When the read value is different from the write value, the frame buffer of the address is considered to be problematic, i.e., the address is stored as an error address in the microdisplay.
S200, determining row and column positions of pixel points of the LED array corresponding to the bad point address.
S300, performing pixel data compensation operation on each bad point address, wherein the process of the compensation operation comprises the following steps:
And reading pixel data D 11、D12、……、D1n of n adjacent left side pixels, pixel data D 21、D22、……、D2n of n adjacent right side pixels, pixel data D 31、D32、……、D3n of n adjacent upper side pixels and pixel data D 41、D42、……、D4n of n adjacent lower side pixels of the pixel point corresponding to the bad pixel address. The pixel data is gray-scale data or brightness data when the LED pixel array is displayed.
And performing weighted average operation on the pixel data D 11、D12、……、D1n, the pixel data D 21、D22、……、D2n, the pixel data D 31、D32、……、D3n and the pixel data D 41、D42、……、D4n to obtain a pixel data compensation operation value, wherein the pixel data compensation operation value is the pixel data of the pixel point corresponding to the bad point address when the pixel point is displayed.
The weighted average operation is as follows:
[(D11+D21+D31+D41)*m1+(D12+D22+D32+D42)*m2+……+(D1n+D2n+D3n+D4n)*mn]/n
The m 1,……,mn is a weight coefficient, and the m 1,……,mn may be configured such that the weight of the pixel data of the selected pixel close to the pixel corresponding to the defective pixel address is greater, and the weight of the pixel data of the selected pixel far away from the pixel corresponding to the defective pixel address is smaller.
S400, driving the LED array pixel point corresponding to each bad point address based on the result of the pixel data compensation operation performed by each bad point address.
Example 7
As shown in fig. 1 and 8, the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, the frame buffer circuit includes address bits and corresponding data bits, and each storage address in the frame buffer circuit corresponds to one display pixel in the LED array. For example, when the frame buffer circuit inputs 8 bits of data bit width and the resolution of the led array is 640x480 (i.e., there are 640 columns, 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address holds one pixel, then address 0 represents 1 st row 1 st column, address 10 represents 1 st row 11 th column, address 639 represents 1 st row 640 th column, address 640 represents 2 nd row 1 st column, address 1280 represents 3 rd row 1 st column. When the SRAM bit width is 16 bits, one address holds two pixels, that is, address 0 represents the 1 st row, 1 st and 2 nd column pixels, and the 8bit higher pixel is the 1 st column or 2 nd column pixel which can be preset, and the same is true. Address 319 represents row 1, columns 639-630. The bit widths of the other different SRAMs representing one address holding a plurality of pixels can be preset.
As shown in fig. 8, the dead pixel avoidance method of the frame buffer circuit of the present embodiment includes:
S100, writing and reading operation is carried out on each address of the frame buffer circuit so as to determine a dead point address in the frame buffer circuit, wherein the dead point address cannot be used for correctly implementing writing and reading operation. And recording error bit in error data fed back by the bad point address.
In this embodiment, the frame buffer circuit is accessed by setting a register through the I2C or SPI interface, that is, the address bits and the data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the frame buffer data is 8bit wide, the address bit wide is 16bit, when the register 0x00[0] is set to 1, the debug mode is entered, the frame buffer is controlled by the register, when 0x00[0] is 0, the normal operation mode is adopted, and the frame buffer is controlled by the normal video read/write function. When the frame buffer circuit enters the debug mode, the register 0x00 1 represents writing when it is 1, the register 0x00 1 represents reading when it is 0, the register 0x00 2 represents operation enabling of the frame buffer when it is 1, and the register 0x00 2 represents no operation of the frame buffer when it is 0.
Data is written into the frame buffer circuit, and a frame buffer address is set first, for example, two register control addresses of {0x02,0x01}, 0x02,0x01} =0, 0x02,0x01} =1, and 1 address. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, when data 0x5a is written to address 5, {0x02,0x01} = 5, 0x03=0x5a, 0x00[0] = 1,0x00[1] = 1,0x00[2] = 1 is set, and the writing operation is completed. The value of address 5 is read out and stored in register 0x 04. For example, {0x02,0x01} = 5,0x00[0] = 1,0x00[1] = 0,0x00[2] = 1, the read operation is completed, and the data of the frame buffer read-out interface is stored in the 0x04 register. The value of the 0x04 register is read out through the i2c or the spi interface to obtain the value of the frame buffer.
Each address is traversed, and the address is read after writing 0x00 value, read after writing 0xff value, read after writing 0x55 value, and read after writing 0xaa value. I.e. test value of 0x00,0xff,0x55,0xa four values. When the read value is different from the write value, the frame buffer of the address is considered to be problematic, i.e., the address is stored as an error address in the microdisplay.
S200, determining row and column positions of pixel points of the LED array corresponding to the bad point address.
S300, a pixel data compensation operation is performed for each bad address, and the process of the compensation operation uses the pixel data compensation operation method used in the foregoing embodiments 1 to 6.
S400, correcting error bits in error data fed back by each bad point address based on the result of pixel data compensation operation performed by the bad point address. I.e. the 8bit value read out of the error data is only bit erroneous and the other bits are paired. If the data is 8 bits, the 8bit error information is also stored along with the error address information, when the bit of the 8bit error information is 1, the corresponding bit is wrong, and when the bit is 0, the corresponding bit is wrong. For example, if only Bit1 is erroneous, the stored Bit error information value should be 11111101, and only Bit1 is 0. If the address has bit2 and bit6 errors, the stored bit error information value should be 10111011, i.e. bit6 and bit2 are 0. The method of the above embodiment adds bit error information to obtain the final display value. For example, the calculation result is x, the data and bit error information of the pixel are read, the correct bit of the pixel is reserved, and according to the calculated x, the error bit is filled with 0 or 1, so that the value closest to x is the final output value.
S500, driving the LED array pixel points corresponding to each bad point address based on the corrected pixel data.
The present invention may be any possible integrated technology level system, method and/or computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to perform the various aspects of the invention.
A computer readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of a computer-readable storage medium includes a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or protrusion structure within a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, should not be construed as a transitory signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through a fiber optic cable), or an electrical signal transmitted through a wire.
The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a corresponding computing/processing device or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for performing operations of the present invention can be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages and procedural programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer, partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, electronic circuitry, including, for example, programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), may perform aspects of the invention by utilizing state information of computer-readable program instructions to execute the computer-readable program instructions to personalize the electronic circuitry.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer readable program instructions may be provided to a processor of a computer, or other programmable data processing apparatus, to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, with some or all of the blocks being time-wise overlapped, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Claims (10)

1.一种微显示芯片中帧缓存电路的坏点规避方法，其特征在于，所述方法包括：1. A method for avoiding bad pixels in a frame buffer circuit in a micro display chip, characterized in that the method comprises: 对帧缓存电路的每一个地址进行写入及读取操作，以确定帧缓存电路中的无法正确实施写入读取操作的坏点地址；Performing write and read operations on each address of the frame buffer circuit to determine a bad pixel address in the frame buffer circuit where the write and read operations cannot be correctly performed; 确定所述坏点地址所对应的LED阵列的像素点的行列位置；Determine the row and column positions of the pixel points of the LED array corresponding to the bad pixel address; 针对每一个坏点地址进行像素数据补偿运算，所述补偿运算的过程包括：读取所述坏点地址所对应的像素点的周围若干像素点所对应的像素数据，并根据所述周围若干像素点所对应的像素数据计算获得所述坏点地址所对应的像素点的像素数据；A pixel data compensation operation is performed for each bad pixel address, wherein the compensation operation process includes: reading pixel data corresponding to a plurality of pixel points surrounding the pixel point corresponding to the bad pixel address, and calculating pixel data of the pixel point corresponding to the bad pixel address according to the pixel data corresponding to the plurality of pixel points surrounding the pixel point; 基于每一个坏点地址所进行的像素数据补偿运算的结果驱动每一个坏点地址所对应的LED阵列像素点。The LED array pixel point corresponding to each bad pixel address is driven based on the result of the pixel data compensation operation performed on each bad pixel address. 2.根据权利要求1所述的微显示芯片中帧缓存电路的坏点规避方法，其特征在于，读取所述坏点地址所对应的像素点的周围若干像素点所对应的像素数据包括：读取所述坏点地址所对应的像素点的同一行像素的相邻的左侧像素点的像素数据D1及相邻的右侧像素点的像素数据D2；并对所述像素数据D1及像素数据D2求取平均值。2. The bad pixel avoidance method of the frame buffer circuit in the micro display chip according to claim 1, characterized in that reading pixel data corresponding to a plurality of pixel points surrounding the pixel point corresponding to the bad pixel address comprises: reading pixel data D1 of adjacent left pixel points and pixel data D2 of adjacent right pixel points in the same row of pixels of the pixel point corresponding to the bad pixel address; and calculating an average value of the pixel data D1 and the pixel data D2 . 3.根据权利要求1所述的微显示芯片中帧缓存电路的坏点规避方法，其特征在于，读取所述坏点地址所对应的像素点的周围若干像素点所对应的像素数据包括：读取所述坏点地址所对应的像素点的同一列像素的相邻的上侧像素点的像素数据D1及相邻的下侧像素点的像素数据D2；并对所述像素数据D1及像素数据D2求取平均值。3. The bad pixel avoidance method of the frame buffer circuit in the micro display chip according to claim 1, characterized in that reading pixel data corresponding to a plurality of pixel points around the pixel point corresponding to the bad pixel address comprises: reading pixel data D1 of adjacent upper pixel points and pixel data D2 of adjacent lower pixel points in the same column of pixels of the pixel point corresponding to the bad pixel address; and calculating an average value of the pixel data D1 and the pixel data D2 . 4.根据权利要求1所述的微显示芯片中帧缓存电路的坏点规避方法，其特征在于，读取所述坏点地址所对应的像素点的周围若干像素点所对应的像素数据包括：读取所述坏点地址所对应的像素点的同一行像素的相邻的左侧n个像素点的像素数据D11、D12、……、D1n及相邻的右侧像素点的像素数据D21、D22、……、D2n；并对像素数据D11、D12、……、D1n及像素数据D21、D22、……、D2n进行加权平均运算。4. The bad pixel avoidance method of the frame buffer circuit in the micro display chip according to claim 1, characterized in that reading pixel data corresponding to a plurality of pixel points surrounding the pixel point corresponding to the bad pixel address comprises: reading pixel data D11 , D12 , ..., D1n of n adjacent left pixel points and pixel data D21 , D22 , ..., D2n of n adjacent right pixel points in the same row of pixels of the pixel point corresponding to the bad pixel address; and performing a weighted average operation on the pixel data D11 , D12 , ..., D1n and the pixel data D21 , D22 , ..., D2n . 5.根据权利要求1所述的微显示芯片中帧缓存电路的坏点规避方法，其特征在于，读取所述坏点地址所对应的像素点的周围若干像素点所对应的像素数据包括：读取所述坏点地址所对应的像素点的同一列像素的相邻的上侧n个像素点的像素数据D11、D12、……、D1n及相邻的下侧像素点的像素数据D21、D22、……、D2n；并对像素数据D11、D12、……、D1n及像素数据D21、D22、……、D2n进行加权平均运算。5. The bad pixel avoidance method of the frame buffer circuit in the micro display chip according to claim 1, characterized in that reading pixel data corresponding to a plurality of pixel points surrounding the pixel point corresponding to the bad pixel address comprises: reading pixel data D11 , D12 , ..., D1n of n adjacent upper pixel points and pixel data D21 , D22 , ..., D2n of n adjacent lower pixel points in the same column of pixels corresponding to the bad pixel address; and performing a weighted average operation on the pixel data D11 , D12 , ..., D1n and the pixel data D21 , D22 , ..., D2n . 6.根据权利要求1所述的微显示芯片中帧缓存电路的坏点规避方法，其特征在于，读取所述坏点地址所对应的像素点的周围若干像素点所对应的像素数据包括：读取所述坏点地址所对应的像素点的同一行像素的相邻的左侧像素点的像素数据D1及相邻的右侧像素点的像素数据D2，同时读取所述坏点地址所对应的像素点的同一列像素的相邻的上侧像素点的像素数据D3及相邻的下侧像素点的像素数据D4；并对所述像素数据D1、像素数据D2、像素数据D3及像素数据D4求取平均值。6. The bad pixel avoidance method of the frame buffer circuit in the micro display chip according to claim 1, characterized in that reading pixel data corresponding to a plurality of pixel points around the pixel point corresponding to the bad pixel address comprises: reading pixel data D1 of adjacent left pixel points and pixel data D2 of adjacent right pixel points in the same row of pixels of the pixel point corresponding to the bad pixel address, and simultaneously reading pixel data D3 of adjacent upper pixel points and pixel data D4 of adjacent lower pixel points in the same column of pixels of the pixel point corresponding to the bad pixel address; and calculating an average value of the pixel data D1 , pixel data D2 , pixel data D3 and pixel data D4 . 7.根据权利要求1所述的微显示芯片中帧缓存电路的坏点规避方法，其特征在于，读取所述坏点地址所对应的像素点的周围若干像素点所对应的像素数据包括：读取所述坏点地址所对应的像素点的同一行像素的相邻的左侧n个像素点的像素数据D11、D12、……、D1n、相邻的右侧像素点的像素数据D21、D22、……、D2n及同一列像素的相邻的上侧n个像素点的像素数据D31、D32、……、D3n及相邻的下侧像素点的像素数据D41、D42、……、D4n；并对像素数据D11、D12、……、D1n；像素数据D21、D22、……、D2n；像素数据D31、D32、……、D3n；像素数据D41、D42、……、D4n进行加权平均运算。7. The bad pixel avoidance method of the frame buffer circuit in the micro display chip according to claim 1, characterized in that reading pixel data corresponding to a plurality of pixel points around the pixel point corresponding to the bad pixel address comprises: reading pixel data D11 , D12 , ..., D1n of adjacent left n pixel points in the same row of pixels, pixel data D21 , D22 , ..., D2n of adjacent right pixel points and pixel data D31 , D32 , ..., D3n of adjacent upper n pixel points in the same column of pixels corresponding to the bad pixel address and pixel data D41 , D42 , ..., D4n of adjacent lower pixel points; and performing pixel data D11 , D12 , ..., D1n ; pixel data D21 , D22 , ..., D2n ; pixel data D31 , D32 , ..., D3n ; pixel data D41 , D 42 , …, D 4n perform weighted averaging operation. 8.根据权利要求1所述的微显示芯片中帧缓存电路的坏点规避方法，其特征在于，所述确定帧缓存电路中的无法正确实施写入读取操作的坏点地址进一步包括：并记录所述坏点地址所反馈的错误数据中的错误比特位。8. The method for avoiding bad pixels in a frame buffer circuit in a micro display chip according to claim 1, wherein determining the bad pixel address in the frame buffer circuit where write and read operations cannot be performed correctly further comprises: and recording the error bit in the error data fed back by the bad pixel address. 9.一种电子设备，其特征在于，包括处理器以及存储器，所述存储器存储有计算机可读取指令，当所述计算机可读取指令由所述处理器执行时，运行如权利要求1-8任一所述的坏点规避方法。9. An electronic device, comprising a processor and a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the bad pixel avoidance method according to any one of claims 1 to 8 is executed. 10.一种Micro-LED显示芯片，其特征在于，所述Micro-LED显示芯片的驱动电路中依据如权利要求1-8之一所述的坏点规避方法驱动LED发光元件进行显示。10. A Micro-LED display chip, characterized in that a driving circuit of the Micro-LED display chip drives an LED light-emitting element for display according to the bad pixel avoidance method according to any one of claims 1 to 8.
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