CN119203909A - Winding method, winding device and readable storage medium based on test structure design - Google Patents
Winding method, winding device and readable storage medium based on test structure design Download PDFInfo
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Abstract
The application relates to a winding method, a winding device and a readable storage medium based on test structure design, which are characterized in that a target area is determined by obtaining a layout, a plurality of winding tasks in the target area are obtained, the winding tasks comprise pins of a test structure to be subjected to winding connection and corresponding bonding pads, the shortest path of each winding task is calculated in the target area, and winding paths are sequentially generated for each winding task based on preset wiring information and the shortest paths until all the winding tasks are completed, so that the problem that the measurement error of the test structure is large due to the fact that the winding randomness of a bit line/word line connection mode is large is solved, the winding paths are sequentially optimized based on the shortest paths, the calculation efficiency of the winding paths is improved, and the reliability of the winding paths is also improved.
Description
Technical Field
The present application relates to the field of integrated circuit design and manufacturing, and more particularly, to a winding method, a winding device, and a readable storage medium based on test structure design.
Background
The design and testing of the test structure (Testkey) may be performed in a WAT test for integrity and reliability testing to ensure that the chip meets specification requirements and quality standards. This helps to improve the quality and reliability of the product and reduce the defective rate. Testkey is critical to the design in that the layout and distribution of testkey is determined to ensure proper placement and quantity on the chip. This would involve balancing the trade-off between chip real estate, area constraints, and test requirements. For example, array testkey refers to a type testkey that has high repeatability and expansibility.
Conventional wire-wrap designs are limited to the form of two pads connected to one test structure, see fig. 1, where up to N-1 test structures (where N is the number of pads) are placed. If the connection is made in the form of bit line/word line (bit line/word line), referring to fig. 9 (the winding path is omitted for clarity of illustration), that is, one test structure is commonly selected by one bit line BL signal (bit line 1/bit line 2/bit line 3/bit line 4/bit line 5/bit line 6) and one word line WL signal (word line 1/word line 2/word line 3/word line 4/word line 5), the number of test structures can be increased to (N/2)/(2) at most.
However, the bit line/word line connection mode has no unified winding rule, and the winding given by the designer is often random, so that the path calculation efficiency is low, the path reliability is poor, the non-uniformity of the parasitic effect of the test structure is easy to cause, and the accuracy of the test result of the test structure is affected.
Disclosure of Invention
In this embodiment, a winding method, a winding device and a readable storage medium based on a test structure design are provided to solve the problems of low efficiency and poor reliability of the winding design in the related art.
In a first aspect, in this embodiment, a winding method based on a test structure design is provided, where the method includes:
Obtaining a layout, determining a target area, and obtaining a plurality of winding tasks in the target area, wherein the winding tasks comprise pins of a test structure to be subjected to winding connection and corresponding bonding pads;
Calculating the shortest path of each winding task in the target area;
And generating winding paths for the winding tasks in turn based on preset wiring information and the shortest paths until all the winding tasks are completed.
In some embodiments, the target area is internally divided into networks with the same size, and a forbidden area, an occupied area and a routing area are defined in the target area;
the forbidden area comprises an edge grid of the target area, a grid occupied by the test structure and a grid occupied by the bonding pad;
The occupied area comprises a grid occupied by the existing winding;
And the remaining area of the target area, from which the forbidden area and the occupied area are removed, is a routing area.
In some of these embodiments, said calculating, in said target area, a shortest path for each of said winding tasks comprises:
based on a uniform grid winding algorithm, respectively calculating the shortest paths of all winding tasks in the wiring area of the target area;
the shortest path is a connecting path with the least occupied grids, and the connecting path is a path for connecting pins of the test structure and the corresponding bonding pads;
The uniform grid winding algorithm comprises the steps that starting from a starting grid where the center position of a pin is located in the routing area, numbering adjacent grids in an ascending order, finally searching a termination grid where the center position of a bonding pad is located, and taking a path with the minimum number of the termination grid as a shortest path.
In some of these embodiments, the uniform grid winding algorithm further comprises:
and defining the pin-out direction of the starting grid and/or the ending grid, wherein adjacent grids of the starting grid and/or the ending grid refer to adjacent grids in the pin-out direction.
In some embodiments, generating a winding path for each winding task in turn based on preset wiring information and the shortest path until all the winding tasks are completed, including:
obtaining the incomplete winding task as a current task;
Confirming and/or optimizing the shortest path of the current task based on the routing area;
generating a winding path according to the confirmed shortest path based on preset wiring information and the wiring area;
Grid filling is carried out based on the winding path, the current task is completed, and the wiring area is updated;
And continuing to acquire the unfinished winding task as a current task to process until all the winding tasks are completed.
In some embodiments, the obtaining the incomplete winding task as the current task includes obtaining the incomplete winding task corresponding to the shortest path with the longest path length as the current task.
In some embodiments, the method further includes obtaining preset wiring information, and specifically includes:
Acquiring winding width information, wherein the winding width information comprises the maximum winding width and the minimum winding width of different metal layers;
Acquiring a winding distance of the wiring;
Obtaining path resistance information, wherein the path resistance information comprises square resistance values of different metal layers, resistance values of through holes with different sizes and winding resistance reference values;
wherein one of said blocks refers to a grid;
The different metal layers include a first metal layer along the transverse trace and a second metal layer along the longitudinal trace, and the via is used to connect the metal traces in the first metal layer and the second metal layer.
In some embodiments, the obtaining the winding resistance reference value includes:
in all the winding tasks, the shortest path with the largest path length is taken as a reference path;
based on the maximum winding widths of the different metal layers, the wiring widths of the reference paths are expanded, and corresponding reference winding paths are obtained;
And calculating the winding resistance values and the through hole resistance values of different metal layers in the reference winding path according to the path resistance information to obtain the total winding resistance value of the reference winding path, namely, the total winding resistance value is used as the winding resistance reference value.
In some of these embodiments, after obtaining the corresponding reference winding path, further comprising:
And filling grids based on the reference winding paths, completing the corresponding winding tasks, and updating the wiring area.
In some of these embodiments, the validating and/or optimizing the shortest path of the current task based on the routing area includes:
based on the routing area, confirming the shortest path of the current task or completing confirmation after optimizing the shortest path of the current task, wherein the method specifically comprises the following steps:
step 1) judging whether grids of the shortest path of the current task are all in the routing area or not:
If yes, confirming the shortest path;
If not, discarding the shortest path, and updating the routing area based on the discarded shortest path;
step 2) recalculating the shortest path of the current task and recalculating to the processing of step 1).
In some embodiments, generating a winding path according to the confirmed shortest path based on preset wiring information and the routing area includes:
Generating a winding path meeting preset rules based on the shortest path and wiring information, and confirming the winding path based on the wiring area, wherein the preset rules comprise preset rules set based on winding width information and preset rules set based on winding resistance reference values, and the method specifically comprises the following steps:
step 3) expanding the wiring width of the shortest path based on the winding width information and the path resistance information to generate a winding path, wherein the difference between the path resistance value of the winding path and the winding resistance reference value meets the preset condition;
Step 4), judging whether grids of the winding paths are all in the wiring area or not:
If yes, confirming the winding path of the current task;
If not, the winding path is abandoned, the processing is carried out in the step 3), or after the shortest path is abandoned and the routing area is updated, the shortest path is confirmed and/or optimized based on the routing area again.
In some of these embodiments, expanding the routing width of the shortest path to generate a routing path includes:
and calculating the wiring widths of different metal layers in the shortest path by using a Lagrange multiplier method to generate a winding path, wherein the difference value of the wiring widths of adjacent metal layers is within a preset range.
In some of these embodiments, after expanding the wiring width of the shortest path to generate a wiring path, further comprising:
If the wiring width is smaller than the minimum wiring width of the corresponding metal layer in the wiring width information, discarding the shortest path and updating the routing area, and then confirming and/or optimizing the shortest path based on the routing area again;
if the wiring width is larger than the maximum winding width of the corresponding metal layer in the winding width information, judging whether the wiring width is within a preset redundancy value range, if so, confirming a winding path of a current task, and if not, reporting an abnormality.
In a second aspect, in this embodiment, there is provided a winding device based on a test structure design, the device including:
the task acquisition module is used for acquiring a layout, determining a target area and acquiring a plurality of winding tasks in the target area, wherein the winding tasks comprise pins of a test structure to be subjected to winding connection and corresponding bonding pads;
The shortest path calculation module is used for calculating the shortest path of each winding task in the target area;
And the path optimization module is used for sequentially generating winding paths for the winding tasks based on preset wiring information and the shortest path until all the winding tasks are completed.
In a third aspect, the present application also provides a computer device. The computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the winding method based on the test structure design in the first aspect when executing the computer program.
In a fourth aspect, the present application also provides a computer-readable storage medium. The computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the test structure design based winding method of the first aspect.
Compared with the related art, the winding method, the winding device and the readable storage medium for the test structure design provided by the embodiment are characterized in that a target area is determined by obtaining a layout, a plurality of winding tasks in the target area are obtained, the winding tasks comprise pins of a test structure to be subjected to winding connection and corresponding bonding pads, the shortest paths of the winding tasks are calculated in the target area, the winding paths of the winding tasks are sequentially generated based on preset wiring information and the shortest paths until all the winding tasks are completed, the problem that the test structure measurement error is large due to the fact that the winding randomness of a bit line/word line connection mode is large is solved, the winding paths are sequentially optimized based on the shortest paths, the calculation efficiency of the winding paths is improved, and the reliability of the winding paths is also improved.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a schematic diagram of a conventional test structure in one embodiment;
FIG. 2 is a block diagram of the hardware architecture of a terminal of a winding method based on test structure design in one embodiment;
FIG. 3 is a flow chart of a winding method based on a test structure design in one embodiment;
FIG. 4 is a flow chart of a winding method based on test structure design in a preferred embodiment;
FIG. 5 is a schematic illustration of a gridded target region in a preferred embodiment;
FIG. 6 is a schematic diagram of a test structure and pads in a preferred embodiment;
FIG. 7 is a schematic diagram of the connection paths of test structures and pads in a target area in a preferred embodiment;
FIG. 8 is a block diagram of a winding device designed based on a test structure in one embodiment;
FIG. 9 is a schematic diagram of a test structure routing scheme based on bit lines/word lines in one embodiment.
Reference numeral 102, a processor, 104, a memory, 106, a transmission device, 108, an input and output device, 10, a task acquisition module, 20, a shortest path calculation module and 30, a path optimization module.
Detailed Description
The present application will be described and illustrated with reference to the accompanying drawings and examples for a clearer understanding of the objects, technical solutions and advantages of the present application.
Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these" and similar terms in this application are not intended to be limiting in number, but may be singular or plural. The terms "comprises," "comprising," "includes," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes the association relationship of the association object, and indicates that three relationships may exist, for example, "a and/or B" may indicate that a exists alone, a and B exist simultaneously, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this disclosure, merely distinguish similar objects and do not represent a particular ordering for objects.
The method embodiments provided in the present embodiment may be executed in a terminal, a computer, or similar computing device. For example, the terminal is operated, and fig. 2 is a block diagram of the hardware structure of the terminal of the winding method based on the test structure design in the present embodiment. As shown in fig. 2, the terminal may include one or more (only one is shown in fig. 2) processors 102 and a memory 104 for storing data, wherein the processors 102 may include, but are not limited to, a microprocessor MCU, a programmable logic device FPGA, or the like. The terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 2 is merely illustrative and is not intended to limit the structure of the terminal. For example, the terminal may also include more or fewer components than shown in fig. 2, or have a different configuration than shown in fig. 2.
The memory 104 may be used to store computer programs, such as software programs of application software and modules, such as computer programs corresponding to the winding method based on the test structure design in the present embodiment, and the processor 102 executes the computer programs stored in the memory 104 to perform various functional applications and data processing, that is, implement the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. The network includes a wireless network provided by a communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as a NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
In this embodiment, a winding method based on a test structure design is provided, and fig. 3 is a flowchart of the winding method based on the test structure design in this embodiment, as shown in fig. 3, the flowchart includes the following steps:
Step S210, obtaining a layout, determining a target area, and obtaining a plurality of winding tasks in the target area, wherein the winding tasks comprise pins of a test structure to be subjected to winding connection and corresponding bonding pads.
Specifically, in the layout, a certain area region is taken as the largest region which can be drawn by the layout, namely a target region, and is preferably rectangular. The area in which the test structures and pads are located is defined in the target area, the test structures and pads being arranged in an array and being regularly arranged, so that when the test structures are defined in the target area, the area of the pads can be defined on the same principle by defining an initial test structure, such as the test structure located in the lower left corner of the target area. Compared with the traditional mode that two bonding pads are connected with one testing structure, more testing structures can be connected to the same bonding pad in the embodiment of the application. However, the application is not limited to a specific connection mode of the bonding pad and the test structure, and can be applied to different application scenes.
In step S220, in the target area, the shortest path of each winding task is calculated.
Specifically, the shortest connection path, i.e., the shortest path, between the pins of the test structure and the corresponding pads is explored. At this time, there may be overlapping between different shortest paths, and the overlapping shortest paths may be optimized in a subsequent step. The shortest path includes a first path along the transverse trace and a second path along the longitudinal trace, the path length of the shortest path being the sum of the lengths of the first and second paths.
Step S230, generating winding paths for all winding tasks in sequence based on preset wiring information and the shortest paths until all the winding tasks are completed.
The method comprises the steps of adjusting wiring width based on the shortest path, determining winding paths of all winding tasks, and filling grids based on the winding paths to complete all winding tasks.
The wiring information comprises wiring width information, path resistance information and path resistance information, wherein the wiring width information comprises maximum wiring widths and minimum wiring widths of different metal layers, the path resistance information comprises square resistance values of the different metal layers and resistance values of through holes with different sizes, the different metal layers comprise a first metal layer along transverse wiring and a second metal layer along longitudinal wiring, and the through holes are used for connecting metal wiring in the first metal layer and the second metal layer.
The routing path optimization includes expanding the width of the shortest path within the range indicated by the routing width information, including expanding the wiring width of the first path and the wiring width of the second path, and determining the number and size of the vias, so that the widths of the first path and the second path are equal or close to each other, which is generally more advantageous for layout design, so that the wiring width of the first path and the wiring width of the second path are collectively indicated as the wiring width hereinafter. Meanwhile, whether the total resistance value of the path after the wiring width is expanded meets the preset requirement is considered, and the total resistance value is generally equal to or similar to the set winding resistance reference value.
The method for calculating the total resistance of the winding path comprises the steps of calculating the resistance of the transverse wire, calculating the resistance of the longitudinal wire, calculating the resistance of a through hole connecting the transverse wire and the longitudinal wire, and adding the resistance of the transverse wire, the resistance of the longitudinal wire and the resistance of the through hole to obtain the total resistance of the winding path. The resistance value of the transverse wire can be calculated by adopting a method of (length multiplied by width multiplied by square resistance value), namely, the resistance value of the transverse wire can be obtained based on the multiplication result of the wiring width, the length of the first path and the square resistance value of the first metal layer, the resistance value of the longitudinal wire can be calculated in the same way, the resistance value of the through holes can be calculated by adopting the method of (the number of the through holes multiplied by the resistance value of the through holes with the corresponding size), and the through holes with the proper size can be selected based on the wiring width, the resistance reference value, the winding mode and the like, so that the resistance value of the through holes can be obtained.
After the final wiring width is determined, generating a winding path based on the corresponding shortest path expansion, and filling grids based on the winding path to complete the corresponding winding task.
In the embodiment, a target area is determined by obtaining a layout, a plurality of winding tasks in the target area are obtained, the winding tasks comprise pins of a test structure to be subjected to winding connection and corresponding bonding pads, shortest paths of the winding tasks are calculated in the target area, and the winding paths of the winding tasks are sequentially optimized based on preset wiring information and the shortest paths until all the winding tasks are completed, so that the problem of larger measurement errors of the test structure caused by large winding randomness of a bit line/word line connection mode is solved, the winding paths are sequentially optimized based on the shortest paths, the calculation efficiency of the winding paths is improved, and the reliability of the winding paths is also improved.
In some of these embodiments, the interior of the target area is divided into networks of equal size, i.e. the target area is evenly meshed. The method comprises the steps that a forbidden area, an occupied area and a routing area are defined in a target area, wherein the forbidden area comprises an edge grid of the target area, a grid occupied by the test structure and a grid occupied by the bonding pad, the occupied area comprises a grid occupied by an existing winding, and the rest area of the target area, from which the forbidden area and the occupied area are removed, is the routing area.
Specifically, in the process of optimizing the subsequent winding path, the occupied area and the routing area are continuously updated, and even the forbidden area can be adjusted according to the requirement.
In this embodiment, the target area is dotted, so that the test result, the bonding pad, each path and other areas in the target area are efficiently located, and by defining the forbidden area, the occupied area and the routing area, the area incapable of routing is automatically avoided, and the reliability of path calculation is improved.
In some of these embodiments, in the target area, calculating the shortest path for each winding task includes:
based on a uniform grid winding algorithm, calculating shortest paths of each winding task in a routing area of a target area, wherein the shortest paths are connecting paths occupying the minimum number of grids, the connecting paths are paths connecting pins of a test structure and corresponding bonding pads, and the path width of the shortest paths is one grid, namely, the path length of the shortest paths is represented by the number of grids occupied by the shortest paths in a metal layer.
The uniform grid winding algorithm comprises the steps of starting from a starting grid where the center position of a pin is located in a routing area, numbering adjacent grids in an ascending order, finally searching a termination grid where the center position of a bonding pad is located, and taking a path with the minimum number of the termination grid as a shortest path.
In some of these embodiments, the uniform grid winding algorithm further comprises:
the pin-out direction of the start grid and/or the end grid is defined, and adjacent grids of the start grid and/or the end grid refer to adjacent grids in the pin-out direction.
Specifically, the pin direction is defined, so that the selection of a part of initial grids for connection can be eliminated, and the calculation time and the storage space of winding are reduced.
In some embodiments, the wire winding path optimization is sequentially performed on each wire winding task based on preset wire routing information and a shortest path until all the wire winding tasks are completed, including:
Step S231, obtaining the incomplete winding task as a current task.
And step S232, confirming and/or optimizing the shortest path of the current task based on the routing area.
Specifically, based on the routing area, the shortest path of the current task is confirmed, or the shortest path of the current task is optimized and then confirmation is completed.
Step S233, calculating to obtain a winding path according to the confirmed shortest path based on preset wiring information and a wiring area.
Step S234, grid filling is carried out based on the winding paths, the current task is completed, and the routing area is updated.
Step S235, continuing to acquire the incomplete winding task as a current task, and processing in step S232 until all winding tasks are completed.
In this embodiment, the reliability of the winding path is ensured to be finally obtained through repeated confirmation of the shortest path and the winding path.
In some of these embodiments, step S231, the acquisition of the incomplete winding task as the current task includes acquiring the incomplete winding task corresponding to the shortest path having the longest path length as the current task.
Specifically, when the current task is selected each time, the winding task with the largest occupied grid number is used as the current task, so that winding calculation is performed according to the descending order of the occupied grid number.
In some embodiments, the method further includes obtaining preset wiring information, and specifically includes:
And obtaining winding width information, wherein the winding width information comprises the maximum winding width and the minimum winding width of different metal layers.
And acquiring the winding space of the wiring, and occupying the grid where the winding path is positioned and the peripheral grids in the winding space as occupied areas based on the winding space after one winding path is confirmed so as to update the wiring area, thereby avoiding interference among a plurality of winding paths.
And obtaining path resistance information, wherein the path resistance information comprises square resistance values of different metal layers, resistance values of through holes with different sizes and winding resistance reference values.
In this embodiment, one block refers to one grid, but in other embodiments, one block does not necessarily need to be equal to the same grid, and the present application is not limited specifically. The different metal layers include a first metal layer along the lateral trace and a second metal layer along the longitudinal trace, and the via is used to connect the metal traces in the first metal layer and the second metal layer.
The winding resistance reference value may be set in advance, or may be obtained by calculating the first winding task when the first winding task is performed. The winding resistance reference value set in advance may be set in advance according to a priori knowledge, or may be calculated in advance based on a winding task.
In some of these embodiments, the obtaining of the winding resistance reference value includes:
in step S310, the shortest path having the largest path length is set as the reference path in all the winding tasks.
Specifically, the path width of the shortest path is one grid, so the path length is counted by the occupied grid amount, and the occupied grid is the largest, namely the path length is the largest.
Step S320, based on the maximum winding widths of the different metal layers, the wiring widths of the reference paths are expanded to obtain corresponding reference winding paths.
Step S330, according to the path resistance information, the winding resistance values and the through hole resistance values of different metal layers in the reference winding path are calculated to obtain the total winding resistance value of the reference winding path, namely the winding resistance reference value.
In some embodiments, after obtaining the corresponding reference winding path, the method further comprises filling grids based on the reference winding path, completing the corresponding winding task, and updating the routing area.
Specifically, according to the wiring width confirmed in the reference wiring path, the first metal layer and the second metal layer are respectively filled, and the first metal layer and the second metal layer are connected through the through holes matched with the wiring width, so that corresponding winding tasks are completed, and the winding task corresponding to the reference wiring path is the first winding task to be filled, and the winding task is completed. Updating the grid occupied by the reference winding path in the occupied area, and obtaining the wiring area based on the updated occupied area.
The winding task corresponding to the reference winding path is used as the winding task of the first process in this embodiment, and after the wire width is expanded based on the shortest path, the mesh filling is directly performed based on the winding reference path, so as to complete the winding task. However, in other embodiments, the grid after the shortest path expansion is possibly an occupied grid, for example, the defined maximum winding width is larger, and the grid is expanded to the boundary of the test structure or the target area, so that the winding needs to be completed after the specific grid filling after the processing of step S232 and step S233 as the subsequent processing of the winding task is performed. However, before winding, the first winding task of this embodiment, that is, the winding reference path, can directly perform grid filling, because these problems are avoided by setting the routing area, for example, the area grid within a certain distance range (greater than the maximum wiring width) of the test structure and the edge grid of the target area are set to forbidden areas. However, in other embodiments, if this limitation is not made before winding, the first winding task also needs to make the processing determination of step S232 and step S233 before the grid occupancy filling is performed.
In some embodiments, step S232, performing adjustment confirmation and/or optimization on the shortest path of the current task based on the routing area, includes:
Step S410, judging whether grids of the shortest paths of the current task are all in the routing area, if yes, confirming the shortest paths, ending the processing of the current task in step S232, if not, discarding the shortest paths, and updating the routing area based on the discarded shortest paths.
Step S420, recalculates the shortest path of the current task, and reverts to step S410 for processing.
Specifically, the occupied area in the target area is updated based on the discarded shortest path to obtain an updated routing area. The lattice points of the discarded shortest path middle section can be partially occupied, so that the occupied area is updated.
In the embodiment, the optimal wire winding path between the pins and the bonding pads can be automatically laid out, and the existing wire winding and the area incapable of winding can be automatically avoided.
In some embodiments, step S233, based on preset routing information and routing area, calculates a routing path according to the confirmed shortest path, including:
And step S510, expanding the wiring width of the shortest path based on the winding width information and the path resistance information to generate a winding path, wherein the difference between the path resistance value of the winding path and the winding resistance reference value meets the preset condition.
Specifically, the difference in wiring widths of the adjacent metal layers is within a preset range.
Step S520, judging whether grids of the winding paths are all in the routing area, if yes, confirming the winding paths of the current task, ending the processing of the current task in step S233, if not, discarding the winding paths, and then restarting to step S510 for processing, or discarding the shortest paths and updating the routing area, and then confirming and/or optimizing the shortest paths again based on the routing area.
In the embodiment, an optimal solution is provided for each section of winding width, so that the winding width is more reasonable and the process is more stable, and resistance calculation is provided for each section of winding, so that the resistance value of each winding path is close.
In some embodiments, expanding the wiring widths of the shortest paths to generate the wiring paths includes calculating wiring widths of different metal layers in the shortest paths to generate the wiring paths using Lagrangian multiplier method, wherein differences in wiring widths of adjacent metal layers are within a preset range.
Specifically, the principle of calculating the path width by the Lagrange multiplier method is that we need to calculate the optimal solution of the width Wx of the transverse trace and the width Wy of the longitudinal trace according to the following formula:
R=R1×Lx/Wx+R2×Ly/Wy+m×Rv_nxn;
namely R- (R1×Lx/Wx+R2×) Ly/Wy+mX rv_nxn) =0;
let g (x, y) =r- (r1×lx/x+r2×ly/y+m×rv_nxn);
Wherein R is the total resistance of the winding path, lx is the path length of the transverse wire (i.e. the mesh number of the transverse wire in this embodiment), ly is the path length of the longitudinal wire (i.e. the mesh number of the longitudinal wire in this embodiment), rv_nxn is the resistance value of the through hole (i.e. the resistance value of the through hole with different dimensions), R1 is the square resistance value of the first metal layer Mn corresponding to the transverse wire, R2 is the square resistance value of the second metal layer mn+1 corresponding to the longitudinal wire, m is the number of times of invoking the through hole array via, n is the type of the through hole array via that needs to be matched (i.e. different through hole sizes), these two values are easy to obtain in the winding path, so we only need to determine the optimal solution of Wx and Wy, let the optimal solution condition be f (Wx, wy) = |wx-wy| minimum (x, y is used in the following description instead of Wx, wy, this optimal solution condition is abbreviated as f (x= |y), and n is the optimal solution is designed for the adjacent metal layer 25+ is designed to be more general, and the structure is more suitable for the same.
Let L (x, y, λ) =f (x, y) - λ×g (x, y), where λ is the lagrangian multiplier.
L (x, y, λ) derives from x, y, λ, respectively, i.e. (-)L/x,L/y,L/Λ), and the values of x, y, λ are obtained by setting the three values to 0, and the minimum value of f (x, y) is obtained.
In the embodiment, the Lagrangian multiplier method is adopted to process the optimization problem of the equality constraint and realize the calculation of the path width, but in other embodiments, based on different application scene requirements and different constraint conditions, other constraint optimization methods can be selected to realize the calculation of the path width, such as KKT conditions (Karush-Kuhn-Tucker Conditions) suitable for the optimization problem of the nonlinear inequality and equality constraint, a multiplier updating method suitable for the complex constraint optimization problem in combination with a penalty function and the Lagrangian multiplier method, even other sequence quadratic programming, an interior point method and the like, so as to process the specific constraint optimization problem. In some of these embodiments, after expanding the wiring width of the shortest path to generate the wiring path, further comprising:
In step S610, if the wiring width is smaller than the minimum wiring width of the corresponding metal layer in the wiring width information, the current task is processed again in step S232 after discarding the shortest path and updating the routing area.
Specifically, the winding width is smaller than the minimum winding width, the path is abandoned (the lattice points in the middle section are partially occupied), then the winding path is planned again, and iterative operation is performed until the winding width meets the minimum width requirement, so that a winding path which is not the optimal path is obtained, and the winding path is expanded and the lattice points are filled.
In addition, a length threshold of the shortest path can be defined, and when the length threshold is calculated by using the uniform grid winding algorithm, the shortest path smaller than the length threshold is abandoned, and the search is continued until the shortest path meeting the requirement of the defined length threshold is searched.
Step S620, if the wiring width is larger than the maximum winding width of the corresponding metal layer in the winding width information, judging whether the wiring width is within the preset redundancy value range, if so, confirming the winding path of the current task, and if not, reporting an abnormality.
Specifically, the wiring width is larger than the maximum winding width, and the reason for this phenomenon is that the subsequent winding path is changed due to occupation of the reference winding path, and the reason for the probability that the winding path is longer than the longest winding path defined in the preamble is likely to occur. The solution to this situation is to set a redundancy value for the maximum width (e.g. a maximum width of 4.5um as defined in the process, we define a maximum width of 4.0um in the algorithm, leaving a redundancy of 0.5 um) such that even if there is a winding path width exceeding the maximum winding width, the calculation based on the first pass uniform grid winding algorithm will not exceed much if the path width is exceeded. Thus, a redundancy value is maintained, allowing the path to be extended and filled normally without violating the rules in the process. In addition, the probability of occurrence of the case that the redundancy value is also exceeded is extremely small and can be ignored.
The present embodiment is described and illustrated below by way of preferred embodiments.
Fig. 4 is a preferred flowchart of the winding method based on the test structure design according to the present embodiment, as shown in fig. 5, the winding method based on the test structure design includes the following steps:
S1, taking a certain area as a target area which can be drawn by the layout, and generally taking the area as a rectangular area. The size of the grid is defined, see fig. 5, and the target area is divided into m×n grids (the number of grid points in practical application will be much larger than the number of grid points in the illustration). And defining forbidden areas and occupied areas in grids of the target area, assigning the grids of the forbidden areas and the occupied areas as 1, assigning the grids outside the forbidden areas as routing areas, and assigning the grids of the routing areas as 0. The frame position (grid marked by yellow) of the target area in fig. 5 is one of the forbidden areas, and the grid occupied by the subsequent test structure, the grid occupied by the bonding pad, and the like are all used as forbidden areas.
S2, referring to fig. 6 and 7, defining the areas of the test structure and the bonding pads, automatically calculating the central positions of the pins and the bonding pads of the test structure, and calculating the length and width of the current metal layer where the pins are located (the data may be used in the subsequent wiring width setting and path resistance value calculation to optimize the calculation results of the width and the resistance value of the pins). The connection relationship of each pin to the pad is defined, that is, the connection relationship of the pad 1 to the pin 1, the pad 2 to the pin 2 in fig. 7 is obtained.
S3, calculating the shortest path between each pin and each bonding pad one by taking one grid as a winding unit through a Less maze wiring algorithm (the embodiment is realized by the Less maze wiring algorithm, but other winding algorithms based on uniform grids can be realized, and the selection can be carried out according to different application scene requirements). (the path width at this time is only one grid, and different paths may overlap), see fig. 7, pin1 indicates pin1, pin2 indicates pin2, pad1 indicates pad1, pad2 indicates pad2, grid number information of X/Y direction routing of each shortest path is stored to be Lx/Ly, lx=x1+x2, ly=y1+y2 in the shortest path corresponding to pin2 and pad2 in fig. 7, and total routing path length=lx+ly.
S4, defining wiring information, namely setting the winding space of the wiring, defining the information of the metal layers and the through holes of the transverse and longitudinal wiring, and defining the square resistance value of the metal layers, for example:
the transverse metal wiring is Mn, R1 omega/square, and the maximum/minimum width is Wmax1/Wmin1 respectively.
The longitudinal metal wire is Mn+1, R2 omega/square, and the maximum/minimum width is Wmax2/Wmin2.
The through holes are ViaX, the through hole resistance of the size of 1 multiplied by 1 is about Rv_1X1Ω, the through hole resistance of the size of 2 multiplied by 2 is about Rv_2X1Ω, the through hole resistance of the size of 5 multiplied by 5 is about Rv_5X15Ω, the through holes are divided into arrays (namely different through hole sizes) of 1 multiplied by 1,2 multiplied by 2 and 5 multiplied by 5, in order to adapt to windings with different widths, in practical application, the specific value n of n multiplied by n can be obtained according to practical requirements, the method is not limited to the three types, and a script can automatically configure a proper through hole array for each section of winding through the comparison of the winding width and the widths of different through hole arrays.
S5, sorting the length=Lx+Ly value calculated in the step S3 from large to small, preferentially filling the largest winding path, setting the width of the largest winding path to be the maximum winding width (taking the lattice point occupied by the path as a central line to extend towards two sides), occupying the occupied lattice point (comprising the winding space required to be met in the process) after the line segment is extended, namely assigning the occupied lattice point to be changed from 0 to 1, assigning the unoccupied lattice point to be still 0, and filling the occupied lattice point with the metal layer defined in the step 7.
The number of square resistances of the transverse windings in the winding path is calculated to be Nsq _x=lx/Wmax 1.
The total resistance value rx= Nsq _x×r1 of the transverse windings is calculated.
And calculating the number of square resistances of the longitudinal windings in the winding path to be Nsq _y=ly/Wmax 2.
The total resistance value ry= Nsq _y×r2 of the longitudinal windings is calculated.
This routing path invokes a 5x5 array of vias m times, then the total via resistance rv=m×rv_5x5.
The total resistance of the winding is r=rx+ry+rv.
S6, sequencing the winding paths according to the path Length (except the calculated longest path), sequentially calculating one by one, considering that the former winding can influence the subsequent winding paths, and therefore, the winding paths can re-calculate the shortest path by using a Lee maze wiring algorithm, calculating the width of the current winding by taking the resistance value of the maximum winding path as a reference (enabling the total resistance value of the current winding to be the same as the resistance value of the maximum winding path or enabling the difference value of the resistance value of the maximum winding path to be not more than a preset threshold value as much as possible), and finally filling the required lattice points of the current winding. The method specifically comprises the following steps:
The following judgment processing is sequentially performed from the second path:
Determining whether the mesh that the path needs to occupy is already occupied:
if yes, calculating the shortest path again by using a Legend maze wiring algorithm, calculating the winding width by using a Lagrange multiplier method, expanding the winding path, judging the winding path, and if not, calculating the winding width by using the Lagrange multiplier method, expanding the winding path, and judging the winding path.
The winding path judging process comprises judging whether the grid occupied by the expanded winding path is occupied or not:
If not, the grid of the winding path is occupied to complete the winding task, if so, the winding width is calculated again by using the Lagrangian multiplier method and expanded to obtain a new winding path, or the shortest path is calculated again by using the Ligrangian maze wiring algorithm and the winding width is calculated again by using the Lagrangian multiplier method and expanded to obtain a new winding path until the new winding path meets the winding path judging process, namely, the required grid is unoccupied, and the winding task is completed after the new winding path is occupied.
According to the preferred embodiment, the array type test structure can automatically layout the optimal winding paths between the pins and the bonding pads when the array type test structure is connected in a bit line/word line mode, automatically avoid the existing winding and the area incapable of winding, provide an optimal solution for the winding width of each section, enable the winding width to be more reasonable and stable in process performance, and provide resistance calculation for each section of winding, so that the resistance value of each winding path is close.
It should be noted that the steps illustrated in the above-described flow or flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order other than that illustrated herein.
In this embodiment, a winding device based on a test structure design is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, which are not described herein. The terms "module," "unit," "sub-unit," and the like as used below may refer to a combination of software and/or hardware that performs a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware, are also possible and contemplated.
Fig. 8 is a block diagram of a winding device based on a test structure design according to the present embodiment, and as shown in fig. 8, the device includes a task acquisition module 10, a shortest path calculation module 20, and a path optimization module 30.
The task acquisition module 10 is configured to acquire a layout, determine a target area, and acquire a plurality of winding tasks in the target area, where the winding tasks include pins of a test structure to be subjected to winding connection and corresponding pads.
The shortest path calculation module 20 is configured to calculate, in the target area, a shortest path of each winding task.
The path optimization module 30 is configured to sequentially perform winding path optimization on each winding task based on preset wiring information and a shortest path until all the winding tasks are completed.
In some embodiments, the inside of the target area is divided into networks with the same size, a forbidden area, an occupied area and a routing area are defined in the target area, wherein the forbidden area comprises an edge grid of the target area, a grid occupied by a test structure and a grid occupied by a bonding pad, the occupied area comprises a grid occupied by an existing routing, and the rest area of the target area after the forbidden area and the occupied area are excluded is the routing area.
In some embodiments, the shortest path calculation module 20 is further configured to calculate, based on a uniform grid winding algorithm, a shortest path of each winding task in the routing area of the target area.
The shortest path is a connecting path occupying the least amount of grids, the connecting path is a path connecting pins of the test structure and corresponding bonding pads, and the path width of the shortest path is one grid.
The uniform grid winding algorithm comprises the steps of starting from a starting grid where the center position of a pin is located in a routing area, numbering adjacent grids in an ascending order, finally searching a termination grid where the center position of a bonding pad is located, and taking a path with the minimum number of the termination grid as a shortest path.
In some of these embodiments, the uniform mesh winding algorithm further includes defining a pin-out direction of the start mesh and/or the end mesh, adjacent meshes of the start mesh and/or the end mesh referring to adjacent meshes within the pin-out direction.
In some embodiments, the path optimization module 30 is further configured to obtain an incomplete winding task as a current task, confirm and/or optimize the shortest path of the current task based on the routing area, calculate to obtain a winding path according to the confirmed shortest path based on preset routing information and the routing area, fill a grid based on the winding path, complete the current task, and update the routing area, and continue to obtain the incomplete winding task as the current task until all the winding tasks are completed.
In some embodiments, the path optimization module 30 is further configured to obtain, as the current task, an incomplete winding task corresponding to the shortest path with the longest path length.
In some embodiments, the path optimization module 30 is further configured to obtain preset routing information, and specifically includes:
The method comprises the steps of obtaining winding width information comprising maximum winding widths and minimum winding widths of different metal layers, obtaining winding intervals of wiring, obtaining path resistance information comprising square resistance values of the different metal layers, resistance values of through holes with different sizes and winding resistance reference values, wherein one square refers to a grid, the different metal layers comprise a first metal layer along transverse wiring and a second metal layer along longitudinal wiring, and the through holes are used for connecting metal wiring in the first metal layer and the second metal layer.
In some embodiments, the path optimization module 30 is further configured to obtain a winding resistance reference value, and includes:
In all winding tasks, the shortest path with the largest path length is used as a reference path, the wiring width of the reference path is expanded based on the largest winding width of different metal layers to obtain a corresponding reference winding path, and the winding resistance value and the through hole resistance value of different metal layers in the reference winding path are calculated according to path resistance information to obtain the total winding resistance value of the reference winding path, namely the winding resistance reference value.
In some embodiments, the path optimization module 30 is further configured to perform grid filling based on the reference winding path, complete a corresponding winding task, and update the routing area.
In some embodiments, the path optimization module 30 is further configured to confirm the shortest path of the current task based on the routing area, or complete confirmation after optimizing the shortest path of the current task, and specifically includes step 1) of determining whether the grids of the shortest path of the current task are all in the routing area, if yes, confirming the shortest path, if not, discarding the shortest path, and updating the routing area based on the discarded shortest path.
Step 2) recalculating the shortest path of the current task and recalculating to the processing of step 1).
In some embodiments, the path optimization module 30 is further configured to implement the method including step 3) of expanding a wiring width of the shortest path based on the winding width information and the path resistance information to generate a winding path, wherein a difference between a path resistance value of the winding path and a winding resistance reference value satisfies a preset condition.
And step 4) judging whether grids of the winding paths are all in the wiring area, if yes, confirming the winding paths of the current task, if not, discarding the winding paths, and then restarting the processing in step 3), or discarding the shortest paths and updating the wiring area, and then confirming and/or optimizing the shortest paths again based on the wiring area.
In some of these embodiments, the path optimization module 30 is further configured to calculate, using a Lagrangian multiplier method, wiring widths of different metal layers in the shortest path to generate a wire-wound path, wherein a difference in wiring widths of adjacent metal layers is within a preset range.
In some embodiments, the path optimization module 30 is further configured to discard the shortest path and update the routing area, and then confirm and/or optimize the shortest path based on the routing area again if the wiring width is smaller than the minimum winding width of the corresponding metal layer in the winding width information, and determine whether the wiring width is within a preset redundancy value range if the wiring width is greater than the maximum winding width of the corresponding metal layer in the winding width information, confirm the winding path of the current task if the wiring width is within the preset redundancy value range, and report an exception if the wiring width is not within the preset redundancy value range.
The above-described respective modules may be functional modules or program modules, and may be implemented by software or hardware. For modules implemented in hardware, the modules may be located in the same processor, or may be located in different processors in any combination.
There is also provided in this embodiment a computer device comprising a memory in which a computer program is stored and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
Optionally, the computer device may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
It should be noted that, specific examples in this embodiment may refer to examples described in the foregoing embodiments and alternative implementations, and are not described in detail in this embodiment.
In addition, in combination with the winding method based on the test structure design provided in the above embodiment, a storage medium may be provided in this embodiment. The storage medium stores a computer program which when executed by a processor implements any of the test structure design based winding methods of the above embodiments.
It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure in accordance with the embodiments provided herein.
It is to be understood that the drawings are merely illustrative of some embodiments of the present application and that it is possible for those skilled in the art to adapt the present application to other similar situations without the need for inventive work. In addition, it should be appreciated that while the development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as a departure from the disclosure.
The term "embodiment" in this disclosure means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive. It will be clear or implicitly understood by those of ordinary skill in the art that the embodiments described in the present application can be combined with other embodiments without conflict.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
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